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Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
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Change subject: nb/via/cx700: Implement raminit
......................................................................
nb/via/cx700: Implement raminit
This brings the old raminit implementation for CX700 back. It was
removed in commit e99f0390b9b8 (Remove VIA CX700 northbridge sup-
port). The code is mostly unchanged, three minor issues are fixed:
* A shift (>>= 2) was missing when reading tRRD from SPD byte 28.
The fixed value matches what the vendor BIOS of a VIA EPIA-EX
board programs. The code also suggests that we are looking for
a small value (<= 19 for DDR2-533).
* We allow the board port to specify which clock outputs should
be enabled now. This is necessary for the VIA EPIA-EX, which
needs the ALL_MCLKO setting (instead of the previously hard-
coded MCLKO2.
* When programming the DQS output delays, we considered the 1~2
rank values only for single-rank configurations. Changing the
`< 2` to `<= 2` brings us closer to the vendor values on the
VIA EPIA-EX.
Otherwise a lot of cosmetics changed. Partly because the original
code was to be #included into another C file, but also to satisfy
checkpatch. Also, all the #if'd code was removed (32-bit width
option, ECC, etc.).
Change-Id: Ibc36b4f314cdf47f18c8be0fcb98218c50938e94
Signed-off-by: Nico Huber <nico.h(a)gmx.de>
---
M src/cpu/via/c7/Makefile.mk
M src/mainboard/via/epia-ex/devicetree.cb
M src/northbridge/via/cx700/Kconfig
M src/northbridge/via/cx700/Makefile.mk
A src/northbridge/via/cx700/chip.h
A src/northbridge/via/cx700/memmap.c
A src/northbridge/via/cx700/raminit.c
A src/northbridge/via/cx700/raminit.h
A src/northbridge/via/cx700/registers.h
M src/northbridge/via/cx700/romstage.c
10 files changed, 1,800 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/82770/3
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Change subject: nb/via/cx700: Implement FSB tuning
......................................................................
Patch Set 2:
(1 comment)
File src/northbridge/via/cx700/romstage.c:
https://review.coreboot.org/c/coreboot/+/82769/comment/76ce391a_040d81d2?us… :
PS2, Line 47: pci_write_config8(_sdev_host_ctrl, 0x4f, 0x01);
> Wasn't there one of these in bootblock? Or does it need to be done again?
There's one in `clock.c`, however that depends on early usage of the
timer framework. I don't know but could imagine that it doesn't run
with the bootblock console disabled. Also wasn't sure if putting it
into soc_early_bootblock_init() (instead of `clock.c`) would be early
enough. Just doing it here, potentially again, seemed safest.
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Change subject: mb/intel/archercity_crb: Deselect OCP drivers
......................................................................
Patch Set 1:
(1 comment)
File src/mainboard/intel/archercity_crb/Kconfig:
https://review.coreboot.org/c/coreboot/+/82169/comment/d02647cc_f9c17fde?us… :
PS1, Line 34: config MAINBOARD_OCP_COMPABILITY
> Can we name it as below? […]
Those names seem reasonable, but as Angel mentions, maybe the easier way is just to add a config file that enables this to the coreboot/configs folder. Feel free to reach out to me on google chat if you have any questions about that - gaumless@gmail.
Honestly, I'm not convinced that variants are the way to go. It's not a different board, just a different config.
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Change subject: mb/system76/mtl: Add Lemur Pro 13
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/system76/mtl/variants/lemp13/ramstage.c:
https://review.coreboot.org/c/coreboot/+/82788/comment/31d0e24d_fcfdec38?us… :
PS3, Line 14: params->EnableTcssCovTypeA[1] = 0x81;
: params->EnableTcssCovTypeA[3] = 0x85;
> Showing up as errors in jenkins: […]
Waiting on either Intel to release a Client FSP or Google to do whatever they do to update the headers to a newer version.
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Change subject: mb/asrock: Rename h77pro4-m to ivybridge
......................................................................
Patch Set 3: Code-Review-1
(1 comment)
Patchset:
PS3:
> Done
I agree with akjuxr3. Let's not set this precedent - I just don't see the need to rename it.
I'm not sure what "done" means in this context.
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Change subject: mb/system76/mtl: Add Lemur Pro 13
......................................................................
Patch Set 3:
(1 comment)
File src/mainboard/system76/mtl/variants/lemp13/ramstage.c:
https://review.coreboot.org/c/coreboot/+/82788/comment/c89c9a73_b0336d53?us… :
PS3, Line 14: params->EnableTcssCovTypeA[1] = 0x81;
: params->EnableTcssCovTypeA[3] = 0x85;
Showing up as errors in jenkins:
src/mainboard/system76/mtl/variants/lemp13/ramstage.c:14:10: error: no member named 'EnableTcssCovTypeA' in 'FSP_S_CONFIG'
14 | params->EnableTcssCovTypeA[1] = 0x81;
| ~~~~~~ ^
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Change subject: mb/system76/mtl: Add Darter Pro 10
......................................................................
Patch Set 5: Code-Review+2
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Change subject: console: Fix I2C/SMBus console if it's the only slow one
......................................................................
Patch Set 2:
(1 comment)
File src/include/console/console.h:
https://review.coreboot.org/c/coreboot/+/82761/comment/a972d056_3d38c721?us… :
PS1, Line 72: #define HAS_ONLY_FAST_CONSOLES !(CONFIG(SPKMODEM) || CONFIG(CONSOLE_QEMU_DEBUGCON) || \
: CONFIG(CONSOLE_SERIAL) || CONFIG(CONSOLE_NE2K) || CONFIG(CONSOLE_USB) || \
: CONFIG(EM100PRO_SPI_CONSOLE) || CONFIG(CONSOLE_SPI_FLASH) || \
: CONFIG(CONSOLE_SYSTEM76_EC) || CONFIG(CONSOLE_AMD_SIMNOW) || \
: CONFIG(CONSOLE_I2C_SMBUS))
> Would it make sense to replace this with a new `HAVE_SLOW_CONSOLE` Kconfig option (or something with […]
One could still miss to select it. But I guess it would look a lot nicer :)
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