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Change subject: [WIP] OptiPlex 3050 Micro port
......................................................................
Patch Set 14:
(3 comments)
File src/mainboard/dell/optiplex_3050/romstage.c:
https://review.coreboot.org/c/coreboot/+/82053/comment/0e06d822_b86e8ce1?us… :
PS14, Line 3: #include <assert.h>
maybe not used
https://review.coreboot.org/c/coreboot/+/82053/comment/1912251c_9f411cfb?us… :
PS14, Line 8: include <cbfs.h>
maybe not used
File src/mainboard/dell/optiplex_3050/sch5555_ec.c:
https://review.coreboot.org/c/coreboot/+/82053/comment/4ced6eb8_cca98ea2?us… :
PS14, Line 11: uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
: outb(tmp, SCH555x_EMI_IOBASE + 1);
not sure but maybe `pnp_unset_and_set_index` can be used ?
see device/pnp.h
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Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82053?usp=email
to look at the new patch set (#14).
Change subject: [WIP] OptiPlex 3050 Micro port
......................................................................
[WIP] OptiPlex 3050 Micro port
- Boots Linux
- SMSC SCH5553 SIO/EC
+ Early EC init + HWM init implemented
+ Console on serial port tested
+ TODO: late HWM init for fan control (fan runs at low speed now)
- Realtek Gigabit LAN works
- WiFi slot works
- NVMe SSD slot works
- Extra: LPSS UART0
+ Stock FW sets undocumented power gating bit, RTC battery needs to
be pulled for it to work.
+ Signals exposed on test points on the back of the board.
FIXME: add documentation about this
- Needs 'deguard' to bypass BootGuard
+ See https://review.coreboot.org/plugins/gitiles/deguard
- TODO: HDA verbs
- TODO: USB ports
- TODO: Add VBT
- Currently limited to the Micro form factor, but others are very
similar
Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2
Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com>
---
A src/mainboard/dell/optiplex_3050/Kconfig
A src/mainboard/dell/optiplex_3050/Kconfig.name
A src/mainboard/dell/optiplex_3050/Makefile.mk
A src/mainboard/dell/optiplex_3050/acpi/ec.asl
A src/mainboard/dell/optiplex_3050/acpi/superio.asl
A src/mainboard/dell/optiplex_3050/board_info.txt
A src/mainboard/dell/optiplex_3050/bootblock.c
A src/mainboard/dell/optiplex_3050/cmos.default
A src/mainboard/dell/optiplex_3050/cmos.layout
A src/mainboard/dell/optiplex_3050/devicetree.cb
A src/mainboard/dell/optiplex_3050/dsdt.asl
A src/mainboard/dell/optiplex_3050/gma-mainboard.ads
A src/mainboard/dell/optiplex_3050/include/early_gpio.h
A src/mainboard/dell/optiplex_3050/include/gpio.h
A src/mainboard/dell/optiplex_3050/ramstage.c
A src/mainboard/dell/optiplex_3050/romstage.c
A src/mainboard/dell/optiplex_3050/sch5555_ec.c
A src/mainboard/dell/optiplex_3050/sch5555_ec.h
18 files changed, 754 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/82053/14
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Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/82053?usp=email
to look at the new patch set (#13).
Change subject: [WIP] OptiPlex 3050 Micro port
......................................................................
[WIP] OptiPlex 3050 Micro port
- Boots Linux
- SMSC SCH5553 SIO/EC
+ Early EC init + HWM init implemented
+ Console on serial port tested
+ TODO: late HWM init for fan control (fan runs at low speed now)
- Realtek Gigabit LAN works
- WiFi slot works
- NVMe SSD slot works
- Extra: LPSS UART0
+ Stock FW sets undocumented power gating bit, RTC battery needs to
be pulled for it to work.
+ Signals exposed on test points on the back of the board.
FIXME: add documentation about this
- Needs 'deguard' to bypass BootGuard
+ See https://review.coreboot.org/plugins/gitiles/deguard
- TODO: HDA verbs
- TODO: USB ports
- TODO: Add VBT
- Currently limited to the Micro form factor, but others are very
similar
Change-Id: I8d443e39ee684a4eaa19c835a945cfe569c051e2
Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com>
---
A src/mainboard/dell/optiplex_3050/Kconfig
A src/mainboard/dell/optiplex_3050/Kconfig.name
A src/mainboard/dell/optiplex_3050/Makefile.mk
A src/mainboard/dell/optiplex_3050/acpi/ec.asl
A src/mainboard/dell/optiplex_3050/acpi/superio.asl
A src/mainboard/dell/optiplex_3050/board_info.txt
A src/mainboard/dell/optiplex_3050/bootblock.c
A src/mainboard/dell/optiplex_3050/cmos.default
A src/mainboard/dell/optiplex_3050/cmos.layout
A src/mainboard/dell/optiplex_3050/devicetree.cb
A src/mainboard/dell/optiplex_3050/dsdt.asl
A src/mainboard/dell/optiplex_3050/gma-mainboard.ads
A src/mainboard/dell/optiplex_3050/include/early_gpio.h
A src/mainboard/dell/optiplex_3050/include/gpio.h
A src/mainboard/dell/optiplex_3050/ramstage.c
A src/mainboard/dell/optiplex_3050/romstage.c
A src/mainboard/dell/optiplex_3050/sch5555_ec.c
A src/mainboard/dell/optiplex_3050/sch5555_ec.h
18 files changed, 754 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/82053/13
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Máté Kukri has posted comments on this change by Máté Kukri. ( https://review.coreboot.org/c/coreboot/+/82053?usp=email )
Change subject: [WIP] OptiPlex 3050 Micro port
......................................................................
Patch Set 12:
(6 comments)
This change is ready for review.
File src/mainboard/dell/optiplex_3050/Kconfig:
https://review.coreboot.org/c/coreboot/+/82053/comment/bde8c189_0d362918?us… :
PS11, Line 30: config PRERAM_CBMEM_CONSOLE_SIZE
: hex
: default 0xd00
> I suspect not, this is probably a copypasta leftover.
Gone
File src/mainboard/dell/optiplex_3050/acpi/dptf.asl:
PS11:
> Okay, I am not disagreeing, I'll get rid of it in the next patchset, I have no use for this.
Dptf gone
File src/mainboard/dell/optiplex_3050/cmos.default:
https://review.coreboot.org/c/coreboot/+/82053/comment/bb5478df_6b261f28?us… :
PS11, Line 6: nmi=Enable
> Not implemented for this platform, please drop
Done
File src/mainboard/dell/optiplex_3050/cmos.layout:
https://review.coreboot.org/c/coreboot/+/82053/comment/52d06430_17345091?us… :
PS11, Line 21: 408 1 e 1 nmi
> Not implemented for this platform, please drop
Done
File src/mainboard/dell/optiplex_3050/include/gpio.h:
https://review.coreboot.org/c/coreboot/+/82053/comment/11ab3257_eb72599c?us… :
PS11, Line 15: /* Pad configuration was generated automatically using intelp2m utility */
> I am planning on re-writing the GPIO table based on schematic.
Done
https://review.coreboot.org/c/coreboot/+/82053/comment/4bc843f4_08ba2f7d?us… :
PS11, Line 87: PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0_RXD */
> > `code indent should use tabs where possible` […]
Done
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Attention is currently required from: Jérémy Compostella, Paul Menzel, Shuo Liu, yuchi.chen(a)intel.com.
Hello Jérémy Compostella, Shuo Liu, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83192?usp=email
to look at the new patch set (#6).
The following approvals got outdated and were removed:
Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins)
Change subject: vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC
......................................................................
vc/intel/fsp/fsp2_0/snowridge: Add FSP headers for Snow Ridge SoC
Change-Id: I333b137c1dc08a3c06bdd3f7a78ca44a5dd043cc
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
A src/vendorcode/intel/fsp/fsp2_0/snowridge/FspUpd.h
A src/vendorcode/intel/fsp/fsp2_0/snowridge/FspmUpd.h
A src/vendorcode/intel/fsp/fsp2_0/snowridge/FspsUpd.h
A src/vendorcode/intel/fsp/fsp2_0/snowridge/FsptUpd.h
4 files changed, 1,385 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/83192/6
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Hello Jérémy Compostella, Paul Menzel, Shuo Liu, build bot (Jenkins), جوكر الطويل,
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/common: add CPU and PCIe IDs for Snow Ridge platform
......................................................................
soc/intel/common: add CPU and PCIe IDs for Snow Ridge platform
CPU and PCIe IDs are from Intel Atom Processor C5100, C5300,
P5300 and P5700 Product Families EDS, doc No. 575160 rev 2.0.
Change-Id: I3f5d612765bbe9adffe0b6c7a4151f32b33e88b4
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
M src/include/cpu/intel/cpu_ids.h
M src/include/device/pci_ids.h
M src/soc/intel/common/block/cpu/mp_init.c
M src/soc/intel/common/block/lpc/lpc.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/common/block/systemagent/systemagent.c
M src/soc/intel/common/block/xhci/xhci.c
7 files changed, 22 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/83314/5
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Change subject: soc/intel/snowridge: add support for Intel Atom Snow Ridge SoC
......................................................................
soc/intel/snowridge: add support for Intel Atom Snow Ridge SoC
Change-Id: I32ad836dfaaff0d1816eac41e5a7d19ece11080f
Signed-off-by: Yuchi Chen <yuchi.chen(a)intel.com>
---
A src/soc/intel/snowridge/Kconfig
A src/soc/intel/snowridge/Makefile.mk
A src/soc/intel/snowridge/acpi.c
A src/soc/intel/snowridge/acpi/hostbridges.asl
A src/soc/intel/snowridge/acpi/ith.asl
A src/soc/intel/snowridge/acpi/lpc.asl
A src/soc/intel/snowridge/acpi/pch_irqs.asl
A src/soc/intel/snowridge/acpi/pci_irqs.asl
A src/soc/intel/snowridge/acpi/pcie.asl
A src/soc/intel/snowridge/acpi/pcie_port.asl
A src/soc/intel/snowridge/acpi/pmc.asl
A src/soc/intel/snowridge/acpi/sata0.asl
A src/soc/intel/snowridge/acpi/sata2.asl
A src/soc/intel/snowridge/acpi/smbus.asl
A src/soc/intel/snowridge/acpi/southcluster.asl
A src/soc/intel/snowridge/acpi/uncore.asl
A src/soc/intel/snowridge/bootblock/bootblock.c
A src/soc/intel/snowridge/bootblock/bootblock.h
A src/soc/intel/snowridge/bootblock/early_uart_init.c
A src/soc/intel/snowridge/chip.c
A src/soc/intel/snowridge/chip.h
A src/soc/intel/snowridge/common/fsp_hob.c
A src/soc/intel/snowridge/common/fsp_hob.h
A src/soc/intel/snowridge/common/gpio.c
A src/soc/intel/snowridge/common/hob_display.c
A src/soc/intel/snowridge/common/kti_cache.c
A src/soc/intel/snowridge/common/kti_cache.h
A src/soc/intel/snowridge/common/pmclib.c
A src/soc/intel/snowridge/common/reset.c
A src/soc/intel/snowridge/common/spi.c
A src/soc/intel/snowridge/common/uart8250mem.c
A src/soc/intel/snowridge/common/uart8250mem.h
A src/soc/intel/snowridge/common/upd_display.c
A src/soc/intel/snowridge/cpu.c
A src/soc/intel/snowridge/finalize.c
A src/soc/intel/snowridge/heci.c
A src/soc/intel/snowridge/hob_iiouds.h
A src/soc/intel/snowridge/hqm.c
A src/soc/intel/snowridge/include/soc/acpi.h
A src/soc/intel/snowridge/include/soc/cpu.h
A src/soc/intel/snowridge/include/soc/gpio.h
A src/soc/intel/snowridge/include/soc/gpio_defs.h
A src/soc/intel/snowridge/include/soc/gpio_snr.h
A src/soc/intel/snowridge/include/soc/gpmr.h
A src/soc/intel/snowridge/include/soc/iomap.h
A src/soc/intel/snowridge/include/soc/irq.h
A src/soc/intel/snowridge/include/soc/itss.h
A src/soc/intel/snowridge/include/soc/lpc.h
A src/soc/intel/snowridge/include/soc/msr.h
A src/soc/intel/snowridge/include/soc/nvs.h
A src/soc/intel/snowridge/include/soc/p2sb.h
A src/soc/intel/snowridge/include/soc/pci_devs.h
A src/soc/intel/snowridge/include/soc/pci_ids.h
A src/soc/intel/snowridge/include/soc/pcr_ids.h
A src/soc/intel/snowridge/include/soc/pm.h
A src/soc/intel/snowridge/include/soc/pmc.h
A src/soc/intel/snowridge/include/soc/sata.h
A src/soc/intel/snowridge/include/soc/smbus.h
A src/soc/intel/snowridge/include/soc/soc_chip.h
A src/soc/intel/snowridge/include/soc/systemagent.h
A src/soc/intel/snowridge/lockdown.c
A src/soc/intel/snowridge/lpc.c
A src/soc/intel/snowridge/memmap.c
A src/soc/intel/snowridge/nis.c
A src/soc/intel/snowridge/qat.c
A src/soc/intel/snowridge/ramstage.h
A src/soc/intel/snowridge/romstage/gpio_snr.c
A src/soc/intel/snowridge/romstage/romstage.c
A src/soc/intel/snowridge/sata.c
A src/soc/intel/snowridge/smihandler.c
A src/soc/intel/snowridge/sriov.c
A src/soc/intel/snowridge/systemagent.c
72 files changed, 5,844 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/83321/7
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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to look at the new patch set (#3).
Change subject: commonlib/device_tree.c: Add read reg property helper
......................................................................
commonlib/device_tree.c: Add read reg property helper
Add a helper function to read the reg property.
It is based on our fdt_read_reg_prop(...) function.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I7846eb8af390d709b0757262025cb819e9988699
---
M src/commonlib/device_tree.c
M src/commonlib/include/commonlib/device_tree.h
2 files changed, 59 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/83457/3
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