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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
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Change subject: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
......................................................................
csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
Conveniently and securely gets, checks SHA256 and installs some of my
patches from this page - https://review.coreboot.org/q/status:open+banon
- and also gets a collection of useful floppy-based operating systems.
More info at http://dangerousprototypes.com/docs/Lenovo_G505S_hacking
Sometimes it takes quite a long time to get a patch merged, while the
people might need it today! - and this script could be really helpful.
It asks a [Y/N] question for every addition, and since there are some
"universal" patches as well as great floppies, you may still want to
run this script - even if your board is not Lenovo G505S or not AMD.
Use restore_agesa.sh script to restore AMD AGESA boards before running.
Please share your feedback and tell me about the other useful patches,
preferably the "universal" ones - i.e. SeaBIOS. Currently included:
1) "board-specific": Lenovo G505S discrete GPU support, board-specific
SeaBIOS options, known good AtomBIOS ROMs, good IRQ routing for AMD
Lenovo G505S, ASUS A88XM-E and AM1I-A boards, example configs for
G505S / AM1I-A / A88XM-E, and avoid the apu/amdfw wasting CBFS space.
2) "universal": SeaBIOS patches: advanced_bootmenu, multiple_floppies,
smbios_mptable_768; a floppies collection: KolCrpt, KolibriOS, FreeDOS,
MichalOS, Visopsys, Snowdrop, Fiwix, Memtest, Tatos, Plop, FloppyBird.
Run ./csb_patcher.sh help or ./csb_patcher.sh usage for more usage info.
Send all your questions/suggestions to [ mikebdp2 [at] gmail [d0t] c0m ]
Change-Id: Ia392bad869a82707380d3a1e3c51b3e15f4f02f2
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
---
A csb_patcher.sh
1 file changed, 1,115 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/64873/23
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Change subject: configs: add ASUS A88XM-E sample configuration
......................................................................
configs: add ASUS A88XM-E sample configuration
This sample .config can be used ONLY if your git clone'd (and also
git reset --hard to the revision mentioned at restore_agesa.sh script)
coreboot source code has been processed with the following scripts:
restore_agesa.sh - https://review.coreboot.org/c/coreboot/+/79838
csb_patcher.sh - https://review.coreboot.org/c/coreboot/+/64873
More info at http://dangerousprototypes.com/docs/Lenovo_G505S_hacking
After you have executed the scripts above, you can use this .config
as the base config for your A88XM-E by saving it to ./coreboot/.config -
however, you may want to change some of its' configs! I.e. if you are
using a SSD, you may want to change the "CONFIG_HUDSON_SATA_MODE"
from "0: NATIVE" to "2: AHCI". Also, I have disabled the Intel WiFi
at this .config to save space ( CONFIG_DRIVERS_INTEL_WIFI is not set ).
Send all your questions/suggestions to [ mikebdp2 [at] gmail [d0t] c0m ]
Change-Id: Ie180e498a90d8a1c8380f18c77c5a6be0a731c2c
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
---
A configs/config.asus_a88xm-e
1 file changed, 705 insertions(+), 0 deletions(-)
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Change subject: mb/clevo/cml-u/dt: Make use of chipset devicetree
......................................................................
mb/clevo/cml-u/dt: Make use of chipset devicetree
Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: Ifc882c2ac9d4e9ce2ed4305bdd6859a5d1e1b09c
Signed-off-by: Felix Singer <felixsinger(a)posteo.net>
---
M src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb
1 file changed, 15 insertions(+), 53 deletions(-)
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Change subject: configs: add ASUS AM1I-A sample configuration
......................................................................
configs: add ASUS AM1I-A sample configuration
This sample .config can be used ONLY if your git clone'd (and also
git reset --hard to the revision mentioned at restore_agesa.sh script)
coreboot source code has been processed with the following scripts:
restore_agesa.sh - https://review.coreboot.org/c/coreboot/+/79838
csb_patcher.sh - https://review.coreboot.org/c/coreboot/+/64873
More info at http://dangerousprototypes.com/docs/Lenovo_G505S_hacking
After you have executed the scripts above, you can use this .config
as the base config for your AM1I-A by saving it to ./coreboot/.config -
however, you may want to change some of its' configs! I.e. if you are
using a SSD, you may want to change the "CONFIG_HUDSON_SATA_MODE"
from "0: NATIVE" to "2: AHCI". Also, I have disabled the Intel WiFi
at this .config to save space ( CONFIG_DRIVERS_INTEL_WIFI is not set ).
Send all your questions/suggestions to [ mikebdp2 [at] gmail [d0t] c0m ]
Change-Id: Ib184333f0e800f6b6e92195bf44e1780edc5d14c
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
---
A configs/config.asus_am1i-a
1 file changed, 706 insertions(+), 0 deletions(-)
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Change subject: configs: add Lenovo G505S sample configuration (use with dGPU patches)
......................................................................
configs: add Lenovo G505S sample configuration (use with dGPU patches)
This sample .config can be used ONLY if your git clone'd (and also
git reset --hard to the revision mentioned at restore_agesa.sh script)
coreboot source code has been processed with the following scripts:
restore_agesa.sh - https://review.coreboot.org/c/coreboot/+/79838
csb_patcher.sh - https://review.coreboot.org/c/coreboot/+/64873
More info at http://dangerousprototypes.com/docs/Lenovo_G505S_hacking
After you have executed the scripts above, you can use this .config
as the base config for your G505S by saving it to ./coreboot/.config -
however, you may want to change some of its' configs! I.e. it specifies
CONFIG_VGA_BIOS_DGPU_FILE="pci1002,6665.rom"
CONFIG_VGA_BIOS_DGPU_ID="1002,6665"
which is compatible with R5-M230 dGPU, but if your G505S has HD-8570M
discrete GPU instead - you will need to change these configs to ",6663".
Or, if your G505S does not have a discrete GPU at all, please disable
CONFIG_AMD_DGPU_WITHOUT_EEPROM=y
and those DGPU configs will be disabled. Also, if you are using a SSD -
may want to change the "CONFIG_HUDSON_SATA_MODE" from "0: NATIVE" to
"2: AHCI". Also I've disabled the Intel WiFi at my .config to save space
( CONFIG_DRIVERS_INTEL_WIFI is not set ).
Send all your questions/suggestions to [ mikebdp2 [at] gmail [d0t] c0m ]
Change-Id: Id7d07303d98f795ca699d1955574a01dc9c87d1a
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
---
A configs/config.lenovo_g505s_use_with_dgpu_patches
1 file changed, 697 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/79839/5
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/64873?usp=email
to look at the new patch set (#22).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
......................................................................
csb_patcher.sh: gets,checks,installs the coreboot and SeaBIOS patches
Conveniently and securely gets, checks SHA256 and installs some of my
patches from this page - https://review.coreboot.org/q/status:open+banon
- and also gets a collection of useful floppy-based operating systems.
More info at http://dangerousprototypes.com/docs/Lenovo_G505S_hacking
Sometimes it takes quite a long time to get a patch merged, while the
people might need it today! - and this script could be really helpful.
It asks a [Y/N] question for every addition, and since there are some
"universal" patches as well as great floppies, you may still want to
run this script - even if your board is not Lenovo G505S or not AMD.
Use restore_agesa.sh script to restore AMD AGESA boards before running.
Please share your feedback and tell me about the other useful patches,
preferably the "universal" ones - i.e. SeaBIOS. Currently included:
1) "board-specific": Lenovo G505S discrete GPU support, board-specific
SeaBIOS options, known good AtomBIOS ROMs, good IRQ routing for AMD
Lenovo G505S, ASUS A88XM-E and AM1I-A boards, example configs for
G505S / AM1I-A / A88XM-E, and avoid the apu/amdfw wasting CBFS space.
2) "universal": SeaBIOS patches: advanced_bootmenu, multiple_floppies,
smbios_mptable_768; a floppies collection: KolCrpt, KolibriOS, FreeDOS,
MichalOS, Visopsys, Snowdrop, Fiwix, Memtest, Tatos, Plop, FloppyBird.
Run ./csb_patcher.sh help or ./csb_patcher.sh usage for more usage info.
Send all your questions/suggestions to [ mikebdp2 [at] gmail [d0t] c0m ]
Change-Id: Ia392bad869a82707380d3a1e3c51b3e15f4f02f2
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
---
A csb_patcher.sh
1 file changed, 1,115 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/64873/22
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Anastasios Koutian has posted comments on this change by Anastasios Koutian. ( https://review.coreboot.org/c/coreboot/+/83280?usp=email )
Change subject: mb/lenovo/t420: Use vendor default power limits
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> Would be good to check the values when using a dual-core CPU and a quad-core CPU
The T420 was only produced with 35 Watt chips, so I think it's safe to assume the power limits would be the same.
Not sure about the other values.
I do have a spare T420 motherboard as well as a couple of dual core i5s that I could test with. However they are in storage and I do not have access to them right now.
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Change subject: cpu/intel/model_206ax: Allow package power limit clamping
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83270/comment/b8ce70dd_bedc6440?us… :
PS5, Line 8:
> Please explain what it does. […]
From "Intel® 64 and IA-32 Architectures Software Developer’s Manual Volume 3B: System Programming Guide, Part 2", section 14.9.3, page 14-33:
"Package Clamping Limitation #1 (bit 16): Allow going below OS-requested P/T state setting during time window specified by bits 23:17."
"Package Clamping Limitation #2 (bit 48): Allow going below OS-requested P/T state setting during time window specified by bits 23:17."
So basically it turns PL1/PL2 respectively into a hard constraint and slows down the CPU a much as possible in order to satisfy the power limit.
If, for example, PL1 clamp is disabled, the CPU might decide to exceed PL1. Same for PL2.
I tested this with the i7-3940XM, by running a combined stress test for CPU cores and integrated graphics:
`$ stress-ng -c 8 --cpu-method matrixprod`
`$ furmark --fullscreen --p1080 --demo furmark-gl`
With the PL1 clamp disabled, after several minutes of running the two commands simultaneously, the core frequency is 3.0 GHz, graphics frequency is 650 MHz, and package power consumption levels out at ~42 W, which means that the CPU decides to violate the PL1 = 35 W constraint.
When the PL1 clamp is enabled, for the same stress test, core frequency is 2.7 GHz, graphics are at 540 MHz, and package power stabilises at 35 W, which means that PL1 is being enforced.
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Attention is currently required from: Balázs Vinarz, Mike Banon, Vlado Ilic.
Hello Balázs Vinarz, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: restore_agesa.sh - restores the opensource AMD AGESA boards
......................................................................
restore_agesa.sh - restores the opensource AMD AGESA boards
restore_agesa.sh reverts the opensource AGESA AMD boards removal
that happened after 5e8e911b7caee021faff96c4e82a77a42544ea62
commit (0 point of history, or 0 PoH) - by git-reverting:
1) the "bad commits" (marked as "CBF" = coreboot build failure)
- that either remove or break a code needed for our boards
2) the "unlucky commits" (marked as "GRF" = git revert failure)
- that are a roadblock for git-reverting the "bad commits"
Right now at 88bc0f1604494de0f87c6954c050e7ef4d1c4457 (7153 PoH),
it takes 57 CBF git reverts - just 1% of 7153 commits since the
OSS AGESA removal! - making this removal look questionable and
the idea of opensource AGESA AMD boards restoration viable.
SUCCESSFUL BOOT TESTS for the opensource AGESA boards which I own
(Lenovo G505S - fam15 laptop, ASUS A88XM-E - fam15 desktop,
ASUS AM1I-A - fam16 desktop) :
88bc0f1604494de0f87c6954c050e7ef4d1c4457 (7153 PoH) for Lenovo G505S
1879b6a34a6e93a93d691a0d9f2457d6251a17c1 (6092 PoH) for ASUS AM1I-A
1879b6a34a6e93a93d691a0d9f2457d6251a17c1 (6092 PoH) for ASUS A88XM-E
69ffebf5ccf123bc0b3fb28b485985af0597761d (3698 PoH) for ASUS A88XM-E
NOTE for A88XM-E and AM1I-A: may be a bootable USB detection problem
if you add too many floppy images (csb_patcher.sh) to a coreflop ROM
Change-Id: Ia97e80ffaad9459e54ff5cb01f20d9129241433c
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
---
A restore_agesa.sh
1 file changed, 573 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/79838/16
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Change subject: [WIP] OptiPlex 3050 Micro port
......................................................................
Patch Set 14:
(7 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82053/comment/71c8617c_f25b7323?us… :
PS14, Line 7: [WIP]
> Should this be removed before submitting?
USB ports are still TODO, and I would like to get late HWM init in too for fan control. Will remove the WIP when ready for submitting.
File src/mainboard/dell/optiplex_3050/cmos.layout:
https://review.coreboot.org/c/coreboot/+/82053/comment/252771e2_d764e124?us… :
PS14, Line 25: 416 128 r 0 vbnv
> Does this board use vboot/ChromeOS?
I guess it can in theory, but I have no such intentions, so not against removing it.
File src/mainboard/dell/optiplex_3050/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/82053/comment/c9956ceb_f193376b?us… :
PS14, Line 13: register "PrimaryDisplay" = "Display_iGFX"
> Is this needed? It's not wrong, though.
I suspect that it is not needed.
https://review.coreboot.org/c/coreboot/+/82053/comment/460ade89_5f57f6c0?us… :
PS14, Line 18: OC0
> That's a lot of ports on OC0, it feels wrong
Yeah it is definitely wrong, I still need to fix the USB ports, that's just bad copypasta
https://review.coreboot.org/c/coreboot/+/82053/comment/53ad5cec_933618e5?us… :
PS14, Line 55: device ref pcie_rp21 on
> Which device is this? Would be nice to add a comment
Will do, I think this is the M.2 SSD port if I remember correctly.
File src/mainboard/dell/optiplex_3050/ramstage.c:
https://review.coreboot.org/c/coreboot/+/82053/comment/b2b4775c_9ce9c6de?us… :
PS14, Line 11: static void init_mainboard(void *chip_info)
: {
: }
:
: struct chip_operations mainboard_ops = {
: .init = init_mainboard,
: };
> If this does nothing, is it needed? Should GPIOs be configured in there?
Not needed, no.
File src/mainboard/dell/optiplex_3050/sch5555_ec.c:
https://review.coreboot.org/c/coreboot/+/82053/comment/6fa6b522_17f04b3f?us… :
PS14, Line 11: uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
: outb(tmp, SCH555x_EMI_IOBASE + 1);
> not sure but maybe `pnp_unset_and_set_index` can be used ? […]
This isn't PNP, this is a dedicated I/O window for the EC that is mapped via a BAR in PNP config space.
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