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Change subject: mb/google/trulo/var/orisa: Fill in ec.h
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/83154/comment/5de7e61d_9b6e9213?us… :
PS2, Line 7: for orisa
> Redundant.
Done
https://review.coreboot.org/c/coreboot/+/83154/comment/39e80921_57837148?us… :
PS2, Line 8:
> Please document the source for this.
Done
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Hello Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83154?usp=email
to look at the new patch set (#3).
Change subject: mb/google/trulo/var/orisa: Fill in ec.h
......................................................................
mb/google/trulo/var/orisa: Fill in ec.h
Fill in ec.h according to schematic_20240614.
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: Ie1edf655fd20c0c1baee01fa90ed03501e3fe161
Signed-off-by: Amanda Huang <amanda_hwang(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/orisa/include/variant/ec.h
1 file changed, 70 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/83154/3
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Change subject: tree: Use pkgconf over pkg-config
......................................................................
Patch Set 4:
(1 comment)
File tests/data/lib/lzma-test/data.2.bin:
https://review.coreboot.org/c/coreboot/+/83157/comment/a704151a_d1ebc1c4?us… :
PS1, Line 52: * pkgconf
> Thx
You can probably drop `ibs=1`, but `skip=8` is mandatory to drop header from binary data. Also `data.{1,3,4}.lzma.bin` do not need to be regenerated as their uncompressed versions do not change. So commands below should solve the issue:
```
util/cbfs-compression-tool compress tests/data/lib/lzma-test/data.2.bin /tmp/file.lzma.bin lzma ;
dd if=/tmp/file.lzma.bin of=tests/data/lib/lzma-test/data.2.lzma.bin skip=8
```
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Change subject: mb/lenovo: Add ThinkCentre M920q (Coffee Lake)
......................................................................
Patch Set 10:
(1 comment)
File src/mainboard/lenovo/m920q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80609/comment/a6a39c06_5bf66bcf?us… :
PS10, Line 33: //
> I'd use "#" […]
It won't work. This has to be a valid C comment.
This comment is inside the value of `usb2_ports`, and will appear verbatim inside `static.c`. If using a `#` "comment" here, the compiler will complain about "unknown preprocessor directive" because `# Internal USB header` is most certainly not a comment in C.
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Change subject: mb/lenovo: Add ThinkCentre M920q (Coffee Lake)
......................................................................
Patch Set 10: Code-Review+1
(10 comments)
Patchset:
PS10:
Ah, I just saw you added docs.
File Documentation/mainboard/lenovo/m920q.md:
https://review.coreboot.org/c/coreboot/+/80609/comment/93946f4b_7b30607d?us… :
PS10, Line 1: # Dell OptiPlex 9010
Ahem.
```suggestion
# Lenovo M920 Tiny
```
https://review.coreboot.org/c/coreboot/+/80609/comment/e637b452_bd559420?us… :
PS10, Line 9: 8nd Gen or 9rd Gen
Oof, copy-pasta error? ("2***nd*** Gen or 3***rd*** Gen)
```suggestion
| CPU | Intel Core 8th Gen or 9th Gen (Coffee Lake (Refresh)) |
```
https://review.coreboot.org/c/coreboot/+/80609/comment/75537d77_5b281acb?us… :
PS10, Line 11: DIMM
```suggestion
| DRAM | 2 SO-DIMM slots, DDR4-2400/2666 |
```
https://review.coreboot.org/c/coreboot/+/80609/comment/66fe8fdc_b6f54d82?us… :
PS10, Line 45: yes?
I feel this could confuse people into believing that installing coreboot via the internal programmer is working. How about:
```suggestion
| Internal flashing | after flashing coreboot |
```
https://review.coreboot.org/c/coreboot/+/80609/comment/08a4ed04_9563cf70?us… :
PS10, Line 53: flashrom -p internal -w coreboot.rom --ifd -i bios
I thought one needs `--noverify-all` too?
https://review.coreboot.org/c/coreboot/+/80609/comment/b47ed278_d682af1d?us… :
PS10, Line 55: will
Huh? Will... Will what? The sentence doesn't quite parse, could you please check it?
https://review.coreboot.org/c/coreboot/+/80609/comment/e560c9b4_2d365be7?us… :
PS10, Line 71: BIOS1 and BIOS1
I hope they're not marked the same 😄
```suggestion
The flash chips are marked on the mainboard as BIOS1 and BIOS2 respectively.
```
https://review.coreboot.org/c/coreboot/+/80609/comment/123475db_c46738c9?us… :
PS10, Line 85: - PCIe x8 port
This port works, but see comments about riser problems.
File src/mainboard/lenovo/m920q/Kconfig:
https://review.coreboot.org/c/coreboot/+/80609/comment/0df8394d_20c5fa7d?us… :
PS10, Line 33: 0x900000
If this was 0x800000 instead, then by default one could flash only the second flash chip (8 MiB) externally. I find this quite convenient as it reduces the chances of messing up the IFD/ME.
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Change subject: mb/lenovo: Add ThinkCentre M920q (Coffee Lake)
......................................................................
Patch Set 10:
(3 comments)
File src/mainboard/lenovo/m920q/bootblock.c:
https://review.coreboot.org/c/coreboot/+/80609/comment/f7917210_4f269b59?us… :
PS10, Line 5: #include <mainboard/gpio.h>
: #include <soc/gpio.h>
not used if I'm not wrong
File src/mainboard/lenovo/m920q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80609/comment/ca7f4989_819a7e91?us… :
PS10, Line 33: //
I'd use "#"
same style used for comments here
File src/mainboard/lenovo/m920q/romstage.c:
https://review.coreboot.org/c/coreboot/+/80609/comment/cdcdc876_4efce30a?us… :
PS10, Line 3: <cf9_reset.h>
: #include <console/console.h>
: #include <cpu/cpu.h>
: #include <cpu/x86/msr.h>
: #include <soc/cnl_memcfg_init.h>
: #include <soc/romstage.h>
: #include <types.h>
please check and remove unused includes
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Change subject: mb/lenovo: Add ThinkCentre M920q (Coffee Lake)
......................................................................
Patch Set 10: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80609/comment/8330c64d_6791687d?us… :
PS10, Line 26: - PCIe x8 port
Tested by `dnssound.` on the coreboot Discord using a `BA7H70 Rev 1.2` riser and an Intel `X540-T2 10G` dual 10GbE card (PCIe x8).
What remains untested, however, is a different riser with a PCIe x4 connector. On that riser, the PCIe lanes come from the PCH for some reason.
File src/mainboard/lenovo/m920q/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/80609/comment/04fbc778_3de0847f?us… :
PS7, Line 15: device ref peg0 on end # Slot JP3 - not tested
> Done
Update: The `BA7H70 Rev 1.2` riser works properly
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Hello Jakub Czapiga, Julius Werner, Martin L Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/83157?usp=email
to look at the new patch set (#4).
Change subject: tree: Use pkgconf over pkg-config
......................................................................
tree: Use pkgconf over pkg-config
Change-Id: I3e9a92d019854214a5760f705b9cbe3cabe6d2e8
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M Documentation/tutorial/part1.md
M Makefile
M payloads/external/GRUB2/Makefile
M tests/data/lib/lzma-test/data.1.lzma.bin
M tests/data/lib/lzma-test/data.2.bin
M tests/data/lib/lzma-test/data.2.lzma.bin
M tests/data/lib/lzma-test/data.3.lzma.bin
M tests/data/lib/lzma-test/data.4.lzma.bin
M util/amdfwtool/Makefile.mk
M util/cbfstool/lz4/lib/README.md
M util/coreboot-configurator/contrib/debian/control
M util/futility/Makefile.mk
M util/kconfig/mconf-cfg.sh
M util/kconfig/nconf-cfg.sh
M util/msrtool/configure
M util/nixshell/devshell-i386.nix
16 files changed, 17 insertions(+), 18 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/83157/4
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Change subject: mb/emulation/qemu-riscv/cbmem.c: Fix device_tree.h include
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Merging early and out of order as this is a trivial fix.
Please base such fixes directly on main in the future. Otherwise, we can
get inaccurate CI results, which seems to be the cause of the issue at hand.
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