coreboot-gerrit June 2024

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[M] Change in coreboot[main]: device/azalia: Separate codec checking and initialization
by Elyes Haouas (Code Review) 22 Jun '24

22 Jun '24

Attention is currently required from: Felix Held, Felix Singer, Nicholas Sudsgaard, Paul Menzel. Elyes Haouas has posted comments on this change by Nicholas Sudsgaard. ( https://review.coreboot.org/c/coreboot/+/80332?usp=email ) Change subject: device/azalia: Separate codec checking and initialization ...................................................................... Patch Set 9: (1 comment) File src/device/azalia_device.c: https://review.coreboot.org/c/coreboot/+/80332/comment/2ca06a33_1c590dbf?us… : PS5, Line 249: u32 > yes, that's a separate logical change, so please do that in a follow-up Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/80332?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92b6d184abccdbe0e1bfce98a2c959a97a618a29 Gerrit-Change-Number: 80332 Gerrit-PatchSet: 9 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 23 Jun 2024 06:57:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[L] Change in coreboot[main]: mb/lenovo: Add ThinkCentre M920q (Coffee Lake)
by Elyes Haouas (Code Review) 22 Jun '24

22 Jun '24

Attention is currently required from: Alexander Couzens, Maciej Pijanowski, Michał Kopeć, Paul Menzel. Elyes Haouas has posted comments on this change by Maciej Pijanowski. ( https://review.coreboot.org/c/coreboot/+/80609?usp=email ) Change subject: mb/lenovo: Add ThinkCentre M920q (Coffee Lake) ...................................................................... Patch Set 10: (1 comment) Patchset: PS10: Thx -- To view, visit https://review.coreboot.org/c/coreboot/+/80609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iea1dc5745c0ecf687fa18b793f0aab4b0855d6d4 Gerrit-Change-Number: 80609 Gerrit-PatchSet: 10 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Comment-Date: Sun, 23 Jun 2024 06:53:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: skl mainboards/dt: Move SATA related settings into SATA device scope
by Felix Singer (Code Review) 22 Jun '24

22 Jun '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83179?usp=email ) Change subject: skl mainboards/dt: Move SATA related settings into SATA device scope ...................................................................... skl mainboards/dt: Move SATA related settings into SATA device scope Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 11 files changed, 100 insertions(+), 87 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/83179/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 7a77e64..1f2fa40 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -30,15 +30,6 @@ register "dptf_enable" = "0" # FSP Configuration - register "SataSalpSupport" = "1" - - # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "1" - register "SataPortsDevSlp[1]" = "1" - register "SataPortsDevSlp[2]" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" @@ -106,7 +97,21 @@ end device ref thermal on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + + # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2 + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + end device ref pcie_rp3 on end device ref pcie_rp4 on end device ref pcie_rp9 on end diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 854b887..c41a26f 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -32,11 +32,6 @@ register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - }" - # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch # SLP_S3 Minimum Assertion Width. Values 0: 60us, 1: 1ms, 2: 50ms, 3: 2s register "PmConfigSlpS3MinAssert" = "2" @@ -209,7 +204,10 @@ device ref south_xdci on end device ref thermal on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + end device ref pcie_rp3 on end # x1 baseboard WWAN device ref pcie_rp6 on end # x1 baseboard i210 device ref pcie_rp9 on end # x4 FPGA diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 7d11653..9458c81 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -59,9 +59,6 @@ register "s0ix_enable" = true # FSP Configuration - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[1]" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "SkipExtGfxScan" = "1" @@ -359,7 +356,13 @@ device ref i2c0 on end device ref i2c2 on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + }" + register "SataPortsDevSlp[1]" = "1" + end device ref uart2 on end device ref i2c5 on end device ref pcie_rp1 on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index f2e569d..49edccb 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -47,17 +47,6 @@ register "SsicPortEnable" = "1" - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - [4] = 1, - [5] = 1, - [6] = 1, - [7] = 1, - }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -112,7 +101,19 @@ device ref sa_thermal off end device ref i2c2 off end device ref i2c3 off end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end device ref i2c4 off end device ref emmc off end device ref sdxc off end diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb index 87bf0d8..99963bf 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb @@ -1,11 +1,5 @@ chip soc/intel/skylake - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - }" - # Enable deep Sx states register "deep_s5_enable_ac" = "1" register "deep_s5_enable_dc" = "1" @@ -155,7 +149,13 @@ end device ref i2c2 off end device ref i2c3 off end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + }" + end device ref pcie_rp3 on end device ref pcie_rp4 on end device ref pcie_rp5 on end diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 8e70c1e..5516fee 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -98,18 +98,6 @@ register "SsicPortEnable" = "1" # Enable SSIC for WWAN - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - [4] = 1, - [5] = 1, - [6] = 1, - [7] = 1, - }" - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -164,7 +152,19 @@ end device ref i2c2 off end device ref i2c3 off end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end device ref i2c4 off end device ref pcie_rp1 off end device ref pcie_rp3 on end diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 067cb59..73df651 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -130,17 +130,6 @@ # Must leave UART0 enabled or SD/eMMC will not work as PCI - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - [4] = 1, - [5] = 1, - [6] = 1, - [7] = 1, - }" register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -205,7 +194,19 @@ device ref i2c2 on end device ref i2c3 on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end device ref uart2 on end device ref i2c5 on end device ref i2c4 on end diff --git a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb index 6657fa9..b6b3574 100644 --- a/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb +++ b/src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb @@ -8,8 +8,6 @@ register "PcieRpEnable[ 3]" = "1" register "PcieRpEnable[11]" = "1" - register "SataPortsEnable[3]" = "1" - device domain 0 on device ref south_xhci on register "usb2_ports" = "{ @@ -26,6 +24,9 @@ [3] = USB3_PORT_DEFAULT(OC1), }" end + device ref sata on + register "SataPortsEnable[3]" = "1" + end device ref pcie_rp1 on end device ref pcie_rp2 on end device ref pcie_rp3 on end diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 0b5d0cd..5565064 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -101,10 +101,6 @@ # Send an extra VR mailbox command for the PS4 exit issue register "SendVrMbxCmd" = "2" - # Enable SATA ports 1,2 - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - # Enable Root ports. 1-6 for LAN and Root Port 9 register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" @@ -183,7 +179,12 @@ }" end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + }" + end device ref pcie_rp1 on end device ref pcie_rp2 on end device ref pcie_rp3 on end diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 5b222fc..7892c7e 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -38,8 +38,6 @@ register "dptf_enable" = "0" # FSP Configuration - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[2]" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" @@ -146,7 +144,12 @@ device ref south_xhci on end device ref south_xdci on end device ref thermal on end - device ref sata on end + device ref sata on + register "SataPortsEnable" = "{ + [0] = 1, + [2] = 1, + }" + end device ref pcie_rp5 on end device ref pcie_rp9 on end device ref lpc_espi on diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 1a8be1d..29759fd 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -3,18 +3,6 @@ # FSP Configuration register "SkipExtGfxScan" = "1" - # SATA configuration - register "SataSalpSupport" = "1" - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - [4] = 1, - [5] = 1, - [6] = 1, - [7] = 1, - }" # LPC register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -31,7 +19,19 @@ device ref south_xhci on end device ref thermal on end device ref heci1 on end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end device ref lpc_espi on chip superio/common device pnp 2e.0 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/83179?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Gerrit-Change-Number: 83179 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: acer/aspire_vn7_572g: Drop superfluous SATA AHCI mode configuration
by Felix Singer (Code Review) 22 Jun '24

22 Jun '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83178?usp=email ) Change subject: acer/aspire_vn7_572g: Drop superfluous SATA AHCI mode configuration ...................................................................... acer/aspire_vn7_572g: Drop superfluous SATA AHCI mode configuration The SATA controller is configured to AHCI mode by default. Drop the setting from the devicetree. Change-Id: I027b393300e2cbad827e176afddc197007314f10 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/acer/aspire_vn7_572g/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/83178/1 diff --git a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb index 0b590ae..8999aa3 100644 --- a/src/mainboard/acer/aspire_vn7_572g/devicetree.cb +++ b/src/mainboard/acer/aspire_vn7_572g/devicetree.cb @@ -243,7 +243,6 @@ end device ref heci1 on end device ref sata on - register "SataMode" = "SATA_AHCI" register "SataSalpSupport" = "1" register "SataPortsEnable[1]" = "1" # HDD; BIT1 in 92h-93h register "SataPortsEnable[2]" = "1" # ODD; BIT2 in 92h-93h -- To view, visit https://review.coreboot.org/c/coreboot/+/83178?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I027b393300e2cbad827e176afddc197007314f10 Gerrit-Change-Number: 83178 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: skl mainboards/dt: Drop SataPortsDevSlp[x] setting if disabled
by Felix Singer (Code Review) 22 Jun '24

22 Jun '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83177?usp=email ) Change subject: skl mainboards/dt: Drop SataPortsDevSlp[x] setting if disabled ...................................................................... skl mainboards/dt: Drop SataPortsDevSlp[x] setting if disabled The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: I572a9092633c61907794ecbbbe431066d889c5fb Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb 3 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/83177/1 diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 9a1ce33..f173e1e 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -34,11 +34,6 @@ [1] = 1, [2] = 1, }" - register "SataPortsDevSlp" = "{ - [0] = 0, - [1] = 0, - [2] = 0, - }" register "SataSpeedLimit" = "2" register "DspEnable" = "1" register "IoBufferOwnership" = "0" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 010d021..0b5d0cd 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -104,8 +104,6 @@ # Enable SATA ports 1,2 register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[1]" = "0" # Enable Root ports. 1-6 for LAN and Root Port 9 register "PcieRpEnable[0]" = "1" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 62cff2b..5b222fc 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -40,8 +40,6 @@ # FSP Configuration register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" - register "SataPortsDevSlp[0]" = "0" - register "SataPortsDevSlp[2]" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/83177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I572a9092633c61907794ecbbbe431066d889c5fb Gerrit-Change-Number: 83177 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[S] Change in coreboot[main]: skl mainboards/dt: Drop SataPortsEnable[x] setting if disabled
by Felix Singer (Code Review) 22 Jun '24

22 Jun '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83176?usp=email ) Change subject: skl mainboards/dt: Drop SataPortsEnable[x] setting if disabled ...................................................................... skl mainboards/dt: Drop SataPortsEnable[x] setting if disabled The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Icdf58a85bbde0dcb4e555df68cd20eade241dde3 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 12 files changed, 0 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/83176/1 diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index 7705340..854b887 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -35,13 +35,6 @@ register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ [0] = 1, - [1] = 0, - [2] = 0, - [3] = 0, - [4] = 0, - [5] = 0, - [6] = 0, - [7] = 0, }" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index 4137ba1..38d0742 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -30,7 +30,6 @@ register "gpe0_dw2" = "GPP_E" # FSP Configuration - register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index e820832..88b7fbc 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -31,7 +31,6 @@ register "dptf_enable" = "1" # FSP Configuration - register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 464b99c..85a1e23a 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -37,7 +37,6 @@ register "CmdTriStateDis" = "1" # FSP Configuration - register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index cb995f3..c44b380 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -25,7 +25,6 @@ register "s0ix_enable" = true # FSP Configuration - register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 9bc38d1..5d31208 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -34,7 +34,6 @@ register "s0ix_enable" = true # FSP Configuration - register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 00709b7..9853f49 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -30,7 +30,6 @@ register "CmdTriStateDis" = "1" # FSP Configuration - register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 06cf256..fa57537 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -37,7 +37,6 @@ register "CmdTriStateDis" = "1" # FSP Configuration - register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 56e84c1e..d7dea15 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -34,7 +34,6 @@ register "s0ix_enable" = true # FSP Configuration - register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index cb11b45..010d021 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -104,7 +104,6 @@ # Enable SATA ports 1,2 register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" - register "SataPortsEnable[2]" = "0" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[1]" = "0" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 35f63a0..62cff2b 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -39,7 +39,6 @@ # FSP Configuration register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "0" register "SataPortsEnable[2]" = "1" register "SataPortsDevSlp[0]" = "0" register "SataPortsDevSlp[2]" = "0" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index bb5c2ce..438d323 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -19,11 +19,6 @@ register "dptf_enable" = "0" # FSP Configuration - register "SataPortsEnable" = "{ - [0] = 0, - [1] = 0, - [2] = 0, - }" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/83176?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icdf58a85bbde0dcb4e555df68cd20eade241dde3 Gerrit-Change-Number: 83176 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

1 0

[S] Change in coreboot[main]: skl mainboards/dt: Drop SataSalpSupport setting if disabled
by Felix Singer (Code Review) 22 Jun '24

22 Jun '24

Attention is currently required from: Jeremy Soller, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Piotr Król, Tim Crawford. Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83175?usp=email ) Change subject: skl mainboards/dt: Drop SataSalpSupport setting if disabled ...................................................................... skl mainboards/dt: Drop SataSalpSupport setting if disabled The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Icb41f0a9baded01267410bd4c9458ab4bfb82b70 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb 16 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/83175/1 diff --git a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb index f0588da..bb896aa 100644 --- a/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb +++ b/src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb @@ -58,7 +58,6 @@ device ref thermal on end device ref heci1 on end device ref sata on - register "SataSalpSupport" = "0" # Ports register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb index c88d3c2..4137ba1 100644 --- a/src/mainboard/google/eve/devicetree.cb +++ b/src/mainboard/google/eve/devicetree.cb @@ -30,7 +30,6 @@ register "gpe0_dw2" = "GPP_E" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index 891de90..7d11653 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -59,7 +59,6 @@ register "s0ix_enable" = true # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 394b8f7..e820832 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -31,7 +31,6 @@ register "dptf_enable" = "1" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/atlas/devicetree.cb b/src/mainboard/google/poppy/variants/atlas/devicetree.cb index 20a9858..464b99c 100644 --- a/src/mainboard/google/poppy/variants/atlas/devicetree.cb +++ b/src/mainboard/google/poppy/variants/atlas/devicetree.cb @@ -37,7 +37,6 @@ register "CmdTriStateDis" = "1" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb index aa78587..cb995f3 100644 --- a/src/mainboard/google/poppy/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/poppy/variants/baseboard/devicetree.cb @@ -25,7 +25,6 @@ register "s0ix_enable" = true # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 09ca9d2..43c1b4b 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -34,7 +34,6 @@ register "s0ix_enable" = true # FSP Configuration - register "SataSalpSupport" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" register "ScsEmmcHs400Enabled" = "1" diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index 2981080..9bc38d1 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -34,7 +34,6 @@ register "s0ix_enable" = true # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb index 01fda4d..00709b7 100644 --- a/src/mainboard/google/poppy/variants/nocturne/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nocturne/devicetree.cb @@ -30,7 +30,6 @@ register "CmdTriStateDis" = "1" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/rammus/devicetree.cb b/src/mainboard/google/poppy/variants/rammus/devicetree.cb index 4c8804f..06cf256 100644 --- a/src/mainboard/google/poppy/variants/rammus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/rammus/devicetree.cb @@ -37,7 +37,6 @@ register "CmdTriStateDis" = "1" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/google/poppy/variants/soraka/devicetree.cb b/src/mainboard/google/poppy/variants/soraka/devicetree.cb index 7e28b82..56e84c1e 100644 --- a/src/mainboard/google/poppy/variants/soraka/devicetree.cb +++ b/src/mainboard/google/poppy/variants/soraka/devicetree.cb @@ -34,7 +34,6 @@ register "s0ix_enable" = true # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "0" register "DspEnable" = "1" register "IoBufferOwnership" = "3" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index bf974a0..9a1ce33 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -29,7 +29,6 @@ register "dptf_enable" = "0" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable" = "{ [0] = 1, [1] = 1, diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 76023593..cb11b45 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -23,7 +23,6 @@ register "tcc_offset" = "5" # TCC of 95C # FSP Configuration - register "SataSalpSupport" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" register "SkipExtGfxScan" = "1" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index fe34f65..35f63a0 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -38,7 +38,6 @@ register "dptf_enable" = "0" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "0" register "SataPortsEnable[2]" = "1" diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 37e67b8..bb5c2ce 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -19,7 +19,6 @@ register "dptf_enable" = "0" # FSP Configuration - register "SataSalpSupport" = "0" register "SataPortsEnable" = "{ [0] = 0, [1] = 0, diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index d89157c..38578e0 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -128,7 +128,6 @@ end device ref thermal on end device ref sata on - register "SataSalpSupport" = "0" register "SataSpeedLimit" = "2" register "SataPortsEnable" = "{ [0] = 1, -- To view, visit https://review.coreboot.org/c/coreboot/+/83175?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb41f0a9baded01267410bd4c9458ab4bfb82b70 Gerrit-Change-Number: 83175 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com>

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[S] Change in coreboot[main]: skl mainboards/dt: Drop SsicPortEnable setting if disabled
by Felix Singer (Code Review) 22 Jun '24

22 Jun '24

Attention is currently required from: Erik van den Bogaert, Frans Hendriks, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Piotr Król. Hello Erik van den Bogaert, Frans Hendriks, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Piotr Król, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83173?usp=email to look at the new patch set (#3). Change subject: skl mainboards/dt: Drop SsicPortEnable setting if disabled ...................................................................... skl mainboards/dt: Drop SsicPortEnable setting if disabled The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 17 files changed, 0 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/83173/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/83173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b Gerrit-Change-Number: 83173 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com>

1 0

[XS] Change in coreboot[main]: skl mainboards/dt: Drop ScsEmmcHs400Enabled setting if disabled
by Felix Singer (Code Review) 22 Jun '24

22 Jun '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83174?usp=email ) Change subject: skl mainboards/dt: Drop ScsEmmcHs400Enabled setting if disabled ...................................................................... skl mainboards/dt: Drop ScsEmmcHs400Enabled setting if disabled The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: I1239132d5f25345ebb051d216e9187f3d2250339 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 7 files changed, 0 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/83174/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 1bf8337..7a77e64 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -41,7 +41,6 @@ register "SataPortsDevSlp[2]" = "1" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb index a370ab8..891de90 100644 --- a/src/mainboard/google/fizz/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/fizz/variants/baseboard/devicetree.cb @@ -65,7 +65,6 @@ register "SataPortsDevSlp[1]" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 4a56596..067cb59 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -17,7 +17,6 @@ # FSP Configuration register "DspEnable" = "1" register "IoBufferOwnership" = "3" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" # Enabling SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index 721659a..bf974a0 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -43,7 +43,6 @@ register "SataSpeedLimit" = "2" register "DspEnable" = "1" register "IoBufferOwnership" = "0" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 88d3e0b..76023593 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -26,7 +26,6 @@ register "SataSalpSupport" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" register "IslVrCmd" = "2" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index a38a5f1..fe34f65 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -46,7 +46,6 @@ register "SataPortsDevSlp[2]" = "0" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index ad1a9c8..37e67b8 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -27,7 +27,6 @@ }" register "DspEnable" = "0" register "IoBufferOwnership" = "0" - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Enabled" register "PmConfigSlpS3MinAssert" = "2" # 50ms -- To view, visit https://review.coreboot.org/c/coreboot/+/83174?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1239132d5f25345ebb051d216e9187f3d2250339 Gerrit-Change-Number: 83174 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[S] Change in coreboot[main]: skl mainboards/dt: Drop SsicPortEnable if disabled
by Felix Singer (Code Review) 22 Jun '24

22 Jun '24

Attention is currently required from: Erik van den Bogaert, Frans Hendriks, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Piotr Król. Hello Erik van den Bogaert, Frans Hendriks, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Piotr Król, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83173?usp=email to look at the new patch set (#2). Change subject: skl mainboards/dt: Drop SsicPortEnable if disabled ...................................................................... skl mainboards/dt: Drop SsicPortEnable if disabled The attributes are initialized with 0 and thus setting them to 0 makes them superfluous. Remove them. Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/clevo/kbl-u/variants/n13xwu/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/eve/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/google/glados/devicetree.cb M src/mainboard/google/poppy/variants/atlas/devicetree.cb M src/mainboard/google/poppy/variants/baseboard/devicetree.cb M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nocturne/devicetree.cb M src/mainboard/google/poppy/variants/rammus/devicetree.cb M src/mainboard/google/poppy/variants/soraka/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb 17 files changed, 0 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/83173/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83173?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic16d568c38d708da27efa7229e23019e71c0019b Gerrit-Change-Number: 83173 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com>

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