coreboot-gerrit June 2024

coreboot-gerrit@coreboot.org

1 participants
3527 discussions

[M] Change in coreboot[main]: skl mainboards/dt: Move genx_dec settings into LPC device scope
by Marvin Evers (Code Review) 23 Jun '24

23 Jun '24

Attention is currently required from: Erik van den Bogaert, Felix Singer, Frans Hendriks, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Piotr Król. Marvin Evers has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83172?usp=email ) Change subject: skl mainboards/dt: Move genx_dec settings into LPC device scope ...................................................................... Patch Set 1: Code-Review+1 (1 comment) Patchset: PS1: checked whether: - options have been moved to dt - hex values are consistent - all skl/kbl boards are covered -- To view, visit https://review.coreboot.org/c/coreboot/+/83172?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iecb4851bedb7c9ed7793763d80acbcbb068e8832 Gerrit-Change-Number: 83172 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Sun, 23 Jun 2024 22:07:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[XL] Change in coreboot[main]: skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope
by Marvin Evers (Code Review) 23 Jun '24

23 Jun '24

Attention is currently required from: Erik van den Bogaert, Felix Singer, Frans Hendriks, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król. Marvin Evers has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/83171?usp=email ) Change subject: skl mainboards/dt: Move usb{2,3}_ports settings into XHCI device scope ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Patchset: PS2: checked whether: - options have been moved into dt - indices remain consistent - dt comments have been converted to C comments when format changed - all skl/kbl boards are covered -- To view, visit https://review.coreboot.org/c/coreboot/+/83171?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22ba991a9d559b0ecc7b3ceddcfd099890dd6c3a Gerrit-Change-Number: 83171 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Marvin Evers <marvin.n.evers(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Sun, 23 Jun 2024 20:37:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: skl mainboards/dt: Move SsicPortEnable setting into XHCI device scope
by Felix Singer (Code Review) 23 Jun '24

23 Jun '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83189?usp=email ) Change subject: skl mainboards/dt: Move SsicPortEnable setting into XHCI device scope ...................................................................... skl mainboards/dt: Move SsicPortEnable setting into XHCI device scope Change-Id: I64ffba35303c1291f56ae6a038325a7482158ad3 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb 4 files changed, 8 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/83189/1 diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 8a3161a..9d4c0d9 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -41,10 +41,6 @@ # RP17, uses CLK SRC 7 register "PcieRpClkSrcNumber[16]" = "7" - # USB related - register "SsicPortEnable" = "1" - - register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, @@ -66,6 +62,8 @@ device domain 0 on device ref south_xhci on + register "SsicPortEnable" = "1" + register "usb2_ports" = "{ [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ [1] = USB2_PORT_MID(OC3), /* Touch Pad */ diff --git a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb index 0af8282..7de1454 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp3/overridetree.cb @@ -71,9 +71,6 @@ # RP10, uses CLK SRC 4 register "PcieRpClkSrcNumber[9]" = "4" - - register "SsicPortEnable" = "1" # Enable SSIC for WWAN - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -91,6 +88,8 @@ device domain 0 on device ref south_xhci on + register "SsicPortEnable" = "1" # Enable SSIC for WWAN + register "usb2_ports" = "{ [0] = USB2_PORT_MAX(OC0), /* TYPE-A Port */ [1] = USB2_PORT_MAX(OC2), /* TYPE-A Port */ diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 010312c..eb13212 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -93,9 +93,6 @@ register "PcieRpClkReqNumber[8]" = "6" register "PcieRpClkReqNumber[16]" = "7" - - register "SsicPortEnable" = "1" # Enable SSIC for WWAN - # Must leave UART0 enabled or SD/eMMC will not work as PCI register "SerialIoDevMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, @@ -118,6 +115,8 @@ device domain 0 on device ref south_xhci on + register "SsicPortEnable" = "1" # Enable SSIC for WWAN + register "usb2_ports" = "{ [0] = USB2_PORT_MAX(OC2), /* Type-C Port */ [1] = USB2_PORT_MAX(OC5), /* Front panel */ diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 2f5058d..c92377a 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -120,10 +120,6 @@ register "PcieRpClkReqNumber[5]" = "0" register "PcieRpClkReqNumber[12]" = "1" - # USB related - register "SsicPortEnable" = "1" - - register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V # Must leave UART0 enabled or SD/eMMC will not work as PCI @@ -156,6 +152,8 @@ device domain 0 on device ref igpu on end device ref south_xhci on + register "SsicPortEnable" = "1" + register "usb2_ports" = "{ [0] = USB2_PORT_MID(OC_SKIP), /* OTG */ [1] = USB2_PORT_MID(OC3), /* Touch Pad */ -- To view, visit https://review.coreboot.org/c/coreboot/+/83189?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64ffba35303c1291f56ae6a038325a7482158ad3 Gerrit-Change-Number: 83189 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

1 0

[M] Change in coreboot[main]: skl mainboards/dt: Move SATA related settings into SATA device scope
by Felix Singer (Code Review) 23 Jun '24

23 Jun '24

Attention is currently required from: Erik van den Bogaert, Frans Hendriks, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król. Hello Erik van den Bogaert, Frans Hendriks, Jonathon Hall, Michael Niewöhner, Michał Żygowski, Nico Huber, Piotr Król, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83179?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: skl mainboards/dt: Move SATA related settings into SATA device scope ...................................................................... skl mainboards/dt: Move SATA related settings into SATA device scope Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/google/fizz/variants/baseboard/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp7/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/kontron/bsl6/variants/bsl6/overridetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb 12 files changed, 108 insertions(+), 94 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/83179/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83179?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I50706d7a077767d2295d6d5f209c30109d607277 Gerrit-Change-Number: 83179 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com>

1 0

[L] Change in coreboot[main]: [test] Add DH67BL mainboard
by Elyes Haouas (Code Review) 23 Jun '24

23 Jun '24

Attention is currently required from: Pratikkumar V Prajapati. Elyes Haouas has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/83027?usp=email ) Change subject: [test] Add DH67BL mainboard ...................................................................... Patch Set 8: (1 comment) File src/mainboard/intel/dh67bl/Kconfig: https://review.coreboot.org/c/coreboot/+/83027/comment/2f610482_5bd35cc6?us… : PS8, Line 16: superio Winbond W83677HG-i datasheet is missing :( -- To view, visit https://review.coreboot.org/c/coreboot/+/83027?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If466e834aae0a980941fadb18635e90280119088 Gerrit-Change-Number: 83027 Gerrit-PatchSet: 8 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Sun, 23 Jun 2024 18:53:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[M] Change in coreboot[main]: skl mainboards/dt: Move serirq setting into LPC device scope
by Felix Singer (Code Review) 23 Jun '24

23 Jun '24

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83188?usp=email ) Change subject: skl mainboards/dt: Move serirq setting into LPC device scope ...................................................................... skl mainboards/dt: Move serirq setting into LPC device scope Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/mainboard/51nb/x210/devicetree.cb M src/mainboard/facebook/monolith/devicetree.cb M src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb M src/mainboard/intel/saddlebrook/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/protectli/vault_kbl/devicetree.cb M src/mainboard/purism/librem_skl/devicetree.cb M src/mainboard/razer/blade_stealth_kbl/devicetree.cb M src/mainboard/supermicro/x11-lga1151-series/devicetree.cb M src/mainboard/system76/kbl-u/devicetree.cb 11 files changed, 25 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/83188/1 diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index 1f2fa40..3ffc00f 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -39,8 +39,6 @@ register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Enable Root Ports 3, 4 and 9 register "PcieRpEnable[2]" = "1" # Ethernet controller register "PcieRpClkReqSupport[2]" = "1" @@ -116,6 +114,8 @@ device ref pcie_rp4 on end device ref pcie_rp9 on end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" diff --git a/src/mainboard/facebook/monolith/devicetree.cb b/src/mainboard/facebook/monolith/devicetree.cb index c41a26f..763a380 100644 --- a/src/mainboard/facebook/monolith/devicetree.cb +++ b/src/mainboard/facebook/monolith/devicetree.cb @@ -18,9 +18,6 @@ register "lpc_iod" = "0x0070" register "lpc_ioe" = "LPC_IOE_COMA_EN | LPC_IOE_COMB_EN | LPC_IOE_EC_62_66" - # LPC serial IRQ - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # "Intel SpeedStep Technology" register "eist_enable" = "1" @@ -214,6 +211,8 @@ device ref uart0 on end device ref emmc on end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + # CPLD host command ranges are in 0x280-0x2BF # EC PNP registers are at 0x6e and 0x6f register "gen1_dec" = "0x003c0281" diff --git a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb index 49edccb..8a3161a 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp11/overridetree.cb @@ -4,8 +4,6 @@ register "DspEnable" = "0" register "ScsEmmcHs400Enabled" = "0" - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Enable PCIE slot register "PcieRpEnable[5]" = "1" register "PcieRpClkReqSupport[5]" = "1" @@ -119,5 +117,8 @@ device ref sdxc off end device ref hda on end device ref gbe on end + device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + end end end diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 5516fee..010312c 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -7,8 +7,6 @@ # FSP Configuration register "ScsEmmcHs400Enabled" = "0" - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # VR Settings Configuration for 5 Domains #+----------------+-------+-------+-------------+-------------+-------+ #| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT | @@ -173,6 +171,8 @@ device ref emmc off end device ref sdxc off end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + #chip drivers/pc80/tpm # device pnp 0c31.0 on end #end diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 73df651..2f5058d 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -32,8 +32,6 @@ # SLP_A Minimum Assertion Width. Values 0: 0ms, 1: 4s, 2: 98ms, 3: 2s register "PmConfigSlpAMinAssert" = "0x03" - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | @@ -217,6 +215,9 @@ device ref gspi1 on end device ref hda on end device ref smbus on end + device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + end device ref fast_spi on end device ref gbe on end end diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index f173e1e..a171517 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -9,8 +9,6 @@ register "eist_enable" = "1" - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Set the Thermal Control Circuit (TCC) activation value to 95C # even though FSP integration guide says to set it to 100C for SKL-U # (offset at 0), because when the TCC activates at 100C, the CPU @@ -169,6 +167,8 @@ device ref pcie_rp11 on end device ref pcie_rp12 on end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x007c0a01" # EC 0xa00-0xa7f register "gen2_dec" = "0x000c03e1" # COM3 port 0x3e0 - 0x3ef register "gen3_dec" = "0x00fc02e1" # COM2/4/5/6 ports 0x2e0 - 0x2ff diff --git a/src/mainboard/protectli/vault_kbl/devicetree.cb b/src/mainboard/protectli/vault_kbl/devicetree.cb index 5565064..228676b 100644 --- a/src/mainboard/protectli/vault_kbl/devicetree.cb +++ b/src/mainboard/protectli/vault_kbl/devicetree.cb @@ -17,9 +17,6 @@ # Disable DPTF register "dptf_enable" = "0" - # Enable SERIRQ continuous - register "serirq_mode" = "SERIRQ_CONTINUOUS" - register "tcc_offset" = "5" # TCC of 95C # FSP Configuration @@ -198,6 +195,8 @@ "SlotLengthShort" "WIFI1" "SlotDataBusWidth1X" end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x00fc0201" register "gen2_dec" = "0x007c0a01" register "gen3_dec" = "0x000c03e1" diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index 7892c7e..ca18f7a 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -47,9 +47,6 @@ register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - # EC/KBC requires continuous mode - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | @@ -153,6 +150,9 @@ device ref pcie_rp5 on end device ref pcie_rp9 on end device ref lpc_espi on + # EC/KBC requires continuous mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + # EC host command ranges are in 0x380-0x383 & 0x80-0x8f register "gen1_dec" = "0x00000381" chip drivers/pc80/tpm diff --git a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb index 438d323..b8ebb1b 100644 --- a/src/mainboard/razer/blade_stealth_kbl/devicetree.cb +++ b/src/mainboard/razer/blade_stealth_kbl/devicetree.cb @@ -28,8 +28,6 @@ register "PmConfigSlpSusMinAssert" = "3" # 500ms register "PmConfigSlpAMinAssert" = "3" # 2s - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # VR Settings Configuration for 4 Domains #+----------------+-----------+-----------+-------------+----------+ #| Domain/Setting | SA | IA | GT Unsliced | GT | @@ -172,6 +170,8 @@ device ref pcie_rp5 on end device ref pcie_rp9 on end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index 29759fd..fbf896c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -4,9 +4,6 @@ register "SkipExtGfxScan" = "1" - # LPC - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Enabling SLP_S0, SLP_S3#, SLP_S4#, SLP_SUS and SLP_A Stretch register "s0ix_enable" = true register "PmConfigSlpS3MinAssert" = "SLP_S3_MIN_ASSERT_50MS" @@ -33,6 +30,8 @@ }" end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + chip superio/common device pnp 2e.0 on end end diff --git a/src/mainboard/system76/kbl-u/devicetree.cb b/src/mainboard/system76/kbl-u/devicetree.cb index 38578e0..e4658a7 100644 --- a/src/mainboard/system76/kbl-u/devicetree.cb +++ b/src/mainboard/system76/kbl-u/devicetree.cb @@ -18,9 +18,6 @@ [PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART }" - # Serial IRQ - register "serirq_mode" = "SERIRQ_CONTINUOUS" - # Power register "PmConfigSlpS3MinAssert" = "2" # 50ms register "PmConfigSlpS4MinAssert" = "1" # 1s @@ -172,6 +169,8 @@ register "PcieRpLtrEnable[8]" = "1" end device ref lpc_espi on + register "serirq_mode" = "SERIRQ_CONTINUOUS" + register "gen1_dec" = "0x000c0681" register "gen2_dec" = "0x000c1641" register "gen3_dec" = "0x00040069" -- To view, visit https://review.coreboot.org/c/coreboot/+/83188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84da5365907664ce223dec4adb22a8f1a6e2a144 Gerrit-Change-Number: 83188 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

1 0

[XS] Change in coreboot[main]: util/autoport: Move SPDX header before defines in dsdt.asl
by Nicholas Chin (Code Review) 23 Jun '24

23 Jun '24

Nicholas Chin has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/83187?usp=email ) Change subject: util/autoport: Move SPDX header before defines in dsdt.asl ...................................................................... util/autoport: Move SPDX header before defines in dsdt.asl Macros were being printed before the SPDX header in dsdt.asl, so fix this. Previous output: #define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB /* SPDX-License-Identifier: GPL-2.0-only */ Change-Id: Idebdcf816911af9d262a114c86461e6fa5bfd1f8 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/autoport/main.go 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/83187/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idebdcf816911af9d262a114c86461e6fa5bfd1f8 Gerrit-Change-Number: 83187 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[XS] Change in coreboot[main]: util/autoport: Move SPDX header before defines in dsdt.asl
by Nicholas Chin (Code Review) 23 Jun '24

23 Jun '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83187?usp=email ) Change subject: util/autoport: Move SPDX header before defines in dsdt.asl ...................................................................... util/autoport: Move SPDX header before defines in dsdt.asl Macros were being printed before the SPDX header in dsdt.asl, so fix this. Previous output: /* SPDX-License-Identifier: GPL-2.0-only */ Change-Id: Idebdcf816911af9d262a114c86461e6fa5bfd1f8 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/autoport/main.go 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/83187/1 diff --git a/util/autoport/main.go b/util/autoport/main.go index 6426dd3..a4982b4 100644 --- a/util/autoport/main.go +++ b/util/autoport/main.go @@ -827,6 +827,7 @@ dsdt := Create(ctx, "dsdt.asl") defer dsdt.Close() + Add_gpl(dsdt) for _, define := range DSDTDefines { if define.Comment != "" { @@ -835,7 +836,6 @@ dsdt.WriteString("#define " + define.Key + " " + define.Value + "\n") } - Add_gpl(dsdt) dsdt.WriteString( ` #include <acpi/acpi.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/83187?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idebdcf816911af9d262a114c86461e6fa5bfd1f8 Gerrit-Change-Number: 83187 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[XS] Change in coreboot[main]: util/autoport: Remove extra blank lines from generated files
by Nicholas Chin (Code Review) 23 Jun '24

23 Jun '24

Nicholas Chin has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/83186?usp=email ) Change subject: util/autoport: Remove extra blank lines from generated files ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/83186/comment/98dc0b3a_45542c48?us… : PS1, Line 7: til/autoport: Remove extra blank lines > ... […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/83186?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad74098518320c5389cb86badb8737e81dd656ae Gerrit-Change-Number: 83186 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Sun, 23 Jun 2024 17:44:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

1 0

[XS] Change in coreboot[main]: util/autoport: Remove extra blank lines from generated files
by Nicholas Chin (Code Review) 23 Jun '24

23 Jun '24

Hello Felix Singer, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/83186?usp=email to look at the new patch set (#2). Change subject: util/autoport: Remove extra blank lines from generated files ...................................................................... util/autoport: Remove extra blank lines from generated files The generated dsdt.asl and early_init.c files contained 2 consecutive blank lines, so remove one of them. Change-Id: Iad74098518320c5389cb86badb8737e81dd656ae Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- M util/autoport/bd82x6x.go M util/autoport/main.go 2 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/83186/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83186?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad74098518320c5389cb86badb8737e81dd656ae Gerrit-Change-Number: 83186 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2024