coreboot-gerrit May 2024

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[M] Change in coreboot[main]: drivers/intel/dtbt: Add discrete Thunderbolt driver
by Tim Crawford (Code Review) 22 May '24

22 May '24

Attention is currently required from: Jeremy Soller, Kyösti Mälkki, Martin L Roth, Michał Żygowski, Paul Menzel, Tim Wawrzynczak, Utkarsh H Patel. Tim Crawford has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/75286?usp=email ) Change subject: drivers/intel/dtbt: Add discrete Thunderbolt driver ...................................................................... Patch Set 9: (3 comments) File src/drivers/intel/dtbt/dtbt.c: https://review.coreboot.org/c/coreboot/+/75286/comment/3476c984_0ed3e940?us… : PS6, Line 13: #define PCIE2TBT 0x54C > Referring to older datasheet: Alpine-Ridge DP, Thunderbolt Interface Controller, Revision 1. […] Titan Ridge and Maple Ridge BIOS implementation guides document only these 2 specific offsets. DP Thunderbolt Interface Controller is mentioned only as a reference document in the Titan Ridge guide. https://review.coreboot.org/c/coreboot/+/75286/comment/8fc10b00_2cc947d7?us… : PS6, Line 24: #define TIMEOUT_MS 1000 > Is there a reason why you don't use this timeout with acpigen_write_delay_until_namestr_int() calls? […] The BIOS implementation guides specify a default timeout of 600ms for `GO2SX`/`GO2SX_NO_WAKE` acknowledgement. https://review.coreboot.org/c/coreboot/+/75286/comment/885e2f62_e3de1345?us… : PS6, Line 37: if (!wait_ms(TIMEOUT_MS, !(pci_read_config32(dev, TBT2PCIE) & TBT2PCIE_DONE))) { > My old reference for PCIE2TBT_GO2SX command says clearing VALID would not clear DONE. […] Maple Ridge BIOS implementation guide does not specify the timeout after clearing `PCIE2TBT`. Titan Ridge BIOS implementation guide does show it in the flowchart "Figure 2.3: Mailbox Command Handshake Procedure". The only thing that then references this handshake is `OS_UP` though. -- To view, visit https://review.coreboot.org/c/coreboot/+/75286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364 Gerrit-Change-Number: 75286 Gerrit-PatchSet: 9 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Wed, 22 May 2024 23:06:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kyösti Mälkki <kyosti.malkki(a)gmail.com>

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[XS] Change in coreboot[main]: mb/intel/mtlrvp: Enable EC MKBP device
by Vijay P Hiremath (Code Review) 22 May '24

22 May '24

Attention is currently required from: Jay Patel, Pratikkumar V Prajapati, Subrata Banik, Tanu Malhotra. Vijay P Hiremath has posted comments on this change by Jay Patel. ( https://review.coreboot.org/c/coreboot/+/82612?usp=email ) Change subject: mb/intel/mtlrvp: Enable EC MKBP device ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I630421c83784bb4492486d72290b9e8cdada1d47 Gerrit-Change-Number: 82612 Gerrit-PatchSet: 1 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tanu Malhotra <tanu.malhotra(a)intel.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Tanu Malhotra <tanu.malhotra(a)intel.com> Gerrit-Attention: Jay Patel <jay2.patel(a)intel.com> Gerrit-Attention: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Comment-Date: Wed, 22 May 2024 22:59:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/intel/mtlrvp: Enable EC MKBP device
by Jay Patel (Code Review) 22 May '24

22 May '24

Jay Patel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82612?usp=email ) Change subject: mb/intel/mtlrvp: Enable EC MKBP device ...................................................................... mb/intel/mtlrvp: Enable EC MKBP device MKBP device is required for passing events from input sources to AP. Input sources include buttons (power, volume); switches (lid, tablet mode) and sysrq. BUG=b:342227155 TEST=Able to build coreboot for mtlrvp platform and switch tablet mode. Change-Id: I630421c83784bb4492486d72290b9e8cdada1d47 Signed-off-by: Jay Patel <jay2.patel(a)intel.com> --- M src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/include/baseboard/ec.h 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/82612/1 diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/include/baseboard/ec.h b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/include/baseboard/ec.h index 402c9c1..44f9b43 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/include/baseboard/ec.h +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/include/baseboard/ec.h @@ -59,6 +59,9 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE +/* Enable MKBP for buttons and switches */ +#define EC_ENABLE_MKBP_DEVICE + /* Enable LID switch and provide wake pin for EC */ #define EC_ENABLE_LID_SWITCH #define EC_ENABLE_WAKE_PIN GPE_EC_WAKE -- To view, visit https://review.coreboot.org/c/coreboot/+/82612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I630421c83784bb4492486d72290b9e8cdada1d47 Gerrit-Change-Number: 82612 Gerrit-PatchSet: 1 Gerrit-Owner: Jay Patel <jay2.patel(a)intel.com>

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[M] Change in coreboot[main]: drivers/intel/dtbt: Add discrete Thunderbolt driver
by Tim Crawford (Code Review) 22 May '24

22 May '24

Attention is currently required from: Jeremy Soller, Kyösti Mälkki, Martin L Roth, Michał Żygowski, Paul Menzel, Tim Crawford, Tim Wawrzynczak, Utkarsh H Patel. Hello Jeremy Soller, Tim Wawrzynczak, Utkarsh H Patel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/75286?usp=email to look at the new patch set (#9). Change subject: drivers/intel/dtbt: Add discrete Thunderbolt driver ...................................................................... drivers/intel/dtbt: Add discrete Thunderbolt driver Add a new driver for discrete Thunderbolt controllers. This allows using e.g. Maple Ridge devices on Raptor Point PCH. Ref: Titan Ridge BIOS Implementation Guide v1.4 Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472) Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364 Signed-off-by: Jeremy Soller <jeremy(a)system76.com> Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- A src/drivers/intel/dtbt/Kconfig A src/drivers/intel/dtbt/Makefile.mk A src/drivers/intel/dtbt/chip.h A src/drivers/intel/dtbt/dtbt.c 4 files changed, 209 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/75286/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/75286?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364 Gerrit-Change-Number: 75286 Gerrit-PatchSet: 9 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-CC: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-CC: Jeremy Compostella <jeremy.compostella(a)intel.corp-partner.google.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Utkarsh H Patel <utkarsh.h.patel(a)intel.com> Gerrit-Attention: Kyösti Mälkki <kyosti.malkki(a)gmail.com>

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[M] Change in coreboot[main]: Revert "mb/google/rex/var/deku: Configure GPIO"
by Felix Held (Code Review) 22 May '24

22 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82572?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: Revert "mb/google/rex/var/deku: Configure GPIO" ...................................................................... Revert "mb/google/rex/var/deku: Configure GPIO" This reverts commit 7088257b1ab715e93506619727e3bf589ea688fb. Reason for revert: Intel suggest is NC only. No need to change anything that isn't broken. Change-Id: I976a85b35c69b03f1bc0ccd2bc7df923e47be815 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82572 Reviewed-by: Derek Huang <derekhuang(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/deku/gpio.c 1 file changed, 89 insertions(+), 89 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Derek Huang: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/deku/gpio.c b/src/mainboard/google/rex/variants/deku/gpio.c index 52cb2e0..55464dd 100644 --- a/src/mainboard/google/rex/variants/deku/gpio.c +++ b/src/mainboard/google/rex/variants/deku/gpio.c @@ -27,99 +27,99 @@ /* GPP_A12 : [] ==> LAN1_ISOLATE_R_ODL */ PAD_CFG_GPO(GPP_A12, 1, DEEP), /* GPP_A13 : net NC is not present in the given design */ - PAD_NC(GPP_A13, UP_20K), + PAD_NC(GPP_A13, NONE), /* GPP_A14 : net NC is not present in the given design */ - PAD_NC(GPP_A14, UP_20K), + PAD_NC(GPP_A14, NONE), /* GPP_A15 : net NC is not present in the given design */ - PAD_NC(GPP_A15, UP_20K), + PAD_NC(GPP_A15, NONE), /* GPP_A16 : [] ==> ESPI_SOC_ALERT_L */ PAD_CFG_NF_IOSSTATE(GPP_A16, UP_20K, DEEP, NF1, IGNORE), /* GPP_A17 : [] ==> EC_SOC_INT_ODL */ PAD_CFG_GPI_APIC_LOCK(GPP_A17, NONE, LEVEL, INVERT, LOCK_CONFIG), /* GPP_A18 : net NC is not present in the given design */ - PAD_NC(GPP_A18, UP_20K), + PAD_NC(GPP_A18, NONE), /* GPP_A21 : [] ==> SOC_GPP_A21 */ - PAD_NC(GPP_A21, UP_20K), + PAD_NC(GPP_A21, NONE), /* GPP_B00 : net NC is not present in the given design */ - PAD_NC(GPP_B00, UP_20K), + PAD_NC(GPP_B00, NONE), /* GPP_B01 : [] ==> BT_DISABLE_L */ PAD_CFG_GPO(GPP_B01, 1, DEEP), /* GPP_B02 : net NC is not present in the given design */ - PAD_NC(GPP_B02, UP_20K), + PAD_NC(GPP_B02, NONE), /* GPP_B03 : net NC is not present in the given design */ - PAD_NC(GPP_B03, UP_20K), + PAD_NC(GPP_B03, NONE), /* GPP_B04 : [GPP_B04_STRAP] ==> Component NC */ - PAD_NC(GPP_B04, UP_20K), + PAD_NC(GPP_B04, NONE), /* GPP_B05 : net NC is not present in the given design */ - PAD_NC(GPP_B05, UP_20K), + PAD_NC(GPP_B05, NONE), /* GPP_B06 : net NC is not present in the given design */ - PAD_NC(GPP_B06, UP_20K), + PAD_NC(GPP_B06, NONE), /* GPP_B07 : net NC is not present in the given design */ - PAD_NC(GPP_B07, UP_20K), + PAD_NC(GPP_B07, NONE), /* GPP_B08 : [] ==> PWM_BUZZER */ PAD_CFG_GPO(GPP_B08, 0, DEEP), /* GPP_B09 : net NC is not present in the given design */ - PAD_NC(GPP_B09, UP_20K), + PAD_NC(GPP_B09, NONE), /* GPP_B10 : [] ==> WIFI_DISABLE_L */ PAD_CFG_GPO(GPP_B10, 1, DEEP), /* GPP_B11 : net NC is not present in the given design */ - PAD_NC(GPP_B11, UP_20K), + PAD_NC(GPP_B11, NONE), /* GPP_B12 : [] ==> SLP_S0_R_L */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13 : [] ==> PLT_PCIE_RST_L */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* GPP_B14 : [GPP_B14_STRAP] ==> Component NC */ - PAD_NC(GPP_B14, UP_20K), + PAD_NC(GPP_B14, NONE), /* GPP_B15 : [] ==> USB_A_OC_ODL */ PAD_CFG_NF_LOCK(GPP_B15, NONE, NF1, LOCK_CONFIG), /* GPP_B16 : net NC is not present in the given design */ - PAD_NC(GPP_B16, UP_20K), + PAD_NC(GPP_B16, NONE), /* GPP_B17 : net NC is not present in the given design */ - PAD_NC(GPP_B17, UP_20K), + PAD_NC(GPP_B17, NONE), /* GPP_B18 : [] ==> SOC_I2C_TPM_SDA */ PAD_CFG_NF_LOCK(GPP_B18, NONE, NF2, LOCK_CONFIG), /* GPP_B19 : [] ==> SOC_I2C_TPM_SCL */ PAD_CFG_NF_LOCK(GPP_B19, NONE, NF2, LOCK_CONFIG), /* GPP_B20 : net NC is not present in the given design */ - PAD_NC(GPP_B20, UP_20K), + PAD_NC(GPP_B20, NONE), /* GPP_B21 : net NC is not present in the given design */ - PAD_NC(GPP_B21, UP_20K), + PAD_NC(GPP_B21, NONE), /* GPP_B22 : [] ==> USB_C_FORCE_PWR */ PAD_CFG_GPO(GPP_B22, 0, DEEP), /* GPP_B23 : net NC is not present in the given design */ - PAD_NC(GPP_B23, UP_20K), + PAD_NC(GPP_B23, NONE), /* GPP_C00 : net NC is not present in the given design */ - PAD_NC(GPP_C00, UP_20K), + PAD_NC(GPP_C00, NONE), /* GPP_C01 : net NC is not present in the given design */ - PAD_NC(GPP_C01, UP_20K), + PAD_NC(GPP_C01, NONE), /* GPP_C02 : [GPP_C02_STRAP] ==> Component NC */ - PAD_NC(GPP_C02, UP_20K), + PAD_NC(GPP_C02, NONE), /* GPP_C03 : net NC is not present in the given design */ - PAD_NC(GPP_C03, UP_20K), + PAD_NC(GPP_C03, NONE), /* GPP_C04 : net NC is not present in the given design */ - PAD_NC(GPP_C04, UP_20K), + PAD_NC(GPP_C04, NONE), /* GPP_C05 : [GPP_C05_STRAP] ==> Component NC */ - PAD_NC(GPP_C05, UP_20K), + PAD_NC(GPP_C05, NONE), /* GPP_C06 : net NC is not present in the given design */ - PAD_NC(GPP_C06, UP_20K), + PAD_NC(GPP_C06, NONE), /* GPP_C07 : net NC is not present in the given design */ - PAD_NC(GPP_C07, UP_20K), + PAD_NC(GPP_C07, NONE), /* GPP_C08 : [] ==> SOCHOT_ODL */ PAD_CFG_NF(GPP_C08, NONE, DEEP, NF2), /* GPP_C09 : [] ==> MISC_SYNC_OD */ PAD_CFG_GPI(GPP_C09, NONE, DEEP), /* GPP_C10 : net NC is not present in the given design*/ - PAD_NC(GPP_C10, UP_20K), + PAD_NC(GPP_C10, NONE), /* GPP_C11 : [] ==> LAN1_PCIE_CLKREQ_ODL */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* GPP_C12 : net NC is not present in the given design */ - PAD_NC(GPP_C12, UP_20K), + PAD_NC(GPP_C12, NONE), /* GPP_C13 : [] ==> LAN0_PERST_L */ PAD_CFG_GPO_LOCK(GPP_C13, 1, LOCK_CONFIG), /* GPP_C15 : [GPP_C15_STRAP] ==> Component NC */ - PAD_NC(GPP_C15, UP_20K), + PAD_NC(GPP_C15, NONE), /* GPP_C16 : [] ==> USB_C0_LSX_TX */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* GPP_C17 : [] ==> USB_C0_LSX_RX */ @@ -138,43 +138,43 @@ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), /* GPP_D00 : net NC is not present in the given design */ - PAD_NC(GPP_D00, UP_20K), + PAD_NC(GPP_D00, NONE), /* GPP_D01 : [] ==> LAN1_PCIE_WAKE_ODL */ PAD_CFG_GPI_SCI_LOW(GPP_D01, NONE, DEEP, EDGE_SINGLE), /* GPP_D02 : [] ==> LAN1_PERST_L */ PAD_CFG_GPO_LOCK(GPP_D02, 1, LOCK_CONFIG), /* GPP_D03 : net NC is not present in the given design */ - PAD_NC(GPP_D03, UP_20K), + PAD_NC(GPP_D03, NONE), /* GPP_D04 : net NC is not present in the given design */ - PAD_NC(GPP_D04, UP_20K), + PAD_NC(GPP_D04, NONE), /* GPP_D05 : [] ==> UART_DBG_TX_ISH_RX */ - PAD_NC(GPP_D05, UP_20K), + PAD_NC(GPP_D05, NONE), /* GPP_D06 : [] ==> UART_ISH_TX_DBG_RX */ - PAD_NC(GPP_D06, UP_20K), + PAD_NC(GPP_D06, NONE), /* GPP_D07 : [] ==> SOC_GPP_D07 */ - PAD_NC(GPP_D07, UP_20K), + PAD_NC(GPP_D07, NONE), /* GPP_D08 : net NC is not present in the given design */ - PAD_NC(GPP_D08, UP_20K), + PAD_NC(GPP_D08, NONE), /* GPP_D09 : net NC is not present in the given design */ - PAD_NC(GPP_D09, UP_20K), + PAD_NC(GPP_D09, NONE), /* GPP_D10 : net NC is not present in the given design */ - PAD_NC(GPP_D10, UP_20K), + PAD_NC(GPP_D10, NONE), /* GPP_D11 : net NC is not present in the given design */ - PAD_NC(GPP_D11, UP_20K), + PAD_NC(GPP_D11, NONE), /* GPP_D12 : [GPP_D12_STRAP] ==> Component NC */ - PAD_NC(GPP_D12, UP_20K), + PAD_NC(GPP_D12, NONE), /* GPP_D13 : net NC is not present in the given design */ - PAD_NC(GPP_D13, UP_20K), + PAD_NC(GPP_D13, NONE), /* GPP_D14 : net NC is not present in the given design */ - PAD_NC(GPP_D14, UP_20K), + PAD_NC(GPP_D14, NONE), /* GPP_D15 : net NC is not present in the given design */ - PAD_NC(GPP_D15, UP_20K), + PAD_NC(GPP_D15, NONE), /* GPP_D16 : net NC is not present in the given design */ - PAD_NC(GPP_D16, UP_20K), + PAD_NC(GPP_D16, NONE), /* GPP_D17 : net NC is not present in the given design */ - PAD_NC(GPP_D17, UP_20K), + PAD_NC(GPP_D17, NONE), /* GPP_D18 : net NC is not present in the given design */ - PAD_NC(GPP_D18, UP_20K), + PAD_NC(GPP_D18, NONE), /* GPP_D19 : [] ==> SSD_PCIE_CLKREQ_ODL */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* GPP_D20 : [] ==> LAN0_PCIE_CLKREQ_ODL */ @@ -182,12 +182,12 @@ /* GPP_D21 : [] ==> WLAN_PCIE_CLKREQ_ODL */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), /* GPP_D22 : [] ==> SOC_DBG_BPKI3C_SDA */ - PAD_NC(GPP_D22, UP_20K), + PAD_NC(GPP_D22, NONE), /* GPP_D23 : [] ==> SOC_DBG_BPKI3C_SCL */ - PAD_NC(GPP_D23, UP_20K), + PAD_NC(GPP_D23, NONE), /* GPP_E00 : net NC is not present in the given design */ - PAD_NC(GPP_E00, UP_20K), + PAD_NC(GPP_E00, NONE), /* GPP_E01 : [] ==> MEM_STRAP_2 */ PAD_CFG_GPI_LOCK(GPP_E01, NONE, LOCK_CONFIG), /* GPP_E02 : [] ==> MEM_STRAP_1 */ @@ -199,15 +199,15 @@ /* GPP_E05 : [] ==> WLAN_PCIE_WAKE_ODL */ PAD_CFG_GPI_IRQ_WAKE(GPP_E05, NONE, PLTRST, LEVEL, INVERT), /* GPP_E06 : GPP_E06_STRAP ==> Component NC */ - PAD_NC(GPP_E06, UP_20K), + PAD_NC(GPP_E06, NONE), /* GPP_E07 : net NC is not present in the given design */ - PAD_NC(GPP_E07, UP_20K), + PAD_NC(GPP_E07, NONE), /* GPP_E08 : [] ==> USB_C0_AUX_DC_N */ PAD_CFG_NF(GPP_E08, NONE, DEEP, NF6), /* GPP_E09 : [] ==> USB_C_OC_ODL */ PAD_CFG_NF_LOCK(GPP_E09, NONE, NF1, LOCK_CONFIG), /* GPP_E10 : net NC is not present in the given design */ - PAD_NC(GPP_E10, UP_20K), + PAD_NC(GPP_E10, NONE), /* GPP_E11 : [] ==> MEM_STRAP_0 */ PAD_CFG_GPI_LOCK(GPP_E11, NONE, LOCK_CONFIG), /* GPP_E12 : [] ==> MEM_STRAP_3 */ @@ -215,13 +215,13 @@ /* GPP_E13 : [] ==> MEM_CH_SEL */ PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), /* GPP_E14 : net NC is not present in the given design */ - PAD_NC(GPP_E14, UP_20K), + PAD_NC(GPP_E14, NONE), /* GPP_E15 : [] ==> SOC_GPP_E15 */ - PAD_NC(GPP_E15, UP_20K), + PAD_NC(GPP_E15, NONE), /* GPP_E16 : [] ==> GPP_E16_ISH_GP10 */ - PAD_NC(GPP_E16, UP_20K), + PAD_NC(GPP_E16, NONE), /* GPP_E17 : net NC is not present in the given design */ - PAD_NC(GPP_E17, UP_20K), + PAD_NC(GPP_E17, NONE), /* GPP_E22 : [] ==> USB_C0_AUX_DC_P */ PAD_CFG_NF(GPP_E22, NONE, DEEP, NF6), @@ -240,13 +240,13 @@ /* GPP_F06 : [] ==> WLAN_COEX3 */ PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), /* GPP_F07 : net NC is not present in the given design */ - PAD_NC(GPP_F07, UP_20K), + PAD_NC(GPP_F07, NONE), /* GPP_F08 : [] ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_F08, 1, DEEP), /* GPP_F09 : net NC is not present in the given design */ - PAD_NC(GPP_F09, UP_20K), + PAD_NC(GPP_F09, NONE), /* GPP_F10 : net NC is not present in the given design */ - PAD_NC(GPP_F10, UP_20K), + PAD_NC(GPP_F10, NONE), /* GPP_F11 : [] ==> AV_GPIO_P0 */ PAD_CFG_GPO(GPP_F11, 0, DEEP), /* GPP_F12 : [] ==> AV_GPIO_P1 */ @@ -264,30 +264,30 @@ /* GPP_F18 : [] ==> AV_GPIO_P7 */ PAD_CFG_GPO(GPP_F18, 0, DEEP), /* GPP_F19 : [GPP_F19_STRAP] ==> Component NC */ - PAD_NC(GPP_F19, UP_20K), + PAD_NC(GPP_F19, NONE), /* GPP_F20 : [GPP_F20_STRAP] ==> Component NC */ - PAD_NC(GPP_F20, UP_20K), + PAD_NC(GPP_F20, NONE), /* GPP_F21 : [GPP_F21_STRAP] ==> Component NC */ - PAD_NC(GPP_F21, UP_20K), + PAD_NC(GPP_F21, NONE), /* GPP_F22 : [] ==> GPP_F22_ISH_GP8A */ - PAD_NC(GPP_F22, UP_20K), + PAD_NC(GPP_F22, NONE), /* GPP_F23 : [] ==> GPP_F23_ISH_GP9A */ - PAD_NC(GPP_F23, UP_20K), + PAD_NC(GPP_F23, NONE), /* GPP_H00 : GPP_H00_STRAP ==> Component NC */ - PAD_NC(GPP_H00, UP_20K), + PAD_NC(GPP_H00, NONE), /* GPP_H01 : GPP_H01_STRAP ==> Component NC */ - PAD_NC(GPP_H01, UP_20K), + PAD_NC(GPP_H01, NONE), /* GPP_H02 : GPP_H02_STRAP ==> Component NC */ - PAD_NC(GPP_H02, UP_20K), + PAD_NC(GPP_H02, NONE), /* GPP_H04 : [] ==> WLAN_COEX1 */ PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), /* GPP_H05 : [] ==> WLAN_COEX2 */ PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), /* GPP_H06 : net NC is not present in the given design */ - PAD_NC(GPP_H06, UP_20K), + PAD_NC(GPP_H06, NONE), /* GPP_H07 : net NC is not present in the given design */ - PAD_NC(GPP_H07, UP_20K), + PAD_NC(GPP_H07, NONE), /* GPP_H08 : [] ==> UART_DBG_TX_SOC_RX_R */ PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* GPP_H09 : [] ==> UART_SOC_TX_DBG_RX_R */ @@ -295,42 +295,42 @@ /* GPP_H10 : [] ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_H10, NONE, LOCK_CONFIG), /* GPP_H11 : net NC is not present in the given design */ - PAD_NC(GPP_H11, UP_20K), + PAD_NC(GPP_H11, NONE), /* GPP_H13 : [] ==> CPU_C10_GATE_L */ PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), /* GPP_H14 : [] ==> SLP_S0_GATE_R */ PAD_CFG_GPO(GPP_H14, 1, PLTRST), /* GPP_H15 : net NC is not present in the given design */ - PAD_NC(GPP_H15, UP_20K), + PAD_NC(GPP_H15, NONE), /* GPP_H16 : net NC is not present in the given design */ - PAD_NC(GPP_H16, UP_20K), + PAD_NC(GPP_H16, NONE), /* GPP_H17 : net NC is not present in the given design */ - PAD_NC(GPP_H17, UP_20K), + PAD_NC(GPP_H17, NONE), /* GPP_H19 : net NC is not present in the given design */ - PAD_NC(GPP_H19, UP_20K), + PAD_NC(GPP_H19, NONE), /* GPP_H20 : net NC is not present in the given design */ - PAD_NC(GPP_H20, UP_20K), + PAD_NC(GPP_H20, NONE), /* GPP_H21 : net NC is not present in the given design */ - PAD_NC(GPP_H21, UP_20K), + PAD_NC(GPP_H21, NONE), /* GPP_H22 : net NC is not present in the given design */ - PAD_NC(GPP_H22, UP_20K), + PAD_NC(GPP_H22, NONE), /* GPP_S00 : net NC is not present in the given design */ - PAD_NC(GPP_S00, UP_20K), + PAD_NC(GPP_S00, NONE), /* GPP_S01 : net NC is not present in the given design */ - PAD_NC(GPP_S01, UP_20K), + PAD_NC(GPP_S01, NONE), /* GPP_S02 : net NC is not present in the given design */ - PAD_NC(GPP_S02, UP_20K), + PAD_NC(GPP_S02, NONE), /* GPP_S03 : net NC is not present in the given design */ - PAD_NC(GPP_S03, UP_20K), + PAD_NC(GPP_S03, NONE), /* GPP_S04 : net NC is not present in the given design */ - PAD_NC(GPP_S04, UP_20K), + PAD_NC(GPP_S04, NONE), /* GPP_S05 : net NC is not present in the given design */ - PAD_NC(GPP_S05, UP_20K), + PAD_NC(GPP_S05, NONE), /* GPP_S06 : net NC is not present in the given design */ - PAD_NC(GPP_S06, UP_20K), + PAD_NC(GPP_S06, NONE), /* GPP_S07 : net NC is not present in the given design */ - PAD_NC(GPP_S07, UP_20K), + PAD_NC(GPP_S07, NONE), /* GPP_V00 : [] ==> BATLOW_L */ PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), @@ -359,9 +359,9 @@ /* GPP_V14 : [] ==> SOC_WAKE_L */ PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), /* GPP_V22 : net NC is not present in the given design */ - PAD_NC(GPP_V22, UP_20K), + PAD_NC(GPP_V22, NONE), /* GPP_V23 : net NC is not present in the given design */ - PAD_NC(GPP_V23, UP_20K), + PAD_NC(GPP_V23, NONE), }; /* Early pad configuration in bootblock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/82572?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I976a85b35c69b03f1bc0ccd2bc7df923e47be815 Gerrit-Change-Number: 82572 Gerrit-PatchSet: 4 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>

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[M] Change in coreboot[main]: device: drop unnecessary CHECK_REV_IN_OPROM_NAME option
by Matt DeVillier (Code Review) 22 May '24

22 May '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Paul Menzel. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/82598?usp=email ) Change subject: device: drop unnecessary CHECK_REV_IN_OPROM_NAME option ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82598/comment/46117c67_0693b2a1?us… : PS2, Line 13: Later it turned out that there might be a case where even that isn't : sufficient, > can i mark that one as resolved or do you have a better suggestion for this one? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6de533c536044698d85404427719b8f534870fa Gerrit-Change-Number: 82598 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 22 May 2024 20:19:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: device: drop unnecessary CHECK_REV_IN_OPROM_NAME option
by Felix Held (Code Review) 22 May '24

22 May '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Paul Menzel. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82598?usp=email to look at the new patch set (#4). Change subject: device: drop unnecessary CHECK_REV_IN_OPROM_NAME option ...................................................................... device: drop unnecessary CHECK_REV_IN_OPROM_NAME option The CHECK_REV_IN_OPROM_NAME Kconfig option was introduced to solve the problem of the PCI VID/DID combination of the Picasso iGPU not being sufficient information to know which VGA BIOS file to run, so a new function that additionally checks the PCI revision of that device was introduced. Later it turned out that there might be a case where even that isn't sufficient, so the soc_is_raven2() function is used in the remap function to always use the correct VBIOS file. Picasso is the only SoC that selected the CHECK_REV_IN_OPROM_NAME Kconfig option, so all other SoCs are unaffected by this change. Now that we use the VBIOS images with only the PCI VID and DID in the CBFS file name for Picasso, SeaBIOS will find the VBIOS with the same ID as the iGPU in CBFS and we don't need the workaround to add a third VBIOS image via VGA_BIOS_DGPU_* that has the name that SeaBIOS expects. This will result in SeaBIOS now running the VBIOS that has the same PCI VID/DID as the hardware which will be the wrong one in the RV2 silicon showing the PCO silicon PCI VID/DID, but that was also the case with the VGA_BIOS_DGPU_* workaround where the board's Kconfig just selected one of the two possible images during build time and hoped that it was the correct one for that actual hardware. The only board where this patch might cause a regression compared to the old behavior is the AMD Cereme reference board with Pollock APU, but I'm not even sure if any coreboot developer still has one of those boards, so I'm willing to accept that. To properly solve the problem with SeaBIOS using the correct VBIOS file in all cases, we'd need to generate that info during coreboot runtime and somehow pass it to SeaBIOS, but that's out of scope for this patch. TEST=On Mandolin with PCO silicon, the display output in both SeaBIOS and Ubuntu still works. Booting Windows 10 via the pre-built EDK2 payload that I'm using also resulted in the display output working. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia6de533c536044698d85404427719b8f534870fa --- M src/device/Kconfig M src/device/pci_rom.c M src/include/device/pci_rom.h M src/mainboard/amd/bilby/Kconfig M src/mainboard/amd/mandolin/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/graphics.c 7 files changed, 21 insertions(+), 81 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/82598/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6de533c536044698d85404427719b8f534870fa Gerrit-Change-Number: 82598 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com>

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[S] Change in coreboot[main]: device/pci_rom: handle non-remapped VGA_BIOS_ID
by Felix Held (Code Review) 22 May '24

22 May '24

Attention is currently required from: Matt DeVillier, Nico Huber. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/82592?usp=email ) Change subject: device/pci_rom: handle non-remapped VGA_BIOS_ID ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/82592?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7cd8e2036250f4ca2239b04cd070bbf0778b13aa Gerrit-Change-Number: 82592 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 22 May 2024 19:52:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: device: drop unnecessary CHECK_REV_IN_OPROM_NAME option
by Felix Held (Code Review) 22 May '24

22 May '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier, Paul Menzel. Felix Held has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/82598?usp=email ) Change subject: device: drop unnecessary CHECK_REV_IN_OPROM_NAME option ...................................................................... Patch Set 3: (5 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/82598/comment/f11b630b_c0731baf?us… : PS2, Line 11: which VGA BIOS file to run > worth stating it was for PCO only added that info a bit earlier in the sentence https://review.coreboot.org/c/coreboot/+/82598/comment/9838d59a_bace3af8?us… : PS2, Line 12: introduces > introduced Done https://review.coreboot.org/c/coreboot/+/82598/comment/38c8cf6b_3cf3be09?us… : PS2, Line 12: check > check*s* Done https://review.coreboot.org/c/coreboot/+/82598/comment/8ce7f96f_cfd05fce?us… : PS2, Line 13: Later it turned out that there might be a case where even that isn't : sufficient, > there was one (or two?) case(s) where the same VID/DID/revision needed different VBIOS files; no ide […] can i mark that one as resolved or do you have a better suggestion for this one? https://review.coreboot.org/c/coreboot/+/82598/comment/8f44971c_f5cb94b9?us… : PS2, Line 18: SaeaBIOS > SeaBIOS Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82598?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6de533c536044698d85404427719b8f534870fa Gerrit-Change-Number: 82598 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Comment-Date: Wed, 22 May 2024 19:52:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XL] Change in coreboot[main]: mb/system76/bonw14: Enable TAS5825M smart amp
by Tim Crawford (Code Review) 22 May '24

22 May '24

Attention is currently required from: Jeremy Soller, Tim Crawford. Hello Jeremy Soller, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/61410?usp=email to look at the new patch set (#6). Change subject: mb/system76/bonw14: Enable TAS5825M smart amp ...................................................................... mb/system76/bonw14: Enable TAS5825M smart amp The Bonobo has 2 AMPs: one for the speakers and one for the subwoofer. Smart AMP data was collected using a logic analyzer connected to the IC during system start on proprietary firmware. This data is then used to generate a C file [1]. [1]: https://github.com/system76/smart-amp Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9 Signed-off-by: Tim Crawford <tcrawford(a)system76.com> --- M src/mainboard/system76/bonw14/Kconfig M src/mainboard/system76/bonw14/Makefile.mk M src/mainboard/system76/bonw14/devicetree.cb A src/mainboard/system76/bonw14/tas5825m-normal.c A src/mainboard/system76/bonw14/tas5825m-sub.c A src/mainboard/system76/bonw14/tas5825m.c 6 files changed, 2,507 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/61410/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/61410?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5389a9890563ebd3adb20096b6225f474bc006f9 Gerrit-Change-Number: 61410 Gerrit-PatchSet: 6 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com>

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