coreboot-gerrit May 2024

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[M] Change in coreboot[main]: soc/amd/phoenix/chip.h: add USB PHY configuration for openSIL
by Felix Held (Code Review) 22 May '24

22 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82584?usp=email ) Change subject: soc/amd/phoenix/chip.h: add USB PHY configuration for openSIL ...................................................................... soc/amd/phoenix/chip.h: add USB PHY configuration for openSIL Add the USB PHY configuration structs for the openSIL case, so that those can be configured in the devicetree like in the FSP case. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ied25e90859c4b1bc9b876bed3f3c46358ca36d32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82584 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/amd/phoenix/chip.h M src/soc/amd/phoenix/chip_opensil.h 2 files changed, 50 insertions(+), 2 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/phoenix/chip.h b/src/soc/amd/phoenix/chip.h index 0fccb53..07b0dab 100644 --- a/src/soc/amd/phoenix/chip.h +++ b/src/soc/amd/phoenix/chip.h @@ -107,10 +107,10 @@ DXIO_PSPP_POWERSAVE, } pspp_policy; -#if CONFIG(PLATFORM_USES_FSP2_0) uint8_t usb_phy_custom; struct usb_phy_config usb_phy; -#else + +#if !CONFIG(PLATFORM_USES_FSP2_0) struct ddi_descriptor ddi[DDI_DESCRIPTOR_COUNT]; #endif }; diff --git a/src/soc/amd/phoenix/chip_opensil.h b/src/soc/amd/phoenix/chip_opensil.h index fcaa85c..da25a79 100644 --- a/src/soc/amd/phoenix/chip_opensil.h +++ b/src/soc/amd/phoenix/chip_opensil.h @@ -30,3 +30,51 @@ uint8_t aux_index; uint8_t hdp_index; }; + +#define USB2_PORT_COUNT 8 +#define USB3_PORT_COUNT 3 +#define USBC_COMBO_PHY_COUNT 3 + +struct fch_usb2_phy { + uint8_t compdistune; ///< COMPDISTUNE + uint8_t pllbtune; ///< PLLBTUNE + uint8_t pllitune; ///< PLLITUNE + uint8_t pllptune; ///< PLLPTUNE + uint8_t sqrxtune; ///< SQRXTUNE + uint8_t txfslstune; ///< TXFSLSTUNE + uint8_t txpreempamptune; ///< TXPREEMPAMPTUNE + uint8_t txpreemppulsetune; ///< TXPREEMPPULSETUNE + uint8_t txrisetune; ///< TXRISETUNE + uint8_t txvreftune; ///< TXVREFTUNE + uint8_t txhsxvtune; ///< TXHSXVTUNE + uint8_t txrestune; ///< TXRESTUNE +}; + +struct fch_usb3_phy { + uint8_t tx_term_ctrl; ///< tx_term_ctrl + uint8_t rx_term_ctrl; ///< rx_term_ctrl + uint8_t tx_vboost_lvl_en; ///< TX_VBOOST_LVL_EN + uint8_t tx_vboost_lvl; ///< TX_VBOOST_LVL +}; + +#define USB0_PORT0 0 +#define USB0_PORT1 1 +#define USB0_PORT2 1 +#define USB0_PORT3 3 +#define USB1_PORT0 (0<<2) +#define USB1_PORT1 (1<<2) +#define USB1_PORT2 (1<<2) +#define USB1_PORT3 (3<<2) + +#define USB_COMBO_PHY_MODE_USB_C 0 +#define USB_COMBO_PHY_MODE_USB_ONLY 1 +#define USB_COMBO_PHY_MODE_USB_DPM 2 +#define USB_COMBO_PHY_MODE_USB_DPP 3 + +struct usb_phy_config { + struct fch_usb2_phy Usb2PhyPort[USB2_PORT_COUNT]; ///< USB 2.0 Driving Strength + struct fch_usb3_phy Usb3PhyPort[USB3_PORT_COUNT]; ///< USB3 PHY Adjustment + uint8_t BatteryChargerEnable; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] + uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] + uint8_t ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/82584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ied25e90859c4b1bc9b876bed3f3c46358ca36d32 Gerrit-Change-Number: 82584 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/amd/birman/update_devicetree_phoenix_opensil: update DDI1 config
by Felix Held (Code Review) 22 May '24

22 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82583?usp=email ) Change subject: mb/amd/birman/update_devicetree_phoenix_opensil: update DDI1 config ...................................................................... mb/amd/birman/update_devicetree_phoenix_opensil: update DDI1 config Use the now common get_ddi1_type function to update the connector type of the DDI1 port to match the display output extension card plugged into the reference board. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7c51eab0d32e0a1708da415f690689a8ec38dcd3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82583 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c 1 file changed, 9 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c b/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c index 8f7803f..f0060b8 100644 --- a/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c +++ b/src/mainboard/amd/birman/update_devicetree_phoenix_opensil.c @@ -1,8 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/device.h> +#include <soc/amd/phoenix/chip.h> #include <soc/soc_util.h> #include <vendorcode/amd/opensil/chip/mpio/chip.h> +#include "display_card_type.h" #include "update_devicetree.h" static void mainboard_update_mpio(void) @@ -39,7 +41,14 @@ } } +static void mainboard_update_ddi(void) +{ + struct soc_amd_phoenix_config *cfg = config_of_soc(); + cfg->ddi[1].connector_type = get_ddi1_type(); +} + void mainboard_update_devicetree_opensil(void) { mainboard_update_mpio(); + mainboard_update_ddi(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/82583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c51eab0d32e0a1708da415f690689a8ec38dcd3 Gerrit-Change-Number: 82583 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/amd/birman: factor out get_ddi1_type
by Felix Held (Code Review) 22 May '24

22 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82582?usp=email ) Change subject: mb/amd/birman: factor out get_ddi1_type ...................................................................... mb/amd/birman: factor out get_ddi1_type Both port descriptor files used in the FSP case contain an identical get_ddi1_type implementation, so factor it out into a separate file. This will also allow using the same function in the openSIL case in a following patch. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I6f5b75b9bdbdc67901d157079785c8fa2915bf0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/82582 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/birman/Makefile.mk A src/mainboard/amd/birman/display_card_type.c A src/mainboard/amd/birman/display_card_type.h M src/mainboard/amd/birman/port_descriptors_glinda.c M src/mainboard/amd/birman/port_descriptors_phoenix.c 5 files changed, 56 insertions(+), 79 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/amd/birman/Makefile.mk b/src/mainboard/amd/birman/Makefile.mk index 2df1f59..a784d1a 100644 --- a/src/mainboard/amd/birman/Makefile.mk +++ b/src/mainboard/amd/birman/Makefile.mk @@ -4,10 +4,12 @@ bootblock-y += early_gpio.c bootblock-y += ec.c +romstage-y += display_card_type.c romstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_FSP) += port_descriptors_phoenix.c romstage-$(CONFIG_BOARD_AMD_BIRMAN_GLINDA) += port_descriptors_glinda.c ramstage-y += chromeos.c +ramstage-y += display_card_type.c ramstage-y += gpio.c ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_OPENSIL) += update_devicetree_phoenix_opensil.c ramstage-$(CONFIG_BOARD_AMD_BIRMAN_PHOENIX_FSP) += port_descriptors_phoenix.c diff --git a/src/mainboard/amd/birman/display_card_type.c b/src/mainboard/amd/birman/display_card_type.c new file mode 100644 index 0000000..21f536f --- /dev/null +++ b/src/mainboard/amd/birman/display_card_type.c @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/i2c_simple.h> +#if CONFIG(PLATFORM_USES_FSP2_0) +#include <soc/platform_descriptors.h> +#else +#include <soc/amd/phoenix/chip_opensil.h> +#endif +#include <types.h> +#include "display_card_type.h" + +uint8_t get_ddi1_type(void) +{ + const uint8_t eeprom_i2c_bus = 2; + const uint8_t eeprom_i2c_address = 0x55; + const uint16_t eeprom_connector_type_offset = 2; + uint8_t eeprom_connector_type_data[2]; + uint16_t connector_type; + + if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address, + eeprom_connector_type_offset, eeprom_connector_type_data, + sizeof(eeprom_connector_type_data))) { + printk(BIOS_NOTICE, + "Display connector type couldn't be determined. Disabling DDI1.\n"); + return DDI_UNUSED_TYPE; + } + + connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8; + + switch (connector_type) { + case 0x0c: + printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n"); + return DDI_HDMI; + case 0x13: + printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n"); + return DDI_DP; + case 0x14: + printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n"); + return DDI_EDP; + case 0x17: + printk(BIOS_DEBUG, "Configuring DDI1 as USB-C.\n"); + return DDI_DP_W_TYPEC; + default: + printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n", + connector_type); + return DDI_UNUSED_TYPE; + } +} diff --git a/src/mainboard/amd/birman/display_card_type.h b/src/mainboard/amd/birman/display_card_type.h new file mode 100644 index 0000000..bb23fd4 --- /dev/null +++ b/src/mainboard/amd/birman/display_card_type.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +uint8_t get_ddi1_type(void); diff --git a/src/mainboard/amd/birman/port_descriptors_glinda.c b/src/mainboard/amd/birman/port_descriptors_glinda.c index a0dbd17..2af7d26 100644 --- a/src/mainboard/amd/birman/port_descriptors_glinda.c +++ b/src/mainboard/amd/birman/port_descriptors_glinda.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <console/console.h> -#include <device/i2c_simple.h> #include <gpio.h> #include <soc/platform_descriptors.h> #include <types.h> +#include "display_card_type.h" /* TODO: Update for birman */ @@ -79,44 +78,6 @@ } }; -static uint8_t get_ddi1_type(void) -{ - const uint8_t eeprom_i2c_bus = 2; - const uint8_t eeprom_i2c_address = 0x55; - const uint16_t eeprom_connector_type_offset = 2; - uint8_t eeprom_connector_type_data[2]; - uint16_t connector_type; - - if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address, - eeprom_connector_type_offset, eeprom_connector_type_data, - sizeof(eeprom_connector_type_data))) { - printk(BIOS_NOTICE, - "Display connector type couldn't be determined. Disabling DDI1.\n"); - return DDI_UNUSED_TYPE; - } - - connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8; - - switch (connector_type) { - case 0x0c: - printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n"); - return DDI_HDMI; - case 0x13: - printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n"); - return DDI_DP; - case 0x14: - printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n"); - return DDI_EDP; - case 0x17: - printk(BIOS_DEBUG, "Configuring DDI1 as USB-C.\n"); - return DDI_DP_W_TYPEC; - default: - printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n", - connector_type); - return DDI_UNUSED_TYPE; - } -} - void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) diff --git a/src/mainboard/amd/birman/port_descriptors_phoenix.c b/src/mainboard/amd/birman/port_descriptors_phoenix.c index 8ab7417..da07e31 100644 --- a/src/mainboard/amd/birman/port_descriptors_phoenix.c +++ b/src/mainboard/amd/birman/port_descriptors_phoenix.c @@ -1,11 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <device/i2c_simple.h> #include <gpio.h> #include <soc/platform_descriptors.h> #include <soc/soc_util.h> #include <types.h> +#include "display_card_type.h" #define phx_mxm_dxio_descriptor { \ .engine_type = PCIE_ENGINE, \ @@ -163,44 +163,6 @@ } }; -static uint8_t get_ddi1_type(void) -{ - const uint8_t eeprom_i2c_bus = 2; - const uint8_t eeprom_i2c_address = 0x55; - const uint16_t eeprom_connector_type_offset = 2; - uint8_t eeprom_connector_type_data[2]; - uint16_t connector_type; - - if (i2c_2ba_read_bytes(eeprom_i2c_bus, eeprom_i2c_address, - eeprom_connector_type_offset, eeprom_connector_type_data, - sizeof(eeprom_connector_type_data))) { - printk(BIOS_NOTICE, - "Display connector type couldn't be determined. Disabling DDI1.\n"); - return DDI_UNUSED_TYPE; - } - - connector_type = eeprom_connector_type_data[1] | eeprom_connector_type_data[0] << 8; - - switch (connector_type) { - case 0x0c: - printk(BIOS_DEBUG, "Configuring DDI1 as HDMI.\n"); - return DDI_HDMI; - case 0x13: - printk(BIOS_DEBUG, "Configuring DDI1 as DP.\n"); - return DDI_DP; - case 0x14: - printk(BIOS_DEBUG, "Configuring DDI1 as eDP.\n"); - return DDI_EDP; - case 0x17: - printk(BIOS_DEBUG, "Configuring DDI1 as USB-C.\n"); - return DDI_DP_W_TYPEC; - default: - printk(BIOS_WARNING, "Unexpected display connector type %x. Disabling DDI1.\n", - connector_type); - return DDI_UNUSED_TYPE; - } -} - void mainboard_get_dxio_ddi_descriptors( const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) -- To view, visit https://review.coreboot.org/c/coreboot/+/82582?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6f5b75b9bdbdc67901d157079785c8fa2915bf0c Gerrit-Change-Number: 82582 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/amd/birman/devicetree_phoenix_opensil: add static DDI configuration
by Felix Held (Code Review) 22 May '24

22 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82581?usp=email ) Change subject: mb/amd/birman/devicetree_phoenix_opensil: add static DDI configuration ...................................................................... mb/amd/birman/devicetree_phoenix_opensil: add static DDI configuration Add a static DDI port configuration to the devicetree used in the Phoenix with openSIL case. The configuration is taken from the birman_ddi_descriptors array in port_descriptor_phoenix.c. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7b85b04114591f3e9da183019c98ca2cb08e59da Reviewed-on: https://review.coreboot.org/c/coreboot/+/82581 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/birman/devicetree_phoenix_opensil.cb 1 file changed, 26 insertions(+), 0 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved Varshit Pandya: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb index bca4559..055d9e1 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb @@ -41,6 +41,32 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works + register "ddi[0]" = "{ + .connector_type = DDI_EDP, + .aux_index = 0, + .hdp_index = 0, + }" + register "ddi[1]" = "{ + .connector_type = DDI_HDMI, + .aux_index = 1, + .hdp_index = 1, + }" + register "ddi[2]" = "{ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = 2, + .hdp_index = 2, + }" + register "ddi[3]" = "{ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = 3, + .hdp_index = 3, + }" + register "ddi[4]" = "{ + .connector_type = DDI_DP_W_TYPEC, + .aux_index = 4, + .hdp_index = 4, + }" + device domain 0 on device ref iommu on end chip vendorcode/amd/opensil/chip/mpio -- To view, visit https://review.coreboot.org/c/coreboot/+/82581?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7b85b04114591f3e9da183019c98ca2cb08e59da Gerrit-Change-Number: 82581 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/amd/phoenix/chip.h: add DDI configuration for openSIL
by Felix Held (Code Review) 22 May '24

22 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82580?usp=email ) Change subject: soc/amd/phoenix/chip.h: add DDI configuration for openSIL ...................................................................... soc/amd/phoenix/chip.h: add DDI configuration for openSIL In the FSP case, the DDI descriptors aren't part of the devicetree and are instead retrieved in romstage by calling the mainboard's mainboard_get_dxio_ddi_descriptors function which allows updating the descriptors during romstage where the devicetree is static. In the openSIL case, the DDI configuration is first needed in ramstage, so we can put this info into the devicetree and update it if needed in ramstage. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I3de12ff6af42e38751a3016efa313613677fa87a Reviewed-on: https://review.coreboot.org/c/coreboot/+/82580 Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/soc/amd/phoenix/chip.h A src/soc/amd/phoenix/chip_opensil.h 2 files changed, 36 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Varshit Pandya: Looks good to me, approved Matt DeVillier: Looks good to me, approved diff --git a/src/soc/amd/phoenix/chip.h b/src/soc/amd/phoenix/chip.h index e3cadc2..0fccb53 100644 --- a/src/soc/amd/phoenix/chip.h +++ b/src/soc/amd/phoenix/chip.h @@ -15,6 +15,8 @@ #include <types.h> #if CONFIG(PLATFORM_USES_FSP2_0) #include <vendorcode/amd/fsp/phoenix/FspUsb.h> +#else +#include "chip_opensil.h" #endif struct soc_amd_phoenix_config { @@ -108,6 +110,8 @@ #if CONFIG(PLATFORM_USES_FSP2_0) uint8_t usb_phy_custom; struct usb_phy_config usb_phy; +#else + struct ddi_descriptor ddi[DDI_DESCRIPTOR_COUNT]; #endif }; diff --git a/src/soc/amd/phoenix/chip_opensil.h b/src/soc/amd/phoenix/chip_opensil.h new file mode 100644 index 0000000..fcaa85c --- /dev/null +++ b/src/soc/amd/phoenix/chip_opensil.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <types.h> + +#define DDI_DESCRIPTOR_COUNT 5 + +/* DDI display connector type */ +enum ddi_connector_type { + DDI_DP = 0, // DP + DDI_EDP, // eDP + DDI_SINGLE_LINK_DVI, // Single Link DVI-D + DDI_DUAL_LINK_DVI, // Dual Link DVI-D + DDI_HDMI, // HDMI + DDI_DP_TO_VGA, // DP-to-VGA + DDI_DP_TO_LVDS, // DP-to-LVDS + DDI_NUTMEG_DP_TO_VGA, // Hudson-2 NutMeg DP-to-VGA + DDI_SINGLE_LINK_DVI_I, // Single Link DVI-I + DDI_DP_W_TYPEC, // DP with USB type C + DDI_DP_WO_TYPEC, // DP without USB type C + DDI_EDP_TO_LVDS, // eDP-to-LVDS translator chip without AMD SW init + DDI_EDP_TO_LVDS_SW, // eDP-to-LVDS translator which requires AMD SW init + DDI_AUTO_DETECT, // VBIOS auto detect connector type + DDI_UNUSED_TYPE, // UnusedType + DDI_MAX_CONNECTOR_TYPE // Not valid value, used to verify input +}; + +/* DDI Descriptor: used for configuring display outputs */ +struct ddi_descriptor { + uint8_t connector_type; // see ddi_connector_type + uint8_t aux_index; + uint8_t hdp_index; +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/82580?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3de12ff6af42e38751a3016efa313613677fa87a Gerrit-Change-Number: 82580 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/amd/birman/devicetree_phoenix_opensil: remove unexpected '<'
by Felix Held (Code Review) 22 May '24

22 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82579?usp=email ) Change subject: mb/amd/birman/devicetree_phoenix_opensil: remove unexpected '<' ...................................................................... mb/amd/birman/devicetree_phoenix_opensil: remove unexpected '<' Remove the unexpected '<' char at the end of the comment about the PSPP policy config. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Id821351ce3a7a2b7844d8e7478fa3de3227a7da9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82579 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/mainboard/amd/birman/devicetree_phoenix_opensil.cb 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Matt DeVillier: Looks good to me, approved Varshit Pandya: Looks good to me, approved Elyes Haouas: Looks good to me, approved diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb index d1b5e11..bca4559 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb @@ -39,7 +39,7 @@ register "s0ix_enable" = "true" - register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works< + register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works device domain 0 on device ref iommu on end -- To view, visit https://review.coreboot.org/c/coreboot/+/82579?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id821351ce3a7a2b7844d8e7478fa3de3227a7da9 Gerrit-Change-Number: 82579 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/amd/phoenix/chipset_*.cb: remove TODO
by Felix Held (Code Review) 22 May '24

22 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82578?usp=email ) Change subject: soc/amd/phoenix/chipset_*.cb: remove TODO ...................................................................... soc/amd/phoenix/chipset_*.cb: remove TODO Remove the TODO to update the chipset devicetree for Phoenix, since this has already been done. When re-checking the chipset devicetree, I found conflicting information about the existence of the PCI bridge to an external PCIe port on bus 0 device 1 function 5, but after looking into this, I'm reasonably certain that it either doesn't exist or at least wouldn't be usable, so I won't add that one to the chipset devicetree. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I8f0e1540ed45408e86186253d3982a7ba0065ac6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82578 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Reviewed-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- M src/soc/amd/phoenix/chipset_fsp.cb M src/soc/amd/phoenix/chipset_opensil.cb 2 files changed, 0 insertions(+), 4 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved Varshit Pandya: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/phoenix/chipset_fsp.cb b/src/soc/amd/phoenix/chipset_fsp.cb index 08ee8c2..2d1e170 100644 --- a/src/soc/amd/phoenix/chipset_fsp.cb +++ b/src/soc/amd/phoenix/chipset_fsp.cb @@ -1,5 +1,3 @@ -# TODO: Update for Phoenix - chip soc/amd/phoenix device cpu_cluster 0 on ops amd_cpu_bus_ops diff --git a/src/soc/amd/phoenix/chipset_opensil.cb b/src/soc/amd/phoenix/chipset_opensil.cb index c11975c..0c5cfbc 100644 --- a/src/soc/amd/phoenix/chipset_opensil.cb +++ b/src/soc/amd/phoenix/chipset_opensil.cb @@ -1,5 +1,3 @@ -# TODO: Update for Phoenix - chip soc/amd/phoenix device cpu_cluster 0 on ops amd_cpu_bus_ops -- To view, visit https://review.coreboot.org/c/coreboot/+/82578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f0e1540ed45408e86186253d3982a7ba0065ac6 Gerrit-Change-Number: 82578 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/intel/archercity_crb: Fix build for specific configurations
by Felix Held (Code Review) 22 May '24

22 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82168?usp=email ) Change subject: mb/intel/archercity_crb: Fix build for specific configurations ...................................................................... mb/intel/archercity_crb: Fix build for specific configurations Guard OCP functions calls to allow builds without OCP drivers. Change-Id: Ie9a82387366a8bb3387bcba3ec7a4c7f0100f78c Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82168 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/archercity_crb/romstage.c M src/mainboard/intel/archercity_crb/util.c 2 files changed, 18 insertions(+), 15 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve diff --git a/src/mainboard/intel/archercity_crb/romstage.c b/src/mainboard/intel/archercity_crb/romstage.c index ff56f59..9189099 100644 --- a/src/mainboard/intel/archercity_crb/romstage.c +++ b/src/mainboard/intel/archercity_crb/romstage.c @@ -11,7 +11,8 @@ void mainboard_ewl_check(void) { - get_ewl(); + if (CONFIG(OCP_EWL)) + get_ewl(); } static void mainboard_config_iio(FSPM_UPD *mupd) @@ -36,21 +37,23 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) { /* Setup FSP log */ - mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, - FSP_LOG_DEFAULT); - if (mupd->FspmConfig.SerialIoUartDebugEnable) { - mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range( - FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); - /* If serialDebugMsgLvl less than 1, disable FSP memory train results */ - if (mupd->FspmConfig.serialDebugMsgLvl <= 1) { - printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n"); - mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; + if (CONFIG(OCP_VPD)) { + mupd->FspmConfig.SerialIoUartDebugEnable = get_bool_from_vpd(FSP_LOG, + FSP_LOG_DEFAULT); + if (mupd->FspmConfig.SerialIoUartDebugEnable) { + mupd->FspmConfig.serialDebugMsgLvl = get_int_from_vpd_range( + FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); + /* If serialDebugMsgLvl less than 1, disable FSP memory train results */ + if (mupd->FspmConfig.serialDebugMsgLvl <= 1) { + printk(BIOS_DEBUG, "Setting serialDebugMsgLvlTrainResults to 0\n"); + mupd->FspmConfig.serialDebugMsgLvlTrainResults = 0x0; + } } - } - /* FSP Dfx PMIC Secure mode */ - mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range( - FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2); + /* FSP Dfx PMIC Secure mode */ + mupd->FspmConfig.DfxPmicSecureMode = get_int_from_vpd_range( + FSP_PMIC_SECURE_MODE, FSP_PMIC_SECURE_MODE_DEFAULT, 0, 2); + } /* Set Rank Margin Tool to disable. */ mupd->FspmConfig.EnableRMT = 0x0; diff --git a/src/mainboard/intel/archercity_crb/util.c b/src/mainboard/intel/archercity_crb/util.c index 5197b23..0dac1e1 100644 --- a/src/mainboard/intel/archercity_crb/util.c +++ b/src/mainboard/intel/archercity_crb/util.c @@ -4,7 +4,7 @@ #include <soc/chip_common.h> #include <soc/util.h> -#if CONFIG(SOC_INTEL_HAS_CXL) +#if CONFIG(SOC_INTEL_HAS_CXL) && CONFIG(OCP_VPD) enum xeonsp_cxl_mode get_cxl_mode(void) { int ocp_cxl_mode = get_cxl_mode_from_vpd(); -- To view, visit https://review.coreboot.org/c/coreboot/+/82168?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9a82387366a8bb3387bcba3ec7a4c7f0100f78c Gerrit-Change-Number: 82168 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: util/intelp2m: Add support for Emmitsburg macro generation
by Fabian Meyer (Code Review) 22 May '24

22 May '24

Attention is currently required from: Felix Held, Maxim. Fabian Meyer has posted comments on this change by Fabian Meyer. ( https://review.coreboot.org/c/coreboot/+/82204?usp=email ) Change subject: util/intelp2m: Add support for Emmitsburg macro generation ...................................................................... Patch Set 4: (1 comment) File util/intelp2m/platforms/ebg/template.go: https://review.coreboot.org/c/coreboot/+/82204/comment/009bbbb7_8ce793a0?us… : PS3, Line 17: GPP_S > not sure if there's a difference between GPP and GPPC, but in util/inteltool/gpio_names/emmitsburg. […] You are correct, it's also GPPC_S in src/soc/intel/xeon_sp/ebg/include/soc/gpio_soc_defs.h. However, this makes no difference to intelp2m's output (I just tested it). I pushed the change nonetheless to be more correct. -- To view, visit https://review.coreboot.org/c/coreboot/+/82204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib7ded47fb1c0b87ebb3cecaf3e41319ac552b797 Gerrit-Change-Number: 82204 Gerrit-PatchSet: 4 Gerrit-Owner: Fabian Meyer <fabian(a)meyfa.net> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 22 May 2024 14:55:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: util/intelp2m: Add support for Emmitsburg macro generation
by Fabian Meyer (Code Review) 22 May '24

22 May '24

Attention is currently required from: Fabian Meyer, Maxim. Hello Maxim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82204?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+2 by Maxim, Verified+1 by build bot (Jenkins) Change subject: util/intelp2m: Add support for Emmitsburg macro generation ...................................................................... util/intelp2m: Add support for Emmitsburg macro generation Test: Generated GPIO for ASRock Rack SPC741D8-2L2T/BCM. Change-Id: Ib7ded47fb1c0b87ebb3cecaf3e41319ac552b797 Signed-off-by: Fabian Meyer <fabian.meyer(a)student.kit.edu> Co-authored-by: Yussuf Khalil <yussuf.khalil(a)kit.edu> --- M util/intelp2m/config/config.go M util/intelp2m/main.go M util/intelp2m/parser/parser.go A util/intelp2m/platforms/ebg/macro.go A util/intelp2m/platforms/ebg/template.go 5 files changed, 157 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/82204/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82204?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib7ded47fb1c0b87ebb3cecaf3e41319ac552b797 Gerrit-Change-Number: 82204 Gerrit-PatchSet: 4 Gerrit-Owner: Fabian Meyer <fabian(a)meyfa.net> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Attention: Fabian Meyer <fabian(a)meyfa.net>

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