coreboot-gerrit May 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: vc/edk2-stable202302: Add config guards to support FSP 2.4
by Subrata Banik (Code Review) 23 May '24

23 May '24

Attention is currently required from: Appukuttan V K, Ronak Kanabar. Subrata Banik has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82425?usp=email ) Change subject: vc/edk2-stable202302: Add config guards to support FSP 2.4 ...................................................................... Patch Set 12: (1 comment) File src/vendorcode/intel/edk2/edk2-stable202302/IntelFsp2Pkg/Include/FspEas/FspApi.h: https://review.coreboot.org/c/coreboot/+/82425/comment/d22dde2c_8d47e188?us… : PS12, Line 257: PLATFORM_USES_FSP2_X86_32 as per this CL, FSPM_ARCH2_UPD/FSPS_ARCH2_UPD only enable for PLATFORM_USES_FSP2_X86_64,but that is not the case. Take an example of xeon_sp where the platform still selects PLATFORM_USES_FSP2_X86_32 but FSP header declares FSPS_ARCH2_UPD/FSPM_ARCH2_UPD datatype. worth changing the guard from PLATFORM_USES_FSP2_X86_32 to PLATFORM_USES_FSP2_4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82425?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idc849de73723036323f81dfd055730f6669cd52e Gerrit-Change-Number: 82425 Gerrit-PatchSet: 12 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 23 May 2024 10:42:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: AUTHORS: Update with 24.05 release info
by Elyes Haouas (Code Review) 23 May '24

23 May '24

Attention is currently required from: Martin L Roth. Elyes Haouas has posted comments on this change by Martin L Roth. ( https://review.coreboot.org/c/coreboot/+/82617?usp=email ) Change subject: AUTHORS: Update with 24.05 release info ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82617?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb53c62c9a122ccdf2548cc2eebc8b0316a844ef Gerrit-Change-Number: 82617 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 23 May 2024 10:20:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/pcengines/apu2/mainboard: fix up ECC scrubber configuration
by Krystian Hebel (Code Review) 23 May '24

23 May '24

Attention is currently required from: Felix Held, Michał Żygowski, Nico Huber, Piotr Król. Krystian Hebel has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/79612?usp=email ) Change subject: mb/pcengines/apu2/mainboard: fix up ECC scrubber configuration ...................................................................... Patch Set 8: (1 comment) Patchset: PS8: > ^ that was meant to be marked as unresolved Which version of AGESA binary (version, hash, source) are you testing with? -- To view, visit https://review.coreboot.org/c/coreboot/+/79612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifb0cb117bedf900642e93c556a64800e1e52b6ea Gerrit-Change-Number: 79612 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Thu, 23 May 2024 10:07:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/gnr/soc_iio: Remove unused <string.h>
by Lean Sheng Tan (Code Review) 23 May '24

23 May '24

Attention is currently required from: Arthur Heymans, Christian Walter, Elyes Haouas, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu. Lean Sheng Tan has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82618?usp=email ) Change subject: soc/intel/xeon_sp/gnr/soc_iio: Remove unused <string.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d4500edaa0739921831a3b04131046599c35a87 Gerrit-Change-Number: 82618 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 23 May 2024 09:46:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add IIO config utils
by Shuo Liu (Code Review) 23 May '24

23 May '24

Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/81318?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Add IIO config utils ...................................................................... Patch Set 52: (1 comment) File src/soc/intel/xeon_sp/gnr/soc_iio.c: https://review.coreboot.org/c/coreboot/+/81318/comment/002f5938_2f52d98c?us… : PS52, Line 4: <string.h> > is unused […] Good catch, thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/81318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Gerrit-Change-Number: 81318 Gerrit-PatchSet: 52 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 23 May 2024 09:45:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/gnr/soc_iio: Remove unused <string.h>
by Shuo Liu (Code Review) 23 May '24

23 May '24

Attention is currently required from: Arthur Heymans, Christian Walter, Elyes Haouas, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82618?usp=email ) Change subject: soc/intel/xeon_sp/gnr/soc_iio: Remove unused <string.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d4500edaa0739921831a3b04131046599c35a87 Gerrit-Change-Number: 82618 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 23 May 2024 09:45:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/brox: Add romstage early graphics
by Sowmya Aralguppe (Code Review) 23 May '24

23 May '24

Attention is currently required from: Ashish Kumar Mishra, Karthik Ramasubramanian, Krishna P Bhat D, Paul Menzel, Shelley Chen. Hello Ashish Kumar Mishra, Karthik Ramasubramanian, Krishna P Bhat D, Shelley Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81931?usp=email to look at the new patch set (#10). Change subject: mb/google/brox: Add romstage early graphics ...................................................................... mb/google/brox: Add romstage early graphics Select MAINBOARD_USE_EARLY_LIBGFXINIT for brox to enable SOL image. This patch enables Sign of Life image during MRC training. BUG=b:335369811 TEST=Able to boot to ChromeOS with SOL image. CPU log: [0m[DEBUG] Boot Count incremented to 21[0m [0m[INFO ] CBFS: Found 'fspm.bin' @0x90f80 size 0xd0000 in mcache @0xfef89b10[0m [0m[INFO ] VB2:vb2_digest_init() 851968 bytes, hash algo 2, HW acceleration enabled[0m [0m[DEBUG] FMAP: area RW_MRC_CACHE found @ f10000 (65536 bytes)[0m [1m[NOTE ] MRC: no data in 'RW_MRC_CACHE'[0m [0m[SPEW ] bootmode is set to: 0 (boot with full config)[0m [0.384818] DP PHY mode status not complete [0.388911] DP PHY mode status not complete [0.393197] DP PHY mode status not complete [0.397484] DP PHY mode status not complete [0.401771] DP PHY mode status not complete [0.406057] DP PHY mode status not complete [0.410345] DP PHY mode status not complete [0.414632] DP PHY mode status not complete [0.418916] DP PHY mode status not complete [0.423203] DP PHY mode status not complete [0.427491] DP PHY mode status not complete [0.431777] DP PHY mode status not complete [0m[INFO ] Informing user on-display of memory training.[0m [0m[DEBUG] FMAP: area COREBOOT found @ 1877000 (7901184 bytes)[0m [1;4m[WARN ] CBFS: 'preram_locales' not found.[0m [7m[ERROR] ux_locales_get_text: preram_locales not found.[0m [0m[DEBUG] FMAP: area RW_ELOG found @ f20000 (16384 bytes)[0m [0m[INFO ] ELOG: NV offset 0xf20000 size 0x4000[0m [0m[INFO ] ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024[0m brox-rev0 ~ # elogtool list 0 | 2024-05-10 02:26:07-0700 | Log area cleared | 4088 1 | 2024-05-10 02:26:07-0700 | Early Sign of Life | MRC Early SOL Screen Shown 2 | 2024-05-10 02:26:51-0700 | Memory Cache Update | Normal | Success 3 | 2024-05-10 02:27:09-0700 | System boot | 4 4 | 2024-05-10 02:27:09-0700 | Firmware Splash Screen | Enabled 5 | 2024-05-10 02:27:11-0700 | System Reset 6 | 2024-05-10 02:27:11-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown 7 | 2024-05-10 02:27:18-0700 | ACPI Enter | S5 8 | 2024-05-10 02:27:36-0700 | System boot | 5 9 | 2024-05-10 02:27:36-0700 | Firmware Splash Screen | Enabled 10 | 2024-05-10 02:27:37-0700 | System Reset 11 | 2024-05-10 02:27:37-0700 | Firmware vboot info | boot_mode=Developer | fw_tried=A | fw_try_count=0 | fw_prev_tried=A | fw_prev_result=Unknown Change-Id: I1d4795825960bc58f8f7ef494b01aa975f3bc346 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> --- M src/mainboard/google/brox/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/81931/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/81931?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d4795825960bc58f8f7ef494b01aa975f3bc346 Gerrit-Change-Number: 81931 Gerrit-PatchSet: 10 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Dump proximity domain info per types
by Lean Sheng Tan (Code Review) 23 May '24

23 May '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82292?usp=email ) Change subject: soc/intel/xeon_sp: Dump proximity domain info per types ...................................................................... soc/intel/xeon_sp: Dump proximity domain info per types Some proximity domain info are type specifics, e.g. base/size/dev are effective for PD_TYPE_GENERIC_INITIATOR, but not for PD_TYPE_PROCESSOR. Dump info per their type. TEST=Build and boot on intel/archercity Change-Id: I7e722a0577bba954efba3e91cc152c758c001d68 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82292 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/numa.c 1 file changed, 6 insertions(+), 3 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/xeon_sp/numa.c b/src/soc/intel/xeon_sp/numa.c index 81331ed..1f0b9a3 100644 --- a/src/soc/intel/xeon_sp/numa.c +++ b/src/soc/intel/xeon_sp/numa.c @@ -19,9 +19,12 @@ printk(BIOS_DEBUG, "\tproximity domain %d:\n", i); printk(BIOS_DEBUG, "\t\ttype:%d\n", pds.pds[i].pd_type); printk(BIOS_DEBUG, "\t\tsocket_bitmap:0x%x\n", pds.pds[i].socket_bitmap); - printk(BIOS_DEBUG, "\t\tdevice:%s\n", pds.pds[i].dev ? dev_path(pds.pds[i].dev) : ""); - printk(BIOS_DEBUG, "\t\tbase(64MB):0x%x\n", pds.pds[i].base); - printk(BIOS_DEBUG, "\t\tsize(64MB):0x%x\n", pds.pds[i].size); + if (pds.pds[i].pd_type == PD_TYPE_GENERIC_INITIATOR) { + printk(BIOS_DEBUG, "\t\tdevice:%s\n", + pds.pds[i].dev ? dev_path(pds.pds[i].dev) : ""); + printk(BIOS_DEBUG, "\t\tbase(64MB):0x%x\n", pds.pds[i].base); + printk(BIOS_DEBUG, "\t\tsize(64MB):0x%x\n", pds.pds[i].size); + } } } -- To view, visit https://review.coreboot.org/c/coreboot/+/82292?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e722a0577bba954efba3e91cc152c758c001d68 Gerrit-Change-Number: 82292 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Move proximity domain setting up
by Lean Sheng Tan (Code Review) 23 May '24

23 May '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82267?usp=email ) Change subject: soc/intel/xeon_sp: Move proximity domain setting up ...................................................................... soc/intel/xeon_sp: Move proximity domain setting up Move proximity domain setting up to ahead of attach_iio_stacks() so that proximity domain info could be ready before attach_iio_stacks()/create_xeonsp_domains(). For example in SPR, is_iio_cxl_stack_res() refers to proximity domain info, and it will be called in create_xeonsp_domains(). TEST=Build and boot on intel/archercity No significant boot log difference except for proximity domain dump info display are moved ahead (with correct contents). Change-Id: I594f0ec0c23e3b62c3bdd917ebf6e45be6e4069e Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82267 Reviewed-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/gnr/chip.c M src/soc/intel/xeon_sp/include/soc/numa.h M src/soc/intel/xeon_sp/numa.c M src/soc/intel/xeon_sp/skx/chip.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/uncore.c 8 files changed, 21 insertions(+), 15 deletions(-) Approvals: Patrick Rudolph: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 8b9a673..e6b2bdb 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -12,6 +12,7 @@ #include <intelblocks/p2sb.h> #include <soc/acpi.h> #include <soc/chip_common.h> +#include <soc/numa.h> #include <soc/pch.h> #include <soc/soc_pch.h> #include <soc/ramstage.h> @@ -167,6 +168,7 @@ printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(); + setup_pds(); attach_iio_stacks(); override_hpet_ioapic_bdf(); diff --git a/src/soc/intel/xeon_sp/gnr/chip.c b/src/soc/intel/xeon_sp/gnr/chip.c index 2345894..aa9b378 100644 --- a/src/soc/intel/xeon_sp/gnr/chip.c +++ b/src/soc/intel/xeon_sp/gnr/chip.c @@ -4,6 +4,7 @@ #include <intelblocks/pmclib.h> #include <soc/pm.h> #include <soc/chip_common.h> +#include <soc/numa.h> #include <soc/ramstage.h> #include "chip.h" @@ -38,6 +39,7 @@ printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(); + setup_pds(); attach_iio_stacks(); pch_enable_ioapic(); diff --git a/src/soc/intel/xeon_sp/include/soc/numa.h b/src/soc/intel/xeon_sp/include/soc/numa.h index 7bc86ae..d124517 100644 --- a/src/soc/intel/xeon_sp/include/soc/numa.h +++ b/src/soc/intel/xeon_sp/include/soc/numa.h @@ -57,9 +57,7 @@ extern struct proximity_domains pds; -void dump_pds(void); -void fill_pds(void); -void fill_pd_distances(void); +void setup_pds(void); /* * Return the total size of memory regions in generic initiator affinity diff --git a/src/soc/intel/xeon_sp/numa.c b/src/soc/intel/xeon_sp/numa.c index 69ca063..81331ed 100644 --- a/src/soc/intel/xeon_sp/numa.c +++ b/src/soc/intel/xeon_sp/numa.c @@ -11,7 +11,7 @@ #include <soc/util.h> #include <types.h> -void dump_pds(void) +static void dump_pds(void) { printk(BIOS_DEBUG, "====== Proximity Domain Dump ======\n"); printk(BIOS_DEBUG, "number of proximity domains: %d\n", pds.num_pds); @@ -25,7 +25,7 @@ } } -void fill_pds(void) +static void fill_pds(void) { uint8_t num_sockets = soc_get_num_cpus(); uint8_t num_cxlnodes = get_cxl_node_count(); @@ -151,7 +151,7 @@ #define PD_DISTANCE_MAX 0xFF #define PD_DISTANCE_IO_EXTRA 0x01 -void fill_pd_distances(void) +static void fill_pd_distances(void) { for (int i = 0; i < pds.num_pds; i++) { for (int j = 0; j < pds.num_pds; j++) { @@ -173,3 +173,10 @@ } } } + +void setup_pds(void) +{ + fill_pds(); + fill_pd_distances(); + dump_pds(); +} diff --git a/src/soc/intel/xeon_sp/skx/chip.c b/src/soc/intel/xeon_sp/skx/chip.c index 903d0cc..37535a3 100644 --- a/src/soc/intel/xeon_sp/skx/chip.c +++ b/src/soc/intel/xeon_sp/skx/chip.c @@ -7,6 +7,7 @@ #include <intelblocks/acpi.h> #include <soc/acpi.h> #include <soc/chip_common.h> +#include <soc/numa.h> #include <soc/pch.h> #include <soc/soc_pch.h> #include <soc/ramstage.h> @@ -42,6 +43,7 @@ printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(); + setup_pds(); attach_iio_stacks(); override_hpet_ioapic_bdf(); diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index ec23940..1eab917 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -125,6 +125,7 @@ printk(BIOS_DEBUG, "coreboot: calling fsp_silicon_init\n"); fsp_silicon_init(); + setup_pds(); attach_iio_stacks(); override_hpet_ioapic_bdf(); diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index 9ad09f4..17addfc 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -90,6 +90,9 @@ */ bool is_iio_cxl_stack_res(const STACK_RES *res) { + /* pds should be setup ahead of this call */ + assert(pds.num_pds); + for (uint8_t i = 0; i < pds.num_pds; i++) { if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR) continue; diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index efa61b7..4c22685 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -336,15 +336,6 @@ { int index = 0; - static bool once; - if (!once) { - /* Construct NUMA data structure. This is needed for CXL. */ - fill_pds(); - fill_pd_distances(); - dump_pds(); - once = true; - } - /* Read standard PCI resources. */ pci_dev_read_resources(dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/82267?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I594f0ec0c23e3b62c3bdd917ebf6e45be6e4069e Gerrit-Change-Number: 82267 Gerrit-PatchSet: 6 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/brox: Add romstage early graphics
by Sowmya Aralguppe (Code Review) 23 May '24

23 May '24

Attention is currently required from: Ashish Kumar Mishra, Karthik Ramasubramanian, Krishna P Bhat D, Paul Menzel, Shelley Chen. Hello Ashish Kumar Mishra, Karthik Ramasubramanian, Krishna P Bhat D, Shelley Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81931?usp=email to look at the new patch set (#9). Change subject: mb/google/brox: Add romstage early graphics ...................................................................... mb/google/brox: Add romstage early graphics Select MAINBOARD_USE_EARLY_LIBGFXINIT for brox to enable SOL image. This patch enables Sign of Life image during MRC training. BUG=b:335369811 TEST=Able to boot to ChromeOS with SOL image. CPU log: [0m[DEBUG] Boot Count incremented to 21[0m [0m[INFO ] CBFS: Found 'fspm.bin' @0x90f80 size 0xd0000 in mcache @0xfef89b10[0m [0m[INFO ] VB2:vb2_digest_init() 851968 bytes, hash algo 2, HW acceleration enabled[0m [0m[DEBUG] FMAP: area RW_MRC_CACHE found @ f10000 (65536 bytes)[0m [1m[NOTE ] MRC: no data in 'RW_MRC_CACHE'[0m [0m[SPEW ] bootmode is set to: 0 (boot with full config)[0m [0.384818] DP PHY mode status not complete [0.388911] DP PHY mode status not complete [0.393197] DP PHY mode status not complete [0.397484] DP PHY mode status not complete [0.401771] DP PHY mode status not complete [0.406057] DP PHY mode status not complete [0.410345] DP PHY mode status not complete [0.414632] DP PHY mode status not complete [0.418916] DP PHY mode status not complete [0.423203] DP PHY mode status not complete [0.427491] DP PHY mode status not complete [0.431777] DP PHY mode status not complete [0m[INFO ] Informing user on-display of memory training.[0m [0m[DEBUG] FMAP: area COREBOOT found @ 1877000 (7901184 bytes)[0m [1;4m[WARN ] CBFS: 'preram_locales' not found.[0m [7m[ERROR] ux_locales_get_text: preram_locales not found.[0m [0m[DEBUG] FMAP: area RW_ELOG found @ f20000 (16384 bytes)[0m [0m[INFO ] ELOG: NV offset 0xf20000 size 0x4000[0m [0m[INFO ] ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024[0m Change-Id: I1d4795825960bc58f8f7ef494b01aa975f3bc346 Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> --- M src/mainboard/google/brox/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/81931/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/81931?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1d4795825960bc58f8f7ef494b01aa975f3bc346 Gerrit-Change-Number: 81931 Gerrit-PatchSet: 9 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com>

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