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Change subject: mb/qemu-q35/smihandler.c: add support for SMIs on QEMU
......................................................................
Patch Set 3:
(2 comments)
Patchset:
PS2:
> The same comments as in https://review.coreboot.org/c/coreboot/+/78088 apply. […]
Moved the implementation to board directory. This also allowed me to fix SMM for qemu-system-i386.
File src/southbridge/intel/common/smihandler.c:
https://review.coreboot.org/c/coreboot/+/82558/comment/b2270850_f5d1e406?us… :
PS2, Line 216: #if !CONFIG(CPU_QEMU_X86)
: /* Check for Synchronous IO (bit0 == 1) */
: if (!(state->io_misc_info & (1 << 0)))
: continue;
:
: /* Make sure it was a write (bit4 == 0) */
: if (state->io_misc_info & (1 << 4))
: continue;
:
: /* Check for APMC IO port */
: if (((state->io_misc_info >> 16) & 0xff) != APM_CNT)
: continue;
: #endif
> Can this be done in C instead of using the preprocessor?
I've moved the code to board directory and modified significantly, so this no longer applies.
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I'd like you to reexamine a change. Please visit
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Change subject: mb/qemu-q35/smihandler.c: add support for SMIs on QEMU
......................................................................
mb/qemu-q35/smihandler.c: add support for SMIs on QEMU
qemu-system-x86_64 uses AMD64 SMM save state format, despite emulating
Intel chipset. In addition, even though it implements SMI_STS register,
QEMU never sets any bits in it. As there is little emulated hardware
that can be generating SMI, assume that all SMIs come from APM. This
source is used e.g. to disable ACPI (which wasn't working until now on
QEMU) and SMMSTORE.
Tested by invoking SMMSTORE commands from the payload with SMM logging.
Change-Id: I2fc7b74bdc13be8d76bc536283ab5a14fffec45f
Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
---
M src/mainboard/emulation/qemu-q35/Makefile.mk
A src/mainboard/emulation/qemu-q35/smihandler.c
2 files changed, 378 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/82558/4
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Change subject: mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flash
......................................................................
Patch Set 4:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82555/comment/cda0a9cf_dca5e395?us… :
PS3, Line 24: Tested by starting QEMU with firmware passed as '-drive if=pflash',
: '-drive if=pflash,readonly=on' and '-bios'. When started with firmware
: passed through '-device loader', coreboot complains about missing or
: corrupted FMAP, but this is the same behavior as without this change.
> Maybe mention the new debug log that got printed?
Added
https://review.coreboot.org/c/coreboot/+/82555/comment/9dcab72b_fd01e6c3?us… :
PS3, Line 28:
> Is a specific QEMU version needed?
From what I can tell it should work in all publicly available QEMU versions. Original support was added long time ago (~17y), and other than some bug and style fixes, it was mostly unchanged.
File src/mainboard/emulation/qemu-i440fx/rom_media.c:
https://review.coreboot.org/c/coreboot/+/82555/comment/5502a4d1_ad8ffc5e?us… :
PS3, Line 31: to write to the log
> Is that only CBMEM log, or also serial and other log types?
Flash based event log only, the one enabled with CONFIG_ELOG. I've reworded this a bit, hopefully it is a bit clearer now.
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Change subject: payloads: Add leanefi payload
......................................................................
Patch Set 7: Code-Review+2
(1 comment)
Patchset:
PS7:
From the beginning, we've encouraged experiments like this. I understand all the pros and cons, but nobody is requiring this be used; it's an *experimental* *payload*.
I can't see the harm.
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Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82599?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: mb/google/brox/var/brox: Remove mux references from typec port
......................................................................
mb/google/brox/var/brox: Remove mux references from typec port
The Type-C kernel driver no longer programs the AP mux, as of
https://review.coreboot.org/c/coreboot/+/82077. So remove device
references to the TCSS Mux control device from the Type-C port driver.
This eliminates the following kernel error which was observed as a
result of the kernel trying to program muxes it no longer has control
over:
[ 4.618600] cros-ec-typec GOOG0014:00: Failed to get mux info for port: 0, err = -95
[ 4.618608] cros-ec-typec GOOG0014:00: Configure muxes failed, err = -95
BUG=b:341331428
TEST=Run system reboot; configure mux kernel errors no longer seen.
Change-Id: I93e498b12b109c0e649a23a4a49868976a9ee06b
Signed-off-by: Prashant Malani <pmalani(a)chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82599
Reviewed-by: Caveh Jalali <caveh(a)chromium.org>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
---
M src/mainboard/google/brox/variants/brox/overridetree.cb
1 file changed, 2 insertions(+), 4 deletions(-)
Approvals:
build bot (Jenkins): Verified
Caveh Jalali: Looks good to me, approved
diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb
index e9a467a..abb551d 100644
--- a/src/mainboard/google/brox/variants/brox/overridetree.cb
+++ b/src/mainboard/google/brox/variants/brox/overridetree.cb
@@ -138,8 +138,6 @@
end # Integrated Graphics Device
device ref pch_espi on
chip ec/google/chromeec
- use conn0 as mux_conn[0]
- use conn1 as mux_conn[1]
device pnp 0c09.0 on end
end
end
@@ -149,12 +147,12 @@
chip drivers/intel/pmc_mux/conn
use usb2_port1 as usb2_port
use tcss_usb3_port1 as usb3_port
- device generic 0 alias conn0 on end
+ device generic 0 on end
end
chip drivers/intel/pmc_mux/conn
use usb2_port3 as usb2_port
use tcss_usb3_port3 as usb3_port
- device generic 1 alias conn1 on end
+ device generic 1 on end
end
end
end
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Code-Review+2 by Patrick Rudolph, Verified+1 by build bot (Jenkins)
Change subject: mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flash
......................................................................
mb/qemu-{i440fx,q35}/rom_media.c: add code for writable flash
Depending on how firmware image was passed to QEMU, it may behave as:
- ROM - memory mapped reads, writes are ignored (FW image mounted with
'-bios');
- RAM - memory mapped reads and writes (FW image mounted with e.g.
'-device loader');
- flash - memory mapped reads, write and erase possible through
commands. Contrary to physical flash devices erase is not required
before writing, but it also doesn't hurt. Flash may be split into
read-only and read-write parts, like OVMF_CODE.fd and OVMF_VARS.fd.
Combined size of system firmware must not exceed 8 MiB (FW image(s)
mounted with '-drive if=pflash').
This function detects which of the above applies and fills
region_device_ops accordingly.
Tested by starting QEMU with firmware passed as '-drive if=pflash',
'-drive if=pflash,readonly=on' and '-bios'. When started with firmware
passed through '-device loader', coreboot complains about corrupted
FMAP, but this is the same behavior as without this change:
[ERROR] Invalid FMAP at 0x40000
[EMERG] Cannot locate primary CBFS
Writable pflash support was added about 17 years ago, so it should be
supported by all QEMU versions currently in use.
Change-Id: I3ab9f22c6165064a769881d4be5eab13a0a2f519
Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
---
M src/mainboard/emulation/qemu-i440fx/Kconfig
M src/mainboard/emulation/qemu-i440fx/Makefile.mk
A src/mainboard/emulation/qemu-i440fx/rom_media.c
M src/mainboard/emulation/qemu-q35/Kconfig
M src/mainboard/emulation/qemu-q35/Makefile.mk
5 files changed, 204 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/82555/4
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Verified+1 by build bot (Jenkins)
Change subject: mb/qemu-q35/smihandler.c: add support for SMIs on QEMU
......................................................................
mb/qemu-q35/smihandler.c: add support for SMIs on QEMU
qemu-system-x86_64 uses AMD64 SMM save state format, despite emulating
Intel chipset. In addition, even though it implements SMI_STS register,
QEMU never sets any bits in it. As there is little emulated hardware
that can be generating SMI, assume that all SMIs come from APM. This
source is used e.g. to disable ACPI (which wasn't working until now on
QEMU) and SMMSTORE.
Tested by invoking SMMSTORE commands from the payload with SMM logging.
Change-Id: I2fc7b74bdc13be8d76bc536283ab5a14fffec45f
Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com>
---
M src/mainboard/emulation/qemu-q35/Makefile.mk
A src/mainboard/emulation/qemu-q35/smihandler.c
2 files changed, 378 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/82558/3
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Change subject: payloads: Add leanefi payload
......................................................................
Patch Set 7:
(1 comment)
Patchset:
PS7:
I am still unhappy about this, particularly given all the work to make U-Boot function as a better coreboot payload. Should I give up on that? This really is not building bridges between the projects. This whole payload seems to make no sense to me, other than trying to avoid using U-Boot.
A quick look at the source files shows no acknowledgement of U-Boot (BTW that is the correct spelling, bot u-boot). It should be a the top of each file, showing the file it came from.
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