coreboot-gerrit May 2024

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[XS] Change in coreboot[main]: mb/amd/birman/display_card_type.h: add missing include guards
by Felix Held (Code Review) 23 May '24

23 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82607?usp=email ) Change subject: mb/amd/birman/display_card_type.h: add missing include guards ...................................................................... mb/amd/birman/display_card_type.h: add missing include guards Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iaf4478814e672fb8cfae5ffc4fa89c475f5bb0b2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82607 Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/amd/birman/display_card_type.h 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/amd/birman/display_card_type.h b/src/mainboard/amd/birman/display_card_type.h index bb23fd4..f9881c48 100644 --- a/src/mainboard/amd/birman/display_card_type.h +++ b/src/mainboard/amd/birman/display_card_type.h @@ -1,3 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef MAINBOARD_DISPLAY_CARD_TYPE_H +#define MAINBOARD_DISPLAY_CARD_TYPE_H + uint8_t get_ddi1_type(void); + +#endif /* MAINBOARD_DISPLAY_CARD_TYPE_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/82607?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf4478814e672fb8cfae5ffc4fa89c475f5bb0b2 Gerrit-Change-Number: 82607 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/amd/phoenix/chip_opensil.h: add missing include guards
by Felix Held (Code Review) 23 May '24

23 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82606?usp=email ) Change subject: soc/amd/phoenix/chip_opensil.h: add missing include guards ...................................................................... soc/amd/phoenix/chip_opensil.h: add missing include guards Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iba17d44772333ed59e3fdde1443a1862bae8e32f Reviewed-on: https://review.coreboot.org/c/coreboot/+/82606 Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/amd/phoenix/chip_opensil.h 1 file changed, 5 insertions(+), 0 deletions(-) Approvals: Elyes Haouas: Looks good to me, approved Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/phoenix/chip_opensil.h b/src/soc/amd/phoenix/chip_opensil.h index da25a79..37170ad 100644 --- a/src/soc/amd/phoenix/chip_opensil.h +++ b/src/soc/amd/phoenix/chip_opensil.h @@ -1,5 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#ifndef PHOENIX_CHIP_OPENSIL_H +#define PHOENIX_CHIP_OPENSIL_H + #include <types.h> #define DDI_DESCRIPTOR_COUNT 5 @@ -78,3 +81,5 @@ uint8_t PhyP3CpmP4Support; ///< bit[1:0]-Usb0 Port[1:0], bit[3:2]-Usb1 Port[1:0] uint8_t ComboPhyStaticConfig[USBC_COMBO_PHY_COUNT]; ///< 0-Type C, 1- USB only mode, 2- DP only mode, 3- USB + DP }; + +#endif /* PHOENIX_CHIP_OPENSIL_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/82606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iba17d44772333ed59e3fdde1443a1862bae8e32f Gerrit-Change-Number: 82606 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/brya: Add romstage early graphics for nissa
by Subrata Banik (Code Review) 23 May '24

23 May '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/78932?usp=email ) Change subject: mb/google/brya: Add romstage early graphics for nissa ...................................................................... mb/google/brya: Add romstage early graphics for nissa 1) Add all changes needed for early graphics 2) select MAINBOARD_USE_EARLY_LIBGFXINIT for nissa The InnoLux (N156HCN-EBA C7) panel is used for the device tree. BUG=b:296433986 TEST=On-screen text message seen during MRC training on Craask Logs: [NOTE ] MRC: no data in 'RW_MRC_CACHE' [SPEW ] bootmode is set to: 0 [0.171409] DP PHY mode status not complete [0.175509] DP PHY mode status not complete [0.179799] DP PHY mode status not complete [0.184087] DP PHY mode status not complete [0.188376] DP PHY mode status not complete [0.192665] DP PHY mode status not complete [0.196954] DP PHY mode status not complete [0.201243] DP PHY mode status not complete [0.205532] DP PHY mode status not complete [0.209821] DP PHY mode status not complete [0.214110] DP PHY mode status not complete [0.218397] DP PHY mode status not complete [INFO ] Informing user on-display of memory training. Change-Id: I33cfc5d1f8c25c344e598befd21c50a78a65275a Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78932 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/baseboard/nissa/Makefile.mk M src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb A src/mainboard/google/brya/variants/baseboard/nissa/gma-mainboard.ads 4 files changed, 46 insertions(+), 1 deletion(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Dinesh Gehlot: Looks good to me, approved Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index d281a6f..fcc2e63 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -96,6 +96,7 @@ select DRIVERS_AUDIO_SOF select DRIVERS_INTEL_ISH select MAINBOARD_DISABLE_STAGE_CACHE + select MAINBOARD_HAS_EARLY_LIBGFXINIT select MEMORY_SOLDERDOWN select SOC_INTEL_ALDERLAKE_PCH_N select SOC_INTEL_CSE_LITE_COMPRESS_ME_RW diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.mk b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.mk index 3743228..3a66958 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.mk +++ b/src/mainboard/google/brya/variants/baseboard/nissa/Makefile.mk @@ -4,6 +4,7 @@ romstage-y += memory.c romstage-y += gpio.c +romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads ramstage-y += gpio.c ramstage-y += ramstage.c diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb index 55bd9c0..495b571 100644 --- a/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb +++ b/src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb @@ -155,7 +155,37 @@ }" device domain 0 on - device ref igpu on end + # The timing values can be derived from datasheet of display panel + # You can use EDID string to identify the type of display on the board + # use below command to get display info from EDID + # strings /sys/devices/pci0000:00/0000:00:02.0/drm/card0/card0-eDP-1/edid + + # refer to display PRM document (Volume 2b: Command Reference: Registers) + # for more info on display control registers + # https://01.org/linuxgraphics/documentation/hardware-specification-prms + #+-----------------------------+---------------------------------------+-----+ + #| Intel docs | devicetree.cb | eDP | + #+-----------------------------+---------------------------------------+-----+ + #| Power up delay | `gpu_panel_power_up_delay` | T3 | + #+-----------------------------+---------------------------------------+-----+ + #| Power on to backlight on | `gpu_panel_power_backlight_on_delay` | T7 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Down delay | `gpu_panel_power_down_delay` | T10 | + #+-----------------------------+---------------------------------------+-----+ + #| Backlight off to power down | `gpu_panel_power_backlight_off_delay` | T9 | + #+-----------------------------+---------------------------------------+-----+ + #| Power Cycle Delay | `gpu_panel_power_cycle_delay` | T12 | + #+-----------------------------+---------------------------------------+-----+ + device ref igpu on + register "panel_cfg" = "{ + .up_delay_ms = 200, + .down_delay_ms = 50, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 1, + .backlight_off_delay_ms = 200, + .backlight_pwm_hz = 200, + }" + end device ref dtt on end device ref tcss_xhci on end device ref xhci on end diff --git a/src/mainboard/google/brya/variants/baseboard/nissa/gma-mainboard.ads b/src/mainboard/google/brya/variants/baseboard/nissa/gma-mainboard.ads new file mode 100644 index 0000000..3b02f14 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/nissa/gma-mainboard.ads @@ -0,0 +1,13 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + ports : constant Port_List := + (eDP, + others => Disabled); +end GMA.Mainboard; -- To view, visit https://review.coreboot.org/c/coreboot/+/78932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33cfc5d1f8c25c344e598befd21c50a78a65275a Gerrit-Change-Number: 78932 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/brya: Add romstage early graphics for nissa
by Kapil Porwal (Code Review) 23 May '24

23 May '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Haribalaraman Ramasubramanian, Nick Vaccaro, Paul Menzel, Ronak Kanabar, V Sowmya. Kapil Porwal has posted comments on this change by Ronak Kanabar. ( https://review.coreboot.org/c/coreboot/+/78932?usp=email ) Change subject: mb/google/brya: Add romstage early graphics for nissa ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/78932?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33cfc5d1f8c25c344e598befd21c50a78a65275a Gerrit-Change-Number: 78932 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: V Sowmya <v.sowmya(a)intel.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Haribalaraman Ramasubramanian <haribalaraman.r(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Thu, 23 May 2024 13:49:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: device/pci_rom: handle non-remapped VGA_BIOS_ID
by Matt DeVillier (Code Review) 23 May '24

23 May '24

Attention is currently required from: Felix Held, Nico Huber. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/82592?usp=email ) Change subject: device/pci_rom: handle non-remapped VGA_BIOS_ID ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82592?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7cd8e2036250f4ca2239b04cd070bbf0778b13aa Gerrit-Change-Number: 82592 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 23 May 2024 13:47:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Move get_cxl_mode out of soc/util.h
by Lean Sheng Tan (Code Review) 23 May '24

23 May '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/82293?usp=email ) Change subject: soc/intel/xeon_sp: Move get_cxl_mode out of soc/util.h ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82293?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia0302b0d3fd93c49e1d6f64e8159f59d50f33e20 Gerrit-Change-Number: 82293 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 23 May 2024 13:25:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: device/pci_rom: handle non-remapped VGA_BIOS_ID
by Felix Held (Code Review) 23 May '24

23 May '24

Attention is currently required from: Matt DeVillier, Nico Huber. Hello Matt DeVillier, Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82592?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: device/pci_rom: handle non-remapped VGA_BIOS_ID ...................................................................... device/pci_rom: handle non-remapped VGA_BIOS_ID While the SoC-level defaults for VGA_BIOS_ID are the expected correctly remapped PCI VID/PID of the GPU which matches the PCI VID/DID inside the VBIOS file, some mainboards override the VGA_BIOS_ID setting to the non-remapped PCI ID. This resulted in coreboot not finding the VBIOS file after commit 42f0396a1028 ("device/pci_rom: rework PCI ID remapping in pci_rom_probe"). The proper solution would be to not override this SoC-level config in neither the mainboard code nor some external config file. This however requires adding/using some mechanism to tell SeaBIOS which VBIOS image to use for the GPU device. Once this is implemented, the SoC default for VGA_BIOS_ID shouldn't be overridden any more and this patch can be reverted again. This sort-of reverts parts of commit 42f0396a1028 ("device/pci_rom: rework PCI ID remapping in pci_rom_probe"), but it still tries to find the VBIOS image with the expected remapped PCI ID and only adds trying the non-remapped PCI ID as a fallback when the file with the remapped PCI ID doesn't exist and prints a notice in that case. Before the patch referenced above, using the correct remapped PCI VID/DID resulted in a warning about the CBFS file with the non-remapped name not being found, but first checking the remapped version solves that problem. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I7cd8e2036250f4ca2239b04cd070bbf0778b13aa --- M src/device/pci_rom.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/82592/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/82592?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7cd8e2036250f4ca2239b04cd070bbf0778b13aa Gerrit-Change-Number: 82592 Gerrit-PatchSet: 7 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER
by Shuo Liu (Code Review) 23 May '24

23 May '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Tim Chu, Ziang Wang. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/81443?usp=email ) Change subject: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81443/comment/81044333_57109c64?us… : PS6, Line 9: Add a new proximity type to represent the sub-NUMA : cluster (SNC). : : This patch doesn't actually enable SNC. To fully enable : SNC, SoC codes need to override soc_get_cluster_count(), : soc_set_cpu_node_id() and memory_to_pd(), and call : soc_set_cpu_node_id() in its per-CPU init routine. > Please re-flow for 72 characters per line. Done File src/soc/intel/xeon_sp/spr/chip.c: https://review.coreboot.org/c/coreboot/+/81443/comment/58f6f7eb_c8e27bb3?us… : PS6, Line 178: if (pds.pds[i].pd_type != PD_TYPE_GENERIC_INITIATOR) > Excuse my ignorance, but could these hunks be explained in the commit message? Sure, added, With SNC, there are 3 types of proximity domains, PD_TYPE_PROCESSOR, PD_TYPE_GENERIC_INITIATOR and PD_TYPE_CLUSTER. proximity domain type checks in Xeon-SP codes are updated to correctly handle the adding of the new type. -- To view, visit https://review.coreboot.org/c/coreboot/+/81443?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32558983780f302ff4893901540a90baebf47add Gerrit-Change-Number: 81443 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Thu, 23 May 2024 13:06:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER
by Shuo Liu (Code Review) 23 May '24

23 May '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu, Ziang Wang. Hello Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, Ziang Wang, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81443?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+1 by Lean Sheng Tan, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add PD_TYPE_CLUSTER ...................................................................... soc/intel/xeon_sp: Add PD_TYPE_CLUSTER Add a new proximity type to represent the sub-NUMA cluster (SNC). This patch adds necessary Xeon-SP common code level support for SNC support. When SNC on, each SNC cluster will have a proximity domain. DIMMs and CPU cores are attached to SNC proximity domains instead of the processor proximity domains. With SNC, there are 3 types of proximity domains, PD_TYPE_PROCESSOR, PD_TYPE_GENERIC_INITIATOR and PD_TYPE_CLUSTER. proximity domain type checks in Xeon-SP codes are updated to correctly handle the adding of the new type. This patch doesn't actually enable SNC. To fully enable SNC, SoC codes need to override soc_get_cluster_count(), soc_set_cpu_node_ id() and memory_to_pd(), and call soc_set_cpu_node_id() in its per-CPU init routine. Change-Id: I32558983780f302ff4893901540a90baebf47add Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Co-authored-by: Ziang Wang <ziang.wang(a)intel.com> Co-authored-by: Gang Chen <gang.c.chen(a)intel.com> --- M src/soc/intel/xeon_sp/include/soc/numa.h M src/soc/intel/xeon_sp/numa.c M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/uncore.c 5 files changed, 71 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/81443/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/81443?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I32558983780f302ff4893901540a90baebf47add Gerrit-Change-Number: 81443 Gerrit-PatchSet: 7 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Ziang Wang <ziang.wang(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[L] Change in coreboot[main]: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)
by Felix Held (Code Review) 23 May '24

23 May '24

Attention is currently required from: Angel Pons, Federico Amedeo Izzo, Felix Singer. Felix Held has posted comments on this change by Federico Amedeo Izzo. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email ) Change subject: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1) ...................................................................... Patch Set 14: (1 comment) File src/mainboard/aoostar/wtr_r1/gpio.h: PS14: i wonder if the more high level gpio configuration macros could be used here instead of _PAD_CFG_STRUCT. https://review.coreboot.org/c/coreboot/+/81595/13/src/mainboard/cwwk/adl/gp… for example matches what i've seen being used in most mainboards using Intel SoCs. if you change to using the more high level macros, you can use 'make BUILD_TIMELESS=1' in the build before and after changing the macros and compare the resulting files; if they are identical, you can be sure the new macros will evaluate to the same raw values to not have that cause any regression. if it's not possible to get the same raw values using the more high level macros, feel free to just ack this one to not block this patch and possibly look into that later -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 14 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Brandon Weeks <bweeks(a)google.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Thu, 23 May 2024 12:53:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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