coreboot-gerrit May 2024

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[XS] Change in coreboot[main]: Revert "mb/google/brox: Update verb table to fix headset detection"
by Paul Menzel (Code Review) 27 May '24

27 May '24

Attention is currently required from: Terry Cheong. Paul Menzel has posted comments on this change by Terry Cheong. ( https://review.coreboot.org/c/coreboot/+/82273?usp=email ) Change subject: Revert "mb/google/brox: Update verb table to fix headset detection" ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82273/comment/868e59e1_efc2604d?us… : PS2, Line 11: on some devices on : brox > From other teams we can see problems coming up on other SKUs as well. […] How was the original commit tested then? @Poornima? -- To view, visit https://review.coreboot.org/c/coreboot/+/82273?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d8c092de6166b2c62f5ecc3deaf4960128e6106 Gerrit-Change-Number: 82273 Gerrit-PatchSet: 4 Gerrit-Owner: Terry Cheong <htcheong(a)chromium.org> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vamshi Krishna Gopal <vamshi.krishna.gopal(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Poornima Tom <poornima.tom(a)intel.com> Gerrit-CC: Terry Cheong <htcheong(a)google.com> Gerrit-Attention: Terry Cheong <htcheong(a)chromium.org> Gerrit-Comment-Date: Mon, 27 May 2024 12:04:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Terry Cheong <htcheong(a)google.com>

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[S] Change in coreboot[main]: Documentation/index.md: Add coreboot's blob policy
by Paul Menzel (Code Review) 27 May '24

27 May '24

Attention is currently required from: David Hendricks, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Patrick Georgi, Subrata Banik, Werner Zeh. Paul Menzel has posted comments on this change by Werner Zeh. ( https://review.coreboot.org/c/coreboot/+/82086?usp=email ) Change subject: Documentation/index.md: Add coreboot's blob policy ...................................................................... Patch Set 6: (1 comment) File Documentation/index.md: https://review.coreboot.org/c/coreboot/+/82086/comment/53dad6e8_165feeb8?us… : PS3, Line 179: > > Where should that discussion take place? […] It’d be great if you could word it this way. The decision should be at least announced on the mailing list though. -- To view, visit https://review.coreboot.org/c/coreboot/+/82086?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20bc0b345c129ecd59aa1190647d89f6d4e07d46 Gerrit-Change-Number: 82086 Gerrit-PatchSet: 6 Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Patrick Georgi Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Georgi Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 27 May 2024 12:03:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com>

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[XL] Change in coreboot[main]: soc/intel/xeon-sp: Hook up public FSP bin and headers
by Fabian Meyer (Code Review) 27 May '24

27 May '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Singer, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Srinidhi N Kaushik, Tim Chu. Fabian Meyer has posted comments on this change by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/80360?usp=email ) Change subject: soc/intel/xeon-sp: Hook up public FSP bin and headers ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Thanks for looking into it! Thanks for working on this. Just out of curiosity, what part needs clarification? This patch seems to work great in my testing with CB:82203 (which is currently blocked on this being merged). -- To view, visit https://review.coreboot.org/c/coreboot/+/80360?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I778d3535c273dff653330518653bdefcb45e66f4 Gerrit-Change-Number: 80360 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Srinidhi N Kaushik <kaushiksrinidhin(a)gmail.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-CC: Fabian Meyer <fabian(a)meyfa.net> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Srinidhi N Kaushik <kaushiksrinidhin(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 27 May 2024 12:00:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[L] Change in coreboot[main]: mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM
by Fabian Meyer (Code Review) 27 May '24

27 May '24

Attention is currently required from: Angel Pons, Felix Singer, Nico Huber, Paul Menzel. Fabian Meyer has posted comments on this change by Fabian Meyer. ( https://review.coreboot.org/c/coreboot/+/82203?usp=email ) Change subject: mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM ...................................................................... Patch Set 9: (5 comments) Patchset: PS9: > Would you be interested in listed as a maintainer for this mainboard? If so, please add an entry to […] Due to my contract running out, I will not have access to this board in the future, so there likely wouldn't be a point to that. PS9: > I guess we can just merge this without the FSP-header update. One would […] No, this does not work. 1) Without the correct headers, the board cannot boot. 2) Without the additional changes in CB:80360 (i.e., just setting the include path in menuconfig), coreboot does not compile. File src/mainboard/asrock/spc741d8/Kconfig: PS9: > Missing SPDX license identifier Done https://review.coreboot.org/c/coreboot/+/82203/comment/91734fad_097c9e24?us… : PS9, Line 37: config DEBUG_SMI : d > Is it needed to enable that by default? No, removed. Note however that this option is also present in every other EagleStream board's Kconfig, likely not needed there as well. File src/mainboard/asrock/spc741d8/Kconfig.name: PS9: > Missing SPDX license identifier Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82203?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84b170669873f1a168ea2b7e3be1d6071e811fa5 Gerrit-Change-Number: 82203 Gerrit-PatchSet: 9 Gerrit-Owner: Fabian Meyer <fabian(a)meyfa.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Mon, 27 May 2024 11:51:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[L] Change in coreboot[main]: mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM
by Fabian Meyer (Code Review) 27 May '24

27 May '24

Attention is currently required from: Angel Pons, Fabian Meyer, Nico Huber, Paul Menzel. Hello Nico Huber, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82203?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Verified+1 by build bot (Jenkins) Change subject: mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM ...................................................................... mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM SPC741D8-2L2T/BCM is a Xeon SP 4th/5th gen (Eagle Stream) platform with: - 1 SPR socket, 8 DDR5 DIMMs each - 4x PCIe 5.0 / CXL 1.1 x16 slots - 2x MCIO PCIe 5.0 x8 and 1 MCIO on PCH - 2x M.2 PCH PCIe slots - 2x 10 Gbit/s NIC and 2x 1 Gbit/s i210 NIC It has an AST2600 BMC for remote management and most SuperIO functions such as serial and an additional Nuvoton NCT6796D-E for others. Working: - Booting to Linux 6.8 using a mainline EDK2 payload - All CPU cores of a 4th-gen Xeon SP are available at full speed - All 8 memory DIMMs (KSM48R40BS8KMM-16HMR) - All 4 PCIe slots - On-board USB ports - Video output via the AST2600 (on-board VGA) - M.2 devices Untested: - 5th-gen Xeon SP processor - TPM header Not working: - Serial port I/O, related to the AST2600 SuperIO not being located at the default address of 0x2E (it uses 0x4E instead). - PC speaker (buzzer), for the same reason. - M.2 SSDs only use PCIe Gen 2 speeds, however, they should be capable of Gen 3 speeds, which can be observed using the vendor firmware. Change-Id: I84b170669873f1a168ea2b7e3be1d6071e811fa5 Signed-off-by: Fabian Meyer <fabian.meyer(a)student.kit.edu> Co-authored-by: Yussuf Khalil <yussuf.khalil(a)kit.edu> --- A configs/builder/config.asrock.spc741d8 A src/mainboard/asrock/spc741d8/Kconfig A src/mainboard/asrock/spc741d8/Kconfig.name A src/mainboard/asrock/spc741d8/Makefile.mk A src/mainboard/asrock/spc741d8/acpi/platform.asl A src/mainboard/asrock/spc741d8/board.fmd A src/mainboard/asrock/spc741d8/board_info.txt A src/mainboard/asrock/spc741d8/bootblock.c A src/mainboard/asrock/spc741d8/devicetree.cb A src/mainboard/asrock/spc741d8/dsdt.asl A src/mainboard/asrock/spc741d8/include/mainboard_iio.h A src/mainboard/asrock/spc741d8/include/mainboard_ras.h A src/mainboard/asrock/spc741d8/ramstage.c A src/mainboard/asrock/spc741d8/romstage.c A src/mainboard/asrock/spc741d8/util.c 15 files changed, 437 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/82203/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/82203?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84b170669873f1a168ea2b7e3be1d6071e811fa5 Gerrit-Change-Number: 82203 Gerrit-PatchSet: 10 Gerrit-Owner: Fabian Meyer <fabian(a)meyfa.net> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fabian Meyer <fabian(a)meyfa.net> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[XL] Change in coreboot[main]: ec/dasharo/ec: add Dasharo features
by Michał Kopeć (Code Review) 27 May '24

27 May '24

Michał Kopeć has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/82672?usp=email ) Change subject: ec/dasharo/ec: add Dasharo features ...................................................................... ec/dasharo/ec: add Dasharo features - EC firmware update in ramstage - Setting battery thresholds - PEP hooks for S0ix - Remove unused keyboard backlight, OLED, FCMD Change-Id: I5600487afcb0a4b261d9ff85e3b2c73535a23f3d Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/ec/dasharo/ec/Kconfig M src/ec/dasharo/ec/Makefile.mk A src/ec/dasharo/ec/acpi.h A src/ec/dasharo/ec/acpi/dasharo.asl M src/ec/dasharo/ec/acpi/ec.asl M src/ec/dasharo/ec/acpi/ec_ram.asl M src/ec/dasharo/ec/acpi/lid.asl D src/ec/dasharo/ec/acpi/s76.asl A src/ec/dasharo/ec/buttons.c A src/ec/dasharo/ec/commands.h M src/ec/dasharo/ec/dasharo_ec.c M src/ec/dasharo/ec/dasharo_ec.h D src/ec/dasharo/ec/smbios.c 13 files changed, 899 insertions(+), 307 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/82672/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5600487afcb0a4b261d9ff85e3b2c73535a23f3d Gerrit-Change-Number: 82672 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: mb/novacustom: add V5x0TU board (Meteor Lake)
by Michał Kopeć (Code Review) 27 May '24

27 May '24

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82673?usp=email ) Change subject: mb/novacustom: add V5x0TU board (Meteor Lake) ...................................................................... mb/novacustom: add V5x0TU board (Meteor Lake) NovaCustom (Clevo) V5x0TU are two boards with Intel Core Ultra (Meteor Lake) series processors. Two variants (V540TU and V560TU) are supported. Their EC firmware is different due to keyboard layout changes. On coreboot's side, the only difference are SMBIOS strings. Working: - DDR5 SODIMM in slot RAM2 - M.2 2280 PCIe slots - Thunderbolt, USB ports - Onboard audio - Video outputs in OS and firmware - I2C touchpad, webcam, SD Card reader - S0ix - Booting Ubuntu 24.04 with edk2 UefiPayload - Vboot, TPM measured boot Not working: - DDR5 SODIMM in slot RAM1 - PS/2 keyboard in edk2 Change-Id: I82c73ddb1e76a9baf9b97e13124aa249ae1c2771 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- A src/mainboard/novacustom/Kconfig A src/mainboard/novacustom/Kconfig.name A src/mainboard/novacustom/mtl-h/Kconfig A src/mainboard/novacustom/mtl-h/Kconfig.name A src/mainboard/novacustom/mtl-h/Makefile.mk A src/mainboard/novacustom/mtl-h/acpi/backlight.asl A src/mainboard/novacustom/mtl-h/acpi/mainboard.asl A src/mainboard/novacustom/mtl-h/board_info.txt A src/mainboard/novacustom/mtl-h/bootblock.c A src/mainboard/novacustom/mtl-h/cmos.default A src/mainboard/novacustom/mtl-h/cmos.layout A src/mainboard/novacustom/mtl-h/data.vbt A src/mainboard/novacustom/mtl-h/devicetree.cb A src/mainboard/novacustom/mtl-h/dsdt.asl A src/mainboard/novacustom/mtl-h/fadt.c A src/mainboard/novacustom/mtl-h/gpio.c A src/mainboard/novacustom/mtl-h/gpio_early.c A src/mainboard/novacustom/mtl-h/hda_verb.c A src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h A src/mainboard/novacustom/mtl-h/ramstage.c A src/mainboard/novacustom/mtl-h/romstage.c A src/mainboard/novacustom/mtl-h/vboot-rwab.fmd 22 files changed, 1,402 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/82673/1 diff --git a/src/mainboard/novacustom/Kconfig b/src/mainboard/novacustom/Kconfig new file mode 100644 index 0000000..e159480 --- /dev/null +++ b/src/mainboard/novacustom/Kconfig @@ -0,0 +1,17 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_NOVACUSTOM + +choice + prompt "Mainboard model" + +source "src/mainboard/novacustom/*/Kconfig.name" + +endchoice + +source "src/mainboard/novacustom/*/Kconfig" + +config MAINBOARD_VENDOR + default "NovaCustom" + +endif # VENDOR_NOVACUSTOM diff --git a/src/mainboard/novacustom/Kconfig.name b/src/mainboard/novacustom/Kconfig.name new file mode 100644 index 0000000..242b3bb --- /dev/null +++ b/src/mainboard/novacustom/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_NOVACUSTOM + bool "NovaCustom" diff --git a/src/mainboard/novacustom/mtl-h/Kconfig b/src/mainboard/novacustom/mtl-h/Kconfig new file mode 100644 index 0000000..e4a40ca --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Kconfig @@ -0,0 +1,106 @@ +config BOARD_NOVACUSTOM_MTLH_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_GFX_GENERIC + select DRIVERS_I2C_HID + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER + select DRIVERS_WIFI_GENERIC + select EC_DASHARO_EC + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + select NO_UART_ON_SUPERIO + select PMC_IPC_ACPI_INTERFACE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_CRASHLOG + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_METEORLAKE_U_H + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + select TPM_RDRESP_NEED_DELAY + +config BOARD_NOVACUSTOM_V5X0TU_BASE + bool + select BOARD_NOVACUSTOM_MTLH_COMMON + select MAINBOARD_USES_IFD_GBE_REGION + +config BOARD_NOVACUSTOM_V540TU + bool + select BOARD_NOVACUSTOM_V5X0TU_BASE + +config BOARD_NOVACUSTOM_V560TU + bool + select BOARD_NOVACUSTOM_V5X0TU_BASE + +if BOARD_NOVACUSTOM_MTLH_COMMON + +config MAINBOARD_DIR + default "novacustom/mtl-h" + +config MAINBOARD_PART_NUMBER + default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE + +config MAINBOARD_SMBIOS_MANUFACTURER + default "Notebook" + +config MAINBOARD_VERSION + default "V540TU" if BOARD_NOVACUSTOM_V540TU + default "V560TU" if BOARD_NOVACUSTOM_V560TU + +config MAINBOARD_FAMILY + string + default "Not Applicable" # Match Insyde firmware, for Windows Update + +config CBFS_SIZE + default 0xA00000 + +config CONSOLE_POST + default y + +config DIMM_SPD_SIZE + default 512 + +config POST_DEVICE + default n + +config USE_PM_ACPI_TIMER + default n + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + select VBOOT_MOCK_SECDATA + select VBOOT_NO_BOARD_SUPPORT + +config VBOOT_SLOTS_RW_AB + default y if VBOOT + +config VBOOT_VBNV_OFFSET + default 0x28 + +config TPM_PIRQ + default 0x61 # GPP_E01 + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT && VBOOT_SLOTS_RW_AB + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config EC_DASHARO_EC_FLASH_SIZE + default 0x40000 + +endif diff --git a/src/mainboard/novacustom/mtl-h/Kconfig.name b/src/mainboard/novacustom/mtl-h/Kconfig.name new file mode 100644 index 0000000..ff079a0 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Kconfig.name @@ -0,0 +1,7 @@ +comment "Meteor Lake H" + +config BOARD_NOVACUSTOM_V540TU + bool "V540TU (14\")" + +config BOARD_NOVACUSTOM_V560TU + bool "V560TU (16\")" diff --git a/src/mainboard/novacustom/mtl-h/Makefile.mk b/src/mainboard/novacustom/mtl-h/Makefile.mk new file mode 100644 index 0000000..9a35f5a --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Makefile.mk @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += gpio_early.c + +romstage-y += romstage.c + +ramstage-y += ramstage.c +ramstage-y += hda_verb.c +ramstage-y += gpio.c + +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c diff --git a/src/mainboard/novacustom/mtl-h/acpi/backlight.asl b/src/mainboard/novacustom/mtl-h/acpi/backlight.asl new file mode 100644 index 0000000..01fa83e --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/backlight.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <drivers/intel/gma/acpi/gma.asl> + +Scope (GFX0) +{ + Name (BRIG, Package (23) { + 40, /* default AC */ + 40, /* default Battery */ + 0, + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl b/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl new file mode 100644 index 0000000..ec22903 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x6E +#define EC_GPE_SWI 0x6B +#include <ec/dasharo/ec/acpi/ec.asl> + +Scope (\_SB) { + Scope (PCI0) { + #include "backlight.asl" + } +} diff --git a/src/mainboard/novacustom/mtl-h/board_info.txt b/src/mainboard/novacustom/mtl-h/board_info.txt new file mode 100644 index 0000000..4b3db96 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: NovaCustom +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/novacustom/mtl-h/bootblock.c b/src/mainboard/novacustom/mtl-h/bootblock.c new file mode 100644 index 0000000..8d06adc --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <mainboard/gpio.h> + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); +} diff --git a/src/mainboard/novacustom/mtl-h/cmos.default b/src/mainboard/novacustom/mtl-h/cmos.default new file mode 100644 index 0000000..62715bc --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/cmos.default @@ -0,0 +1,3 @@ +boot_option=Fallback +debug_level=Debug +me_state=Enable diff --git a/src/mainboard/novacustom/mtl-h/cmos.layout b/src/mainboard/novacustom/mtl-h/cmos.layout new file mode 100644 index 0000000..66b8665 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/cmos.layout @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 304 r 0 reserved_memory + +# coreboot config options: ramtop +304 80 h 0 ramtop + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter + +# Vboot non-volatile data +432 128 r 0 vbnv + +984 16 h 0 check_sum + +enumerations + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 431 984 diff --git a/src/mainboard/novacustom/mtl-h/data.vbt b/src/mainboard/novacustom/mtl-h/data.vbt new file mode 100644 index 0000000..59c3c78 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/data.vbt Binary files differ diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb new file mode 100644 index 0000000..6976776 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/devicetree.cb @@ -0,0 +1,316 @@ +chip soc/intel/meteorlake + # Common SoC configuration + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable S0ix / Modern Standby + register "s0ix_enable" = "1" + + # SaGv configuration + register "sagv" = "SAGV_ENABLED" + + # Disable C1 and Package C-state auto-demotion + register "disable_c1_state_auto_demotion" = "1" + register "disable_package_c_state_demotion" = "1" + + # Enable Energy Reporting + register "pch_pm_energy_report_enable" = "1" + + # Thermal + register "tcc_offset" = "10" # TCC of 100C + + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC_SKIP), /* USB Type-A Port 1 (Left) */ + [1] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 1 (Non-TBT) */ + [2] = USB2_PORT_MID(OC_SKIP), /* USB Type-A Port 2 (Right) */ + [5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 2 (TBT) */ + [6] = USB2_PORT_LONG(OC_SKIP), /* Integrated Camera */ + [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth on M.2 2230 */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 1 (Left) */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 2 (Right) */ + }" + + register "tcss_ports" = "{ + [0] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 1 (TBT) */ + [1] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 2 (Non-TBT) */ + }" + + device cpu_cluster 0 on end + device domain 0 on + subsystemid 0x1558 0xa743 inherit + device ref system_agent on end + device ref igpu on + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, /* eDP */ + [DDI_PORT_2] = DDI_ENABLE_DDC | DDI_ENABLE_HPD, /* HDMI 2.1 */ + }" + chip drivers/gfx/generic + register "device_count" = "3" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB unused + register "device[1].name" = ""DD01"" + # TCP0 for Thunderbolt 4 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 1))" + # TCP1 unused + register "device[3].name" = ""DD03"" + # TCP2 for HDMI 2.1 + register "device[4].name" = ""DD04"" + # TCP3 unused + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end + device ref dtt on end + device ref pcie_rp10 on # M.2 2280 #2 + register "pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D01)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + register "srcclk_pin" = "8" + device generic 0 on end + end + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" + end + device ref pcie_rp11 on # M.2 2280 #1 + register "pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 7, + .clk_req = 7, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_DETECT, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D05)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)" + register "srcclk_pin" = "7" + device generic 0 on end + end + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + device ref tbt_pcie_rp0 on end + device ref gna on end + device ref crashlog on end + device ref vpu on end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 1 (TBT)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + end + device ref ioe_shared_sram on end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Left"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Right"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 3))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 1 (TBT)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Left"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Right"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 3))" + device ref usb3_port2 on end + end + end + end + end + device ref pmc_shared_sram on end + device ref cnvi_wifi on + register "cnvi_wifi_core" = "true" + register "cnvi_bt_core" = "true" + register "cnvi_bt_audio_offload" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c0 on # Touchpad + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c1 on # USB-PD EEPROM + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref i2c3 on # Pantone ROM + register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci" + end + device ref pcie_rp5 on # GLAN + register "pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_CLK_SRC_UNUSED, + }" + register "pcie_clk_config_flag[2]" = "PCIE_CLK_LAN" + end + device ref pcie_rp6 on # SD Card Reader + register "pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/generic/bayhub_lv2 + register "enable_power_saving" = "1" + device pci 00.0 on end + end + end + device ref pcie_rp8 on # M.2 2230 + register "pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_09" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device ref uart0 on # BIOS Debug Port + register "serial_io_uart_mode[PchSerialIoIndexUART0]" = "PchSerialIoPci" + end + device ref soc_espi on + register "gen1_dec" = "0x00040069" # EC PM channel + register "gen2_dec" = "0x00fc0e01" # AP/EC command + register "gen3_dec" = "0x00fc0f01" # AP/EC debug + chip drivers/pc80/tpm # SLB 9672 TPM 2.0 + device pnp 0c31.0 on end + end + end + device ref pmc hidden + register "pmc_gpe0_dw0" = "PMC_GPP_V" + register "pmc_gpe0_dw1" = "PMC_GPP_B" + register "pmc_gpe0_dw2" = "PMC_GPP_S" + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # USB Type-C Port 1 (TBT) + use usb2_port6 as usb2_port + use tcss_usb3_port0 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + # USB Type-C Port 2 (Non-TBT) + use usb2_port2 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref hda on + subsystemid 0x1558 0xa763 + #register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_codec_enable" = "1" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + + end + device ref smbus on end + device ref fast_spi on end + device ref gbe on end + end +end diff --git a/src/mainboard/novacustom/mtl-h/dsdt.asl b/src/mainboard/novacustom/mtl-h/dsdt.asl new file mode 100644 index 0000000..06e7263 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/dsdt.asl @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/meteorlake/acpi/southbridge.asl> + #include <soc/intel/meteorlake/acpi/tcss.asl> + } + + /* Chipset specific sleep states */ + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Scope (\_SB.PCI0.LPCB) + { + #include <drivers/pc80/pc/ps2_controller.asl> + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/novacustom/mtl-h/fadt.c b/src/mainboard/novacustom/mtl-h/fadt.c new file mode 100644 index 0000000..f983717 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/fadt.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_MOBILE; +} diff --git a/src/mainboard/novacustom/mtl-h/gpio.c b/src/mainboard/novacustom/mtl-h/gpio.c new file mode 100644 index 0000000..f52b044 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/gpio.c @@ -0,0 +1,574 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group V ------- */ + + /* GPP_V00 - BATLOW# */ + PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1), + /* GPP_V01 - ACPRESENT */ + PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1), + /* GPP_V02 - SOC_WAKE# */ + PAD_CFG_NF(GPP_V02, NATIVE, DEEP, NF1), + /* GPP_V03 - PWRBTN# */ + PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), + /* GPP_V04 - SLP_S3# */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), + /* GPP_V05 - SLP_S4# */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), + /* GPP_V06 - SLP_A# */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), + /* GPP_V07 - GPIO */ + PAD_CFG_GPO(GPP_V07, 0, DEEP), + /* GPP_V08 - SUSCLK */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), + /* GPP_V09 - SLP_WLAN# */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), + /* GPP_V10 - SLP_S5# */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), + /* GPP_V11 - LANPHYPC */ + PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), + /* GPP_V12 - SLP_LAN# */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), + /* GPP_V13 - GPIO */ + PAD_CFG_GPO(GPP_V13, 0, DEEP), + /* GPP_V14 - WAKE# */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), + /* GPP_V15 - GPIO */ + PAD_CFG_GPO(GPP_V15, 0, DEEP), + /* GPP_V16 - GPIO */ + PAD_CFG_GPO(GPP_V16, 0, DEEP), + /* GPP_V17 - GPIO */ + PAD_CFG_GPO(GPP_V17, 0, DEEP), + /* GPP_V18 - GPIO */ + PAD_CFG_GPO(GPP_V18, 0, DEEP), + /* GPP_V19 - n/a */ + PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1), + /* GPP_V20 - n/a */ + PAD_CFG_NF(GPP_V20, NONE, DEEP, NF1), + /* GPP_V21 - n/a */ + PAD_CFG_NF(GPP_V21, NONE, DEEP, NF1), + /* GPP_V22 - GPIO */ + PAD_CFG_GPO(GPP_V22, 0, DEEP), + /* GPP_V23 - GPIO */ + PAD_CFG_GPO(GPP_V23, 0, DEEP), + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C00 - SMBCLK */ + PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1), + /* GPP_C01 - SMBDATA */ + PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1), + /* GPP_C02 - GPIO */ + PAD_CFG_GPO(GPP_C02, 0, DEEP), + /* GPP_C03 - SML0CLK */ + PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), + /* GPP_C04 - SML0DATA */ + PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), + /* GPP_C05 - GPIO */ + PAD_CFG_GPO(GPP_C05, 0, DEEP), + /* GPP_C06 - SML1CLK */ + PAD_CFG_NF(GPP_C06, NONE, RSMRST, NF1), + /* GPP_C07 - SML1DATA */ + PAD_CFG_NF(GPP_C07, NONE, RSMRST, NF1), + /* GPP_C08 - GPIO */ + PAD_CFG_GPO(GPP_C08, 0, DEEP), + /* GPP_C09 - GPIO */ + PAD_CFG_GPO(GPP_C09, 0, DEEP), + /* GPP_C10 - GPIO */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + /* GPP_C11 - SRCCLKREQ2# */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), + /* GPP_C12 - SRCCLKREQ3# */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* GPP_C13 - GPIO */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), + /* GPP_C14 - GPIO */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + /* GPP_C15 - GPIO */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), + /* GPP_C16 - TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* GPP_C17 - TBT_LSX0_RXD */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* GPP_C18 - GPIO */ + PAD_CFG_GPO(GPP_C18, 0, DEEP), + /* GPP_C19 - GPIO */ + PAD_CFG_GPO(GPP_C19, 0, DEEP), + /* GPP_C20 - DDP2_CTRLCLK */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), + /* GPP_C21 - DDP2_CTRLDATA */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), + /* GPP_C22 - GPIO */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* GPP_C23 - GPIO */ + PAD_CFG_GPO(GPP_C23, 0, DEEP), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A00 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), + /* GPP_A01 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), + /* GPP_A02 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), + /* GPP_A03 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), + /* GPP_A04 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), + /* GPP_A05 - ESPI_CLK */ + PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), + /* GPP_A06 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), + /* GPP_A07 - GPIO */ + PAD_CFG_GPO(GPP_A07, 0, DEEP), + /* GPP_A08 - GPIO */ + PAD_CFG_GPO(GPP_A08, 0, DEEP), + /* GPP_A09 - GPIO */ + PAD_CFG_GPO(GPP_A09, 0, DEEP), + /* GPP_A10 - GPIO */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + /* GPP_A11 - GPIO */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), + /* GPP_A12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI), + /* GPP_A13 - GPIO */ + PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), + /* GPP_A14 - GPIO */ + PAD_CFG_GPO(GPP_A14, 0, DEEP), + /* GPP_A15 - GPIO */ + PAD_CFG_GPO(GPP_A15, 0, DEEP), + /* GPP_A16 - RSVD */ + PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), + /* GPP_A17 - GPIO */ + PAD_CFG_GPO(GPP_A17, 0, DEEP), + /* GPP_A18 - GPIO */ + PAD_CFG_GPO(GPP_A18, 0, DEEP), + /* GPP_A19 - GPIO */ + PAD_CFG_GPO(GPP_A19, 0, DEEP), + /* GPP_A20 - GPIO */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + /* GPP_A21 - PMCALERT# */ + PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), + /* GPP_A22 - GPIO */ + PAD_NC(GPP_A22, NATIVE), + /* GPP_A23 - GPIO */ + PAD_NC(GPP_A23, NATIVE), + /* GPP_ESPI_CLK_LPBK - n/a */ + PAD_CFG_NF(GPP_ESPI_CLK_LPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E00 - GPIO */ + PAD_CFG_GPO(GPP_E00, 0, DEEP), + /* GPP_E01 - GPIO */ + PAD_CFG_GPI_APIC(GPP_E01, UP_20K, DEEP, LEVEL, NONE), + /* GPP_E02 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E02, NONE, DEEP, OFF, ACPI), + /* GPP_E03 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E03, NONE, DEEP, OFF, ACPI), + /* GPP_E04 - GPIO */ + PAD_CFG_GPO(GPP_E04, 0, DEEP), + /* GPP_E05 - GPIO */ + PAD_CFG_GPO(GPP_E05, 0, DEEP), + /* GPP_E06 - GPIO */ + PAD_CFG_GPO(GPP_E06, 0, DEEP), + /* GPP_E07 - GPIO */ + PAD_CFG_GPO(GPP_E07, 0, DEEP), + /* GPP_E08 - GPIO */ + PAD_CFG_GPO(GPP_E08, 0, DEEP), + /* GPP_E09 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E09, NONE, DEEP, OFF, ACPI), + /* GPP_E10 - GPIO */ + PAD_CFG_GPO(GPP_E10, 0, DEEP), + /* GPP_E11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), + /* GPP_E12 - GPIO */ + PAD_CFG_GPO(GPP_E12, 0, DEEP), + /* GPP_E13 - GPIO */ + PAD_CFG_GPO(GPP_E13, 0, DEEP), + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* GPP_E15 - GPIO */ + PAD_CFG_GPO(GPP_E15, 0, DEEP), + /* GPP_E16 - VRALERT# */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), + /* GPP_E17 - GPIO */ + PAD_CFG_GPO(GPP_E17, 0, DEEP), + /* GPP_E18 - GPIO */ + PAD_CFG_GPO(GPP_E18, 0, DEEP), + /* GPP_E19 - GPIO */ + PAD_CFG_GPO(GPP_E19, 0, DEEP), + /* GPP_E20 - GPIO */ + PAD_CFG_GPO(GPP_E20, 0, DEEP), + /* GPP_E21 - GPIO */ + PAD_CFG_GPO(GPP_E21, 0, DEEP), + /* GPP_E22 - GPIO */ + PAD_CFG_GPO(GPP_E22, 0, DEEP), + /* GPP_E23 - GPIO */ + PAD_NC(GPP_E23, NONE), + /* GPP_THC0_GSPI_CLK_LPBK - GPIO */ + PAD_NC(GPP_THC0_GSPI_CLK_LPBK, NONE), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H00 - GPIO */ + PAD_CFG_GPO(GPP_H00, 0, DEEP), + /* GPP_H01 - GPIO */ + PAD_CFG_GPO(GPP_H01, 0, DEEP), + /* GPP_H02 - GPIO */ + PAD_CFG_GPO(GPP_H02, 0, DEEP), + /* GPP_H03 - GPIO */ + PAD_CFG_GPO(GPP_H03, 0, DEEP), + /* GPP_H04 - GPIO */ + PAD_CFG_GPO(GPP_H04, 0, DEEP), + /* GPP_H05 - GPIO */ + PAD_CFG_GPO(GPP_H05, 0, DEEP), + /* GPP_H06 - I2C3_SDA */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), + /* GPP_H07 - I2C3_SCL */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), + /* GPP_H08 - GPIO */ + PAD_CFG_GPO(GPP_H08, 0, DEEP), + /* GPP_H09 - GPIO */ + PAD_CFG_GPO(GPP_H09, 0, DEEP), + /* GPP_H10 - GPIO */ + PAD_CFG_GPO(GPP_H10, 0, DEEP), + /* GPP_H11 - GPIO */ + PAD_CFG_GPO(GPP_H11, 0, DEEP), + /* GPP_H12 - GPIO */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + /* GPP_H13 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), + /* GPP_H14 - GPIO */ + PAD_CFG_GPO(GPP_H14, 0, DEEP), + /* GPP_H15 - GPIO */ + PAD_CFG_GPO(GPP_H15, 0, DEEP), + /* GPP_H16 - GPIO */ + PAD_CFG_GPO(GPP_H16, 0, DEEP), + /* GPP_H17 - GPIO */ + PAD_CFG_GPO(GPP_H17, 0, DEEP), + /* GPP_H18 - GPIO */ + PAD_CFG_GPO(GPP_H18, 0, DEEP), + /* GPP_H19 - I2C0_SDA */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + /* GPP_H20 - I2C0_SCL */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + /* GPP_H21 - I2C1_SDA */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + /* GPP_H22 - I2C1_SCL */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + /* GPP_H23 - GPIO */ + PAD_NC(GPP_H23, NONE), + /* GPP_LPI3C1_CLK_LPBK - GPIO */ + PAD_NC(GPP_LPI3C1_CLK_LPBK, NATIVE), + /* GPP_LPI3C0_CLK_LPBK - n/a */ + PAD_CFG_NF(GPP_LPI3C0_CLK_LPBK, NATIVE, DEEP, NF2), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F00 - CNV_BRI_DT */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), + /* GPP_F01 - CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), + /* GPP_F02 - CNV_RGI_DT */ + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), + /* GPP_F03 - CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), + /* GPP_F04 - CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), + /* GPP_F05 - MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), + /* GPP_F06 - GPIO */ + PAD_CFG_GPO(GPP_F06, 0, DEEP), + /* GPP_F07 - GPIO */ + PAD_CFG_GPO(GPP_F07, 0, DEEP), + /* GPP_F08 - GPIO */ + PAD_CFG_GPO(GPP_F08, 0, DEEP), + /* GPP_F09 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F09, NONE, DEEP, OFF, ACPI), + /* GPP_F10 - GPIO */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + /* GPP_F11 - GPIO */ + PAD_CFG_GPO(GPP_F11, 0, DEEP), + /* GPP_F12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, ACPI), + /* GPP_F13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), + /* GPP_F14 - GPIO */ + PAD_CFG_GPO(GPP_F14, 0, DEEP), + /* GPP_F15 - GPIO */ + PAD_CFG_GPO(GPP_F15, 0, DEEP), + /* GPP_F16 - GPIO */ + PAD_CFG_GPO(GPP_F16, 0, DEEP), + /* GPP_F17 - GPIO */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + /* GPP_F18 - GPIO */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), + /* GPP_F19 - GPIO */ + PAD_CFG_GPO(GPP_F19, 0, DEEP), + /* GPP_F20 - GPIO */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), + /* GPP_F21 - GPIO */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + /* GPP_F22 - GPIO */ + PAD_CFG_GPO(GPP_F22, 0, DEEP), + /* GPP_F23 - GPIO */ + PAD_CFG_GPO(GPP_F23, 0, DEEP), + /* GPP_THC1_GSPI1_CLK_LPBK - GPIO */ + PAD_NC(GPP_THC1_GSPI1_CLK_LPBK, NONE), + /* GPP_GSPI0A_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_GSPI0A_CLK_LOOPBK, NONE), + + /* ------- GPIO Group SPI ------- */ + + /* ------- GPIO Group VGPIO3 ------- */ + + /* GPP_VGPIO3_USB0 - GPP_VGPIO3_USB0 */ + PAD_CFG_NF(GPP_VGPIO3_USB0, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB1 - GPP_VGPIO3_USB1 */ + PAD_CFG_NF(GPP_VGPIO3_USB1, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB2 - GPP_VGPIO3_USB2 */ + PAD_CFG_NF(GPP_VGPIO3_USB2, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB3 - GPP_VGPIO3_USB3 */ + PAD_CFG_NF(GPP_VGPIO3_USB3, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB4 - GPP_VGPIO3_USB4 */ + PAD_CFG_NF(GPP_VGPIO3_USB4, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB5 - GPP_VGPIO3_USB5 */ + PAD_CFG_NF(GPP_VGPIO3_USB5, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB6 - GPP_VGPIO3_USB6 */ + PAD_CFG_NF(GPP_VGPIO3_USB6, NONE, DEEP, NF1), + /* GPP_VGPIO3_USB7 - GPP_VGPIO3_USB7 */ + PAD_CFG_NF(GPP_VGPIO3_USB7, NONE, DEEP, NF1), + /* GPP_VGPIO3_TS0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS0, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_TS1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS1, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_THC0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC0, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_THC1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC1, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_THC2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC2, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO3_THC3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC3, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S00 - GPIO */ + PAD_CFG_GPO(GPP_S00, 0, DEEP), + /* GPP_S01 - GPIO */ + PAD_CFG_GPO(GPP_S01, 0, DEEP), + /* GPP_S02 - GPIO */ + PAD_CFG_GPO(GPP_S02, 0, DEEP), + /* GPP_S03 - GPIO */ + PAD_CFG_GPO(GPP_S03, 0, DEEP), + /* GPP_S04 - GPIO */ + PAD_CFG_GPO(GPP_S04, 0, DEEP), + /* GPP_S05 - GPIO */ + PAD_CFG_GPO(GPP_S05, 0, DEEP), + /* GPP_S06 - GPIO */ + PAD_CFG_GPO(GPP_S06, 0, DEEP), + /* GPP_S07 - GPIO */ + PAD_CFG_GPO(GPP_S07, 0, DEEP), + + /* ------- GPIO Group JTAG ------- */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B00 - GPIO */ + PAD_CFG_GPI_INT(GPP_B00, NONE, PLTRST, LEVEL), + /* GPP_B01 - GPIO */ + PAD_CFG_GPO(GPP_B01, 0, DEEP), + /* GPP_B02 - GPIO */ + PAD_CFG_GPO(GPP_B02, 0, DEEP), + /* GPP_B03 - GPIO */ + PAD_CFG_GPO(GPP_B03, 0, DEEP), + /* GPP_B04 - GPIO */ + PAD_CFG_GPO(GPP_B04, 0, DEEP), + /* GPP_B05 - GPIO */ + PAD_CFG_GPO(GPP_B05, 0, DEEP), + /* GPP_B06 - GPIO */ + PAD_CFG_GPO(GPP_B06, 0, DEEP), + /* GPP_B07 - GPIO */ + PAD_CFG_GPO(GPP_B07, 0, DEEP), + /* GPP_B08 - GPIO */ + PAD_CFG_GPO(GPP_B08, 0, DEEP), + /* GPP_B09 - GPIO */ + PAD_CFG_GPO(GPP_B09, 0, DEEP), + /* GPP_B10 - GPIO */ + PAD_CFG_GPO(GPP_B10, 0, DEEP), + /* GPP_B11 - DDSP_HPD2 */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B14, NONE, DEEP, OFF, ACPI), + /* GPP_B15 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI), + /* GPP_B16 - GPIO */ + PAD_CFG_GPO(GPP_B16, 0, DEEP), + /* GPP_B17 - GPIO */ + PAD_CFG_GPO(GPP_B17, 0, DEEP), + /* GPP_B18 - GPIO */ + PAD_CFG_GPO(GPP_B18, 1, DEEP), + /* GPP_B19 - GPIO */ + PAD_CFG_GPO(GPP_B19, 1, DEEP), + /* GPP_B20 - GPIO */ + PAD_CFG_GPO(GPP_B20, 0, DEEP), + /* GPP_B21 - GPIO */ + PAD_CFG_GPO(GPP_B21, 0, PLTRST), + /* GPP_B22 - GPIO */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), + /* GPP_B23 - GPIO */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + /* GPP_ACI3C0_CLK_LPBK - n/a */ + PAD_CFG_NF(GPP_ACI3C0_CLK_LPBK, NATIVE, DEEP, NF4), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D00 - GPIO */ + PAD_CFG_GPO(GPP_D00, 1, DEEP), + /* GPP_D01 - GPIO */ + PAD_CFG_GPO(GPP_D01, 1, DEEP), + /* GPP_D02 - GPIO */ + PAD_CFG_GPO(GPP_D02, 1, DEEP), + /* GPP_D03 - GPIO */ + PAD_CFG_GPO(GPP_D03, 0, DEEP), + /* GPP_D04 - GPIO */ + PAD_CFG_GPO(GPP_D04, 0, DEEP), + /* GPP_D05 - GPIO */ + PAD_CFG_GPO(GPP_D05, 1, DEEP), + /* GPP_D06 - GPIO */ + PAD_CFG_GPO(GPP_D06, 0, DEEP), + /* GPP_D07 - GPIO */ + PAD_CFG_GPO(GPP_D07, 0, DEEP), + /* GPP_D08 - GPIO */ + PAD_CFG_GPO(GPP_D08, 0, DEEP), + /* GPP_D09 - GPIO */ + PAD_CFG_GPO(GPP_D09, 0, DEEP), + /* GPP_D10 - HDA_BCLK */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), + /* GPP_D11 - HDA_SYNC */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), + /* GPP_D12 - HDA_SDO */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), + /* GPP_D13 - HDA_SDI0 */ + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), + /* GPP_D14 - GPIO */ + PAD_CFG_GPO(GPP_D14, 0, DEEP), + /* GPP_D15 - GPIO */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), + /* GPP_D16 - GPIO */ + PAD_CFG_GPO(GPP_D16, 0, DEEP), + /* GPP_D17 - HDA_RST# */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), + /* GPP_D18 - SRCCLKREQ6# */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), + /* GPP_D19 - SRCCLKREQ7# */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* GPP_D20 - SRCCLKREQ8# */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), + /* GPP_D21 - SRCCLKREQ5# */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), + /* GPP_D22 - n/a */ + PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1), + /* GPP_D23 - n/a */ + PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1), + /* GPP_BOOTHALT_B - n/a */ + PAD_CFG_NF(GPP_BOOTHALT_B, UP_20K, DEEP, NF1), + + /* ------- GPIO Group VGPIO ------- */ + + /* VGPIO00 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO00, 1, DEEP), + /* VGPIO04 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO04, NONE, DEEP, OFF, ACPI), + /* VGPIO05 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO05, 1, DEEP), + /* VGPIO06 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO06, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO07 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO07, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO08 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO08, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO09 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO09, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO10 - VGPIO10 */ + PAD_CFG_NF(GPP_VGPIO10, NONE, DEEP, NF1), + /* VGPIO11 - VGPIO11 */ + PAD_CFG_NF(GPP_VGPIO11, NONE, DEEP, NF1), + /* VGPIO12 - VGPIO12 */ + PAD_CFG_NF(GPP_VGPIO12, NONE, DEEP, NF1), + /* VGPIO13 - VGPIO13 */ + PAD_CFG_NF(GPP_VGPIO13, NONE, DEEP, NF1), + /* VGPIO18 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO18, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO19 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO19, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO20 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO20, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO21 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO21, 0, NONE, DEEP, LEVEL, ACPI), + /* VGPIO22 - VGPIO22 */ + PAD_CFG_NF(GPP_VGPIO22, NONE, DEEP, NF1), + /* VGPIO23 - VGPIO23 */ + PAD_CFG_NF(GPP_VGPIO23, NONE, DEEP, NF1), + /* VGPIO24 - VGPIO24 */ + PAD_CFG_NF(GPP_VGPIO24, NONE, DEEP, NF1), + /* VGPIO25 - VGPIO25 */ + PAD_CFG_NF(GPP_VGPIO25, NONE, DEEP, NF1), + /* VGPIO30 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3), + /* VGPIO31 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3), + /* VGPIO32 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3), + /* VGPIO33 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3), + /* VGPIO34 - VGPIO34 */ + PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1), + /* VGPIO35 - VGPIO35 */ + PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1), + /* VGPIO36 - VGPIO36 */ + PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1), + /* VGPIO37 - VGPIO37 */ + PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1), + /* VGPIO40 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO40, NONE, DEEP, NF2), + /* VGPIO41 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO41, NONE, DEEP, NF2), + /* VGPIO42 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO42, NONE, DEEP, NF2), + /* VGPIO43 - RESERVED */ + PAD_CFG_NF(GPP_VGPIO43, NONE, DEEP, NF2), + /* VGPIO44 - VGPIO44 */ + PAD_CFG_NF(GPP_VGPIO44, NONE, DEEP, NF1), + /* VGPIO45 - VGPIO45 */ + PAD_CFG_NF(GPP_VGPIO45, NONE, DEEP, NF1), + /* VGPIO46 - VGPIO46 */ + PAD_CFG_NF(GPP_VGPIO46, NONE, DEEP, NF1), + /* VGPIO47 - VGPIO47 */ + PAD_CFG_NF(GPP_VGPIO47, NONE, DEEP, NF1), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/novacustom/mtl-h/gpio_early.c b/src/mainboard/novacustom/mtl-h/gpio_early.c new file mode 100644 index 0000000..c47883e --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <mainboard/gpio.h> +#include <soc/gpio.h> + +static const struct pad_config early_gpio_table[] = { + /* GPP_C00 - SMBCLK */ + PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1), + /* GPP_C01 - SMBDATA */ + PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1), +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/novacustom/mtl-h/hda_verb.c b/src/mainboard/novacustom/mtl-h/hda_verb.c new file mode 100644 index 0000000..cd7493e --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/hda_verb.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x1558a763, /* Subsystem ID */ + 13, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1558a763), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40789b2d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + + /* Intel Meteor Lake HDMI */ + 0x8086281d, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h new file mode 100644 index 0000000..57924a6 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/novacustom/mtl-h/ramstage.c b/src/mainboard/novacustom/mtl-h/ramstage.c new file mode 100644 index 0000000..aeba27d --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/ramstage.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/dasharo/ec/commands.h> +#include <ec/acpi/ec.h> +#include <ec/dasharo/ec/acpi.h> +#include <fmap.h> +#include <lib.h> +#include <mainboard/gpio.h> +#include <security/vboot/vboot_common.h> +#include <smbios.h> +#include <soc/ramstage.h> + +const char *smbios_system_sku(void) +{ + return "Not Applicable"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} + +static void mainboard_init(void *chip_info) +{ + mainboard_configure_gpios(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; + + // Pinmux configuration + params->CnviRfResetPinMux = 0x194CE404; // GPP_F04 + params->CnviClkreqPinMux = 0x394CE605; // GPP_F05 + + params->LidStatus = dasharo_ec_get_lid_state(); +} + diff --git a/src/mainboard/novacustom/mtl-h/romstage.c b/src/mainboard/novacustom/mtl-h/romstage.c new file mode 100644 index 0000000..213924c --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/romstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/meminit.h> +#include <soc/romstage.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const bool half_populated = false; + + static const struct mb_cfg mem_config = { + .type = MEM_TYPE_DDR5, + + .rcomp = { + /* Values for MTL-H DDR5 2R */ + .resistor = 100, + + .targets = {70, 30, 25, 25, 25}, + }, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_ULT_ULX, + + .ddr_config = { + .dq_pins_interleaved = false, + } + }; + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + }, + [1] = { + .addr_dimm[0] = 0x52, + }, + }, + }; + + memcfg_init(mupd, &mem_config, &dimm_module_spd_info, half_populated); +} diff --git a/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd b/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd new file mode 100644 index 0000000..75ec893 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd @@ -0,0 +1,50 @@ +FLASH 32M { + SI_ALL 9M { + SI_DESC 16K + SI_GBE 8K + SI_ME + } + SI_BIOS { + RW_SECTION_A 7M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_MISC 2M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_NVRAM(PRESERVE) 24K + BOOTSPLASH(CBFS) 1M + } + + RW_SECTION_B 7M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } + + WP_RO 7M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} -- To view, visit https://review.coreboot.org/c/coreboot/+/82673?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I82c73ddb1e76a9baf9b97e13124aa249ae1c2771 Gerrit-Change-Number: 82673 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com>

1 0

[XL] Change in coreboot[main]: ec/dasharo/ec: add Dasharo features
by Michał Kopeć (Code Review) 27 May '24

27 May '24

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82672?usp=email ) Change subject: ec/dasharo/ec: add Dasharo features ...................................................................... ec/dasharo/ec: add Dasharo features - EC firmware update in ramstage - Setting battery thresholds - PEP hooks for S0ix - Remove unused keyboard backlight, OLED, FCMD Change-Id: I5600487afcb0a4b261d9ff85e3b2c73535a23f3d Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/ec/dasharo/ec/Kconfig M src/ec/dasharo/ec/Makefile.mk A src/ec/dasharo/ec/acpi.h A src/ec/dasharo/ec/acpi/dasharo.asl M src/ec/dasharo/ec/acpi/ec.asl M src/ec/dasharo/ec/acpi/ec_ram.asl M src/ec/dasharo/ec/acpi/lid.asl D src/ec/dasharo/ec/acpi/s76.asl A src/ec/dasharo/ec/buttons.c A src/ec/dasharo/ec/commands.h M src/ec/dasharo/ec/dasharo_ec.c M src/ec/dasharo/ec/dasharo_ec.h D src/ec/dasharo/ec/smbios.c 13 files changed, 899 insertions(+), 307 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/82672/1 diff --git a/src/ec/dasharo/ec/Kconfig b/src/ec/dasharo/ec/Kconfig index 1a007fa..901d3ce 100644 --- a/src/ec/dasharo/ec/Kconfig +++ b/src/ec/dasharo/ec/Kconfig @@ -1,6 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only config EC_DASHARO_EC + select EC_ACPI bool help Dasharo EC @@ -15,7 +16,16 @@ bool default n -config EC_DASHARO_EC_OLED +config EC_DASHARO_EC_UPDATE depends on EC_DASHARO_EC - bool + bool "Update the embedded controller firmware" default n + +config EC_DASHARO_EC_UPDATE_FILE + depends on EC_DASHARO_EC_UPDATE + string "Path to the EC update file" + default "ec.rom" + +config EC_DASHARO_EC_FLASH_SIZE + hex + default 0x20000 diff --git a/src/ec/dasharo/ec/Makefile.mk b/src/ec/dasharo/ec/Makefile.mk index 247bcd4..e3abf1d5 100644 --- a/src/ec/dasharo/ec/Makefile.mk +++ b/src/ec/dasharo/ec/Makefile.mk @@ -1,10 +1,14 @@ -## SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: GPL-2.0-only + ifeq ($(CONFIG_EC_DASHARO_EC),y) all-y += dasharo_ec.c - -ramstage-y += smbios.c - +all-y += buttons.c smm-$(CONFIG_DEBUG_SMI) += dasharo_ec.c +cbfs-files-$(CONFIG_EC_DASHARO_EC_UPDATE) += ec.rom +ec.rom-file :=$(call strip_quotes,$(CONFIG_EC_DASHARO_EC_UPDATE_FILE)) +ec.rom-compression := $(CBFS_COMPRESS_FLAG) +ec.rom-type := raw + endif diff --git a/src/ec/dasharo/ec/acpi.h b/src/ec/dasharo/ec/acpi.h new file mode 100644 index 0000000..35d7279 --- /dev/null +++ b/src/ec/dasharo/ec/acpi.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef EC_DASHARO_EC_ACPI_H +#define EC_DASHARO_EC_ACPI_H + +#include <ec/acpi/ec.h> + +#define DASHARO_EC_REG_LSTE 0x03 +#define DASHARO_EC_REG_LSTE_LID_STATE 0x01 + +#define DASHARO_EC_REG_BATTERY_START_THRESHOLD 0xBC +#define DASHARO_EC_REG_BATTERY_STOP_THRESHOLD 0xBD + +int dasharo_ec_get_lid_state(void); + +enum bat_threshold_type { + BAT_THRESHOLD_START, + BAT_THRESHOLD_STOP +}; + +int dasharo_ec_get_bat_threshold(enum bat_threshold_type type); +void dasharo_ec_set_bat_threshold(enum bat_threshold_type type, uint8_t value); + +#endif /* EC_DASHARO_EC_ACPI_H */ diff --git a/src/ec/dasharo/ec/acpi/dasharo.asl b/src/ec/dasharo/ec/acpi/dasharo.asl new file mode 100644 index 0000000..a51a58f --- /dev/null +++ b/src/ec/dasharo/ec/acpi/dasharo.asl @@ -0,0 +1,117 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Notifications: +// 0x80 - hardware backlight toggle +// 0x81 - backlight toggle +// 0x82 - backlight down +// 0x83 - backlight up +// 0x84 - backlight color change +// 0x85 - OLED screen toggle +Device (DASH) { + Name (_HID, "DASHEC00") + Name (_UID, 0) + // Hide the device so that Windows does not warn about a missing driver. + Name (_STA, 0xB) + + Method (RSET, 0, Serialized) { + Debug = "DASH: RSET" + SAPL(0) + } + Method (INIT, 0, Serialized) { + Printf ("DASH: INIT") + RSET() + If (^^PCI0.LPCB.EC0.ECOK) { + // Set flags to use software control + ^^PCI0.LPCB.EC0.ECOS = 2 + Return (0) + } Else { + Return (1) + } + } + + Method (FINI, 0, Serialized) { + Printf ("DASH: FINI") + RSET() + If (^^PCI0.LPCB.EC0.ECOK) { + // Set flags to use hardware control + ^^PCI0.LPCB.EC0.ECOS = 1 + Return (0) + } Else { + Return (1) + } + } + + // Get Airplane LED + Method (GAPL, 0, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + If (^^PCI0.LPCB.EC0.AIRP & 0x40) { + Return (1) + } + } + Return (0) + } + + // Set Airplane LED + Method (SAPL, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0) { + ^^PCI0.LPCB.EC0.AIRP |= 0x40 + } Else { + ^^PCI0.LPCB.EC0.AIRP &= 0xBF + } + } + } + + // Fan names + Method (NFAN, 0, Serialized) { + Return (Package() { + "CPU fan", +#if CONFIG(EC_DASHARO_EC_DGPU) + "GPU fan", +#endif + }) + } + + // Get fan duty cycle and RPM as a single value + Method (GFAN, 1, Serialized) { + Local0 = 0 + Local1 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0 == 0) { + Local0 = ^^PCI0.LPCB.EC0.DUT1 + Local1 = ^^PCI0.LPCB.EC0.RPM1 + } ElseIf (Arg0 == 1) { + Local0 = ^^PCI0.LPCB.EC0.DUT2 + Local1 = ^^PCI0.LPCB.EC0.RPM2 + } + } + If (Local1 != 0) { + // 60 * (EC frequency / 120) / 2 + Local1 = 2156250 / Local1 + } + Return ((Local1 << 8) | Local0) + } + + // Temperature names + Method (NTMP, 0, Serialized) { + Return (Package() { + "CPU temp", +#if CONFIG(EC_DASHARO_EC_DGPU) + "GPU temp", +#endif + }) + } + + // Get temperature + Method (GTMP, 1, Serialized) { + Local0 = 0; + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0 == 0) { + Local0 = ^^PCI0.LPCB.EC0.TMP1 + } ElseIf (Arg0 == 1) { + Local0 = ^^PCI0.LPCB.EC0.TMP2 + } + } + Return (Local0) + } +} diff --git a/src/ec/dasharo/ec/acpi/ec.asl b/src/ec/dasharo/ec/acpi/ec.asl index e4fcdeb..063b23f 100644 --- a/src/ec/dasharo/ec/acpi/ec.asl +++ b/src/ec/dasharo/ec/acpi/ec.asl @@ -6,7 +6,7 @@ #include "buttons.asl" #include "hid.asl" #include "lid.asl" - #include "s76.asl" + #include "dasharo.asl" } Device (\_SB.PCI0.LPCB.EC0) @@ -36,7 +36,7 @@ { Printf ("EC: _REG %o %o", ToHexString(Arg0), ToHexString(Arg1)) If ((Arg0 == 0x03) && (Arg1 == 1)) { - // Enable hardware touchpad lock, airplane mode, and keyboard backlight keys + // Enable hardware touchpad lock and airplane mode keys ECOS = 1 // Enable software display brightness keys @@ -58,7 +58,7 @@ ECOK = Arg1 // Reset Dasharo Device - ^^^^S76D.RSET() + ^^^^DASH.RSET() } } @@ -90,6 +90,23 @@ // Notify of changes Notify(^^^^AC, 0) Notify(^^^^BAT0, 0) + + // Reset Dasharo Device + ^^^^DASH.RSET() + } + } + + Method (S0IX, 1, Serialized) { + Printf ("EC: S0ix hook") + If (ECOK) { + S0XH = Arg0 + } + } + + Method (EDSX, 1, Serialized) { + Printf ("EC: Display hook") + If (ECOK) { + DSPH = Arg0 } } @@ -101,9 +118,6 @@ Method (_Q0B, 0, NotSerialized) // Screen Toggle { Printf ("EC: Screen Toggle") -#if CONFIG(EC_DASHARO_EC_OLED) - Notify (^^^^S76D, 0x85) -#endif // CONFIG(EC_DASHARO_EC_OLED) } Method (_Q0C, 0, NotSerialized) // Mute @@ -111,11 +125,6 @@ Printf ("EC: Mute") } - Method (_Q0D, 0, NotSerialized) // Keyboard Backlight - { - Printf ("EC: Keyboard Backlight") - } - Method (_Q0E, 0, NotSerialized) // Volume Down { Printf ("EC: Volume Down") @@ -215,24 +224,7 @@ Method (_Q50, 0, NotSerialized) // Other Events { Local0 = OEM4 - If (Local0 == 0x8A) { - Printf ("EC: White Keyboard Backlight") - Notify (^^^^S76D, 0x80) - } ElseIf (Local0 == 0x9F) { - Printf ("EC: Color Keyboard Toggle") - Notify (^^^^S76D, 0x81) - } ElseIf (Local0 == 0x81) { - Printf ("EC: Color Keyboard Down") - Notify (^^^^S76D, 0x82) - } ElseIf (Local0 == 0x82) { - Printf ("EC: Color Keyboard Up") - Notify (^^^^S76D, 0x83) - } ElseIf (Local0 == 0x80) { - Printf ("EC: Color Keyboard Color Change") - Notify (^^^^S76D, 0x84) - } Else { - Printf ("EC: Other: %o", ToHexString(Local0)) - } + Printf ("EC: Other: %o", ToHexString(Local0)) } #if CONFIG(EC_DASHARO_EC_BAT_THRESHOLDS) diff --git a/src/ec/dasharo/ec/acpi/ec_ram.asl b/src/ec/dasharo/ec/acpi/ec_ram.asl index cb5bcf1..0087377 100644 --- a/src/ec/dasharo/ec/acpi/ec_ram.asl +++ b/src/ec/dasharo/ec/acpi/ec_ram.asl @@ -45,11 +45,7 @@ Offset (0xD9), AIRP, 8, // Airplane mode LED WINF, 8, // Enable ACPI brightness controls - Offset (0xF8), - FCMD, 8, - FDAT, 8, - FBUF, 8, - FBF1, 8, - FBF2, 8, - FBF3, 8, + Offset (0xE0), + S0XH, 1, // S0ix hook + DSPH, 1, // Display hook } diff --git a/src/ec/dasharo/ec/acpi/lid.asl b/src/ec/dasharo/ec/acpi/lid.asl index 0a64341..45e646a 100644 --- a/src/ec/dasharo/ec/acpi/lid.asl +++ b/src/ec/dasharo/ec/acpi/lid.asl @@ -6,16 +6,16 @@ Name (_PRW, Package () { EC_GPE_SWI, 3 }) Method (_LID, 0, NotSerialized) { - Printf ("LID: _LID") + DEBUG = "LID: _LID" If (^^PCI0.LPCB.EC0.ECOK) { Return (^^PCI0.LPCB.EC0.LSTE) } Else { - Return (1) + Return (One) } } Method (_PSW, 1, NotSerialized) { - Printf ("LID: _PSW: %o", ToHexString(Arg0)) + DEBUG = Concatenate("LID: _PSW: ", ToHexString(Arg0)) If (^^PCI0.LPCB.EC0.ECOK) { ^^PCI0.LPCB.EC0.LWKE = Arg0 } diff --git a/src/ec/dasharo/ec/acpi/s76.asl b/src/ec/dasharo/ec/acpi/s76.asl deleted file mode 100644 index f23f857..0000000 --- a/src/ec/dasharo/ec/acpi/s76.asl +++ /dev/null @@ -1,178 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -// Notifications: -// 0x80 - hardware backlight toggle -// 0x81 - backlight toggle -// 0x82 - backlight down -// 0x83 - backlight up -// 0x84 - backlight color change -// 0x85 - OLED screen toggle -Device (S76D) { - Name (_HID, "17761776") - Name (_UID, 0) - // Hide the device so that Windows does not warn about a missing driver. - Name (_STA, 0xB) - - Method (RSET, 0, Serialized) { - Printf ("S76D: RSET") - SAPL(0) - SKBB(0) - SKBC(0xFFFFFF) - } - - Method (INIT, 0, Serialized) { - Printf ("S76D: INIT") - RSET() - If (^^PCI0.LPCB.EC0.ECOK) { - // Set flags to use software control - ^^PCI0.LPCB.EC0.ECOS = 2 - Return (0) - } Else { - Return (1) - } - } - - Method (FINI, 0, Serialized) { - Printf ("S76D: FINI") - RSET() - If (^^PCI0.LPCB.EC0.ECOK) { - // Set flags to use hardware control - ^^PCI0.LPCB.EC0.ECOS = 1 - Return (0) - } Else { - Return (1) - } - } - - // Get Airplane LED - Method (GAPL, 0, Serialized) { - If (^^PCI0.LPCB.EC0.ECOK) { - If (^^PCI0.LPCB.EC0.AIRP & 0x40) { - Return (1) - } - } - Return (0) - } - - // Set Airplane LED - Method (SAPL, 1, Serialized) { - If (^^PCI0.LPCB.EC0.ECOK) { - If (Arg0) { - ^^PCI0.LPCB.EC0.AIRP |= 0x40 - } Else { - ^^PCI0.LPCB.EC0.AIRP &= 0xBF - } - } - } - - // Get Keyboard Backlight Kind - // 0 - No backlight - // 1 - White backlight - // 2 - RGB backlight - Method (GKBK, 0, Serialized) { - Local0 = 0 - If (^^PCI0.LPCB.EC0.ECOK) { - ^^PCI0.LPCB.EC0.FDAT = 2 - ^^PCI0.LPCB.EC0.FCMD = 0xCA - Local0 = ^^PCI0.LPCB.EC0.FBUF - } - Return (Local0) - } - - // Get Keyboard Brightness - Method (GKBB, 0, Serialized) { - Local0 = 0 - If (^^PCI0.LPCB.EC0.ECOK) { - ^^PCI0.LPCB.EC0.FDAT = 1 - ^^PCI0.LPCB.EC0.FCMD = 0xCA - Local0 = ^^PCI0.LPCB.EC0.FBUF - } - Return (Local0) - } - - // Set Keyboard Brightness - Method (SKBB, 1, Serialized) { - If (^^PCI0.LPCB.EC0.ECOK) { - ^^PCI0.LPCB.EC0.FDAT = 0 - ^^PCI0.LPCB.EC0.FBUF = Arg0 - ^^PCI0.LPCB.EC0.FCMD = 0xCA - } - } - - // Get Keyboard Color - Method (GKBC, 0, Serialized) { - Local0 = 0 - If (^^PCI0.LPCB.EC0.ECOK) { - ^^PCI0.LPCB.EC0.FDAT = 4 - ^^PCI0.LPCB.EC0.FCMD = 0xCA - Local0 = ^^PCI0.LPCB.EC0.FBUF - Local0 |= (^^PCI0.LPCB.EC0.FBF1) << 16 - Local0 |= (^^PCI0.LPCB.EC0.FBF2) << 8 - } - Return (Local0) - } - - // Set Keyboard Color - Method (SKBC, 1, Serialized) { - If (^^PCI0.LPCB.EC0.ECOK) { - ^^PCI0.LPCB.EC0.FDAT = 3 - ^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF) - ^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF) - ^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF) - ^^PCI0.LPCB.EC0.FCMD = 0xCA - } - } - - // Fan names - Method (NFAN, 0, Serialized) { - Return (Package() { - "CPU fan", -#if CONFIG(EC_DASHARO_EC_DGPU) - "GPU fan", -#endif - }) - } - - // Get fan duty cycle and RPM as a single value - Method (GFAN, 1, Serialized) { - Local0 = 0 - Local1 = 0 - If (^^PCI0.LPCB.EC0.ECOK) { - If (Arg0 == 0) { - Local0 = ^^PCI0.LPCB.EC0.DUT1 - Local1 = ^^PCI0.LPCB.EC0.RPM1 - } ElseIf (Arg0 == 1) { - Local0 = ^^PCI0.LPCB.EC0.DUT2 - Local1 = ^^PCI0.LPCB.EC0.RPM2 - } - } - If (Local1 != 0) { - // 60 * (EC frequency / 120) / 2 - Local1 = 2156250 / Local1 - } - Return ((Local1 << 8) | Local0) - } - - // Temperature names - Method (NTMP, 0, Serialized) { - Return (Package() { - "CPU temp", -#if CONFIG(EC_DASHARO_EC_DGPU) - "GPU temp", -#endif - }) - } - - // Get temperature - Method (GTMP, 1, Serialized) { - Local0 = 0; - If (^^PCI0.LPCB.EC0.ECOK) { - If (Arg0 == 0) { - Local0 = ^^PCI0.LPCB.EC0.TMP1 - } ElseIf (Arg0 == 1) { - Local0 = ^^PCI0.LPCB.EC0.TMP2 - } - } - Return (Local0) - } -} diff --git a/src/ec/dasharo/ec/buttons.c b/src/ec/dasharo/ec/buttons.c new file mode 100644 index 0000000..d5a5ef4 --- /dev/null +++ b/src/ec/dasharo/ec/buttons.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <ec/acpi/ec.h> + +#include "acpi.h" + +/** + * Return the state of lid switch. + * + * @return 1 if the lid is open. + */ +int dasharo_ec_get_lid_state(void) +{ + return ec_read(DASHARO_EC_REG_LSTE) & DASHARO_EC_REG_LSTE_LID_STATE; +} diff --git a/src/ec/dasharo/ec/commands.h b/src/ec/dasharo/ec/commands.h new file mode 100644 index 0000000..f44297f --- /dev/null +++ b/src/ec/dasharo/ec/commands.h @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> + +// SMFI commands + +// Indicates that EC is ready to accept commands +#define CMD_NONE 0 +// Probe for Dasharo EC protocol +#define CMD_PROBE 1 +// Read board string +#define CMD_BOARD 2 +// Read version string +#define CMD_VERSION 3 +// Write bytes to console +#define CMD_PRINT 4 +// Access SPI chip +#define CMD_SPI 5 +// Reset EC +#define CMD_RESET 6 +// Get fan speeds +#define CMD_FAN_GET 7 +// Set fan speeds +#define CMD_FAN_SET 8 +// Get keyboard map index +#define CMD_KEYMAP_GET 9 +// Set keyboard map index +#define CMD_KEYMAP_SET 10 +// Get LED value by index +#define CMD_LED_GET_VALUE 11 +// Set LED value by index +#define CMD_LED_SET_VALUE 12 +// Get LED color by index +#define CMD_LED_GET_COLOR 13 +// Set LED color by index +#define CMD_LED_SET_COLOR 14 +// Get LED matrix mode and speed +#define CMD_LED_GET_MODE 15 +// Set LED matrix mode and speed +#define CMD_LED_SET_MODE 16 +// Get key matrix state +#define CMD_MATRIX_GET 17 +// Save LED settings to ROM +#define CMD_LED_SAVE 18 +// Enable/disable no input mode +#define CMD_SET_NO_INPUT 19 +// Set fan curve +#define CMD_FAN_CURVE_SET 20 +// Get security state +#define CMD_SECURITY_GET = 21, +// Set security state +#define CMD_SECURITY_SET = 22, +// Set camera enablement +#define CMD_CAMERA_ENABLEMENT_SET 23 +// Set WiFi + Bluetooth card enablement +#define CMD_WIFI_BT_ENABLEMENT_SET 24 +// Get a persistent option by index +#define CMD_OPTION_GET 25 +// Set a persistent option by index +#define CMD_OPTION_SET 26 + +// Print command. Registers are unique for each command +#define CMD_PRINT_REG_FLAGS 2 +#define CMD_PRINT_REG_LEN 3 +#define CMD_PRINT_REG_DATA 4 + +// SPI command +// Read from SPI chip if set, write otherwise +#define CMD_SPI_FLAG_READ BIT(0) +// Disable SPI chip after executing command +#define CMD_SPI_FLAG_DISABLE BIT(1) +// Run firmware from scratch RAM if necessary +#define CMD_SPI_FLAG_SCRATCH BIT(2) +// Write to backup ROM instead +#define CMD_SPI_FLAG_BACKUP BIT(3) + +#define CMD_LED_INDEX_ALL 0xFF + +// Persistent option definitions +enum { + OPT_POWER_ON_AC = 0, + NUM_OPTIONS +}; + +uint8_t dasharo_ec_smfi_cmd(uint8_t cmd, uint8_t len, uint8_t *data); +uint8_t dasharo_ec_read_version(uint8_t *data); +uint8_t dasharo_ec_read_board(uint8_t *data); diff --git a/src/ec/dasharo/ec/dasharo_ec.c b/src/ec/dasharo/ec/dasharo_ec.c index 97c9613..985ee3b 100644 --- a/src/ec/dasharo/ec/dasharo_ec.c +++ b/src/ec/dasharo/ec/dasharo_ec.c @@ -1,31 +1,31 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include "dasharo_ec.h" +#include <bootstate.h> #include <arch/io.h> -#include <console/dasharo_ec.h> -#include <console/console.h> +#include <cbfs.h> +#include <console/system76_ec.h> +#include <pc80/mc146818rtc.h> +#include <security/vboot/misc.h> +#include <security/vboot/vboot_common.h> #include <timer.h> +#include "acpi.h" +#include "commands.h" +#include "dasharo_ec.h" // This is the command region for Dasharo EC firmware. It must be // enabled for LPC in the mainboard. #define DASHARO_EC_BASE 0x0E00 #define DASHARO_EC_SIZE 256 -#define REG_CMD 0 +#define SPI_SECTOR_SIZE 1024 + +#define REG_CMD 0 #define REG_RESULT 1 -#define REG_DATA 2 // Start of command data +#define REG_DATA 2 // Start of command data // When command register is 0, command is complete #define CMD_FINISHED 0 -#define RESULT_OK 0 - -// Print command. Registers are unique for each command -#define CMD_PRINT 4 -#define CMD_PRINT_REG_FLAGS 2 -#define CMD_PRINT_REG_LEN 3 -#define CMD_PRINT_REG_DATA 4 - static inline uint8_t dasharo_ec_read(uint8_t addr) { return inb(DASHARO_EC_BASE + (uint16_t)addr); @@ -36,77 +36,600 @@ outb(data, DASHARO_EC_BASE + (uint16_t)addr); } -void dasharo_ec_init(void) +uint8_t dasharo_ec_smfi_cmd(uint8_t cmd, uint8_t len, uint8_t *data) { - // Clear entire command region - for (int i = 0; i < DASHARO_EC_SIZE; i++) - dasharo_ec_write((uint8_t)i, 0); -} + int i; -void dasharo_ec_flush(void) -{ - dasharo_ec_write(REG_CMD, CMD_PRINT); + if (len > DASHARO_EC_SIZE - 2) + return -1; - // Wait for command completion, for up to 10 milliseconds, with a + // Wait for previous command completion, for up to 10 milliseconds, with a // test period of 1 microsecond wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); - dasharo_ec_write(CMD_PRINT_REG_LEN, 0); -} + // Write data first + for (i = 0; i < len; ++i) + dasharo_ec_write(REG_CMD + 2 + i, data[i]); -void dasharo_ec_print(uint8_t byte) -{ - uint8_t len = dasharo_ec_read(CMD_PRINT_REG_LEN); - dasharo_ec_write(CMD_PRINT_REG_DATA + len, byte); - dasharo_ec_write(CMD_PRINT_REG_LEN, len + 1); - - // If we hit the end of the buffer, or were given a newline, flush - if (byte == '\n' || len >= (DASHARO_EC_SIZE - CMD_PRINT_REG_DATA)) - dasharo_ec_flush(); -} - -bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data, - uint8_t request_size, uint8_t *reply_data, uint8_t reply_size) -{ - if (request_size > DASHARO_EC_SIZE - REG_DATA || - reply_size > DASHARO_EC_SIZE - REG_DATA) { - printk(BIOS_ERR, "EC command %d too long - request size %u, reply size %u\n", - cmd, request_size, reply_size); - return false; - } - - /* If any data were buffered by dasharo_ec_print(), flush it first */ - uint8_t buffered_len = dasharo_ec_read(CMD_PRINT_REG_LEN); - if (buffered_len > 0) - dasharo_ec_flush(); - - /* Write the data */ - uint8_t i; - for (i = 0; i < request_size; ++i) - dasharo_ec_write(REG_DATA + i, request_data[i]); - - /* Write the command */ + // Write command register, which starts command dasharo_ec_write(REG_CMD, cmd); - /* Wait for the command to complete */ - bool ret = true; - int elapsed = wait_ms(1000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); - if (elapsed == 0) { - /* Timed out: fail the command, don't attempt to read a reply. */ - printk(BIOS_WARNING, "EC command %d timed out - request size %d, reply size %d\n", - cmd, request_size, reply_size); - ret = false; - } else { - /* Read the reply */ - for (i = 0; i < reply_size; ++i) - reply_data[i] = dasharo_ec_read(REG_DATA+i); - /* Check the reply status */ - ret = (dasharo_ec_read(REG_RESULT) == RESULT_OK); + // Wait for previous command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + return (dasharo_ec_read(REG_RESULT)); +} + +uint8_t dasharo_ec_read_version(uint8_t *data) +{ + int i; + uint8_t result; + + if (!data) + return -1; + + // Wait for previous command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + // Write command register, which starts command + dasharo_ec_write(REG_CMD, CMD_VERSION); + + // Wait for previous command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + result = dasharo_ec_read(REG_RESULT); + + if (result != 0) + return result; + + // Read data bytes, index should be valid due to length test above + for (i = 0; i < (DASHARO_EC_SIZE - REG_DATA); i++) { + data[i] = dasharo_ec_read(REG_DATA + i); + if (data[i] == '\0') + break; } - /* Reset the flags and length so we can buffer console prints again */ - dasharo_ec_write(CMD_PRINT_REG_FLAGS, 0); - dasharo_ec_write(CMD_PRINT_REG_LEN, 0); + return result; +} + +uint8_t dasharo_ec_read_board(uint8_t *data) +{ + int i; + uint8_t result; + + if (!data) + return -1; + + // Wait for previous command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + // Write command register, which starts command + dasharo_ec_write(REG_CMD, CMD_BOARD); + + // Wait for previous command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + result = dasharo_ec_read(REG_RESULT); + + if (result != 0) + return result; + + // Read data bytes, index should be valid due to length test above + for (i = 0; i < (DASHARO_EC_SIZE - REG_DATA); i++) { + data[i] = dasharo_ec_read(REG_DATA + i); + if (data[i] == '\0') + break; + } + + return result; +} + +int dasharo_ec_get_bat_threshold(enum bat_threshold_type type) +{ + int ret = -1; + + switch (type) { + case BAT_THRESHOLD_START: + ret = ec_read(DASHARO_EC_REG_BATTERY_START_THRESHOLD); + break; + case BAT_THRESHOLD_STOP: + ret = ec_read(DASHARO_EC_REG_BATTERY_STOP_THRESHOLD); + break; + default: + break; + } return ret; } + +void dasharo_ec_set_bat_threshold(enum bat_threshold_type type, uint8_t value) +{ + switch (type) { + case BAT_THRESHOLD_START: + ec_write(DASHARO_EC_REG_BATTERY_START_THRESHOLD, value); + break; + case BAT_THRESHOLD_STOP: + ec_write(DASHARO_EC_REG_BATTERY_STOP_THRESHOLD, value); + break; + default: + break; + } +} + +/* Ported from system76_ectool */ +static int firmware_str(char *data, int data_len, const char *key, char *dest, int dest_len) +{ + int data_i, key_i, ret_i; + int key_len = strlen(key); + + data_i = key_i = ret_i = 0; + + /* Locate the key */ + while (data_i < data_len && key_i < key_len) { + if (data[data_i] == key[key_i]) + key_i += 1; + else + key_i = 0; + data_i += 1; + } + + if (key_i < key_len) + return 0; + + while (data_i < data_len && ret_i < dest_len - 1 && data[data_i] != 0) + dest[ret_i++] = data[data_i++]; + + dest[ret_i] = '\0'; + + return ret_i; +} + +/* Reset the EC SPI bus */ +static uint8_t ec_spi_reset(void) +{ + uint8_t reset_cmd = CMD_SPI_FLAG_DISABLE | CMD_SPI_FLAG_SCRATCH; + + return dasharo_ec_smfi_cmd(CMD_SPI, 1, &reset_cmd); +} + +#define SPI_ACCESS_SIZE 252 + +/* + * Read len bytes from EC SPI bus into dest + * Returns 0 on success, <0 on error + */ +static int ec_spi_bus_read(uint8_t *dest, uint32_t len) +{ + uint32_t addr, i, rv; + + uint8_t read_cmd[2] = { + [0] = CMD_SPI_FLAG_READ | CMD_SPI_FLAG_SCRATCH, + [1] = 0, + }; + + for (addr = 0; addr + SPI_ACCESS_SIZE < len; addr += SPI_ACCESS_SIZE) { + read_cmd[1] = SPI_ACCESS_SIZE; + + if ((rv = dasharo_ec_smfi_cmd(CMD_SPI, ARRAY_SIZE(read_cmd), read_cmd))) + return -rv; + + if (dasharo_ec_read(REG_DATA + 1) != read_cmd[1]) + return -1; + + for (i = 0; i < read_cmd[1]; i++) + dest[addr + i] = dasharo_ec_read(REG_DATA + 2 + i); + } + + if (addr == len) + return 0; + + read_cmd[1] = len % SPI_ACCESS_SIZE; + + if ((rv = dasharo_ec_smfi_cmd(CMD_SPI, ARRAY_SIZE(read_cmd), read_cmd))) + return -rv; + + if (dasharo_ec_read(REG_DATA + 1) != read_cmd[1]) + return -1; + + for (i = 0; i < read_cmd[1]; i++) + dest[addr + i] = dasharo_ec_read(REG_DATA + 2 + i); + + return 0; +} + +/* + * Write len bytes from data to EC SPI bus + * Returns 0 on success, <0 on error + */ +static int ec_spi_bus_write(uint8_t *data, uint8_t len) +{ + uint32_t addr, i, rv; + uint8_t write_cmd[2] = { + [0] = CMD_SPI_FLAG_SCRATCH, + [1] = len, + }; + + for (addr = 0; addr + SPI_ACCESS_SIZE < len; addr += SPI_ACCESS_SIZE) { + write_cmd[1] = SPI_ACCESS_SIZE; + + for (i = 0; i < write_cmd[1]; ++i) + dasharo_ec_write(REG_DATA + 2 + i, data[addr + i]); + + if ((rv = dasharo_ec_smfi_cmd(CMD_SPI, ARRAY_SIZE(write_cmd), write_cmd))) + return -rv; + + if (dasharo_ec_read(REG_DATA + 1) != write_cmd[1]) + return -1; + } + + if (addr == len) + return 0; + + write_cmd[1] = len % SPI_ACCESS_SIZE; + + for (i = 0; i < write_cmd[1]; i++) + dasharo_ec_write(REG_DATA + 2 + i, data[addr + i]); + + if ((rv = dasharo_ec_smfi_cmd(CMD_SPI, ARRAY_SIZE(write_cmd), write_cmd))) + return -rv; + + if (dasharo_ec_read(REG_DATA + 1) != write_cmd[1]) + return -1; + + return 0; +} + +static int ec_spi_cmd_status(void) +{ + int rv; + uint8_t cmd; + + if ((rv = ec_spi_reset())) + return rv; + + cmd = 0x05; /* SPI Read Status */ + + if ((rv = ec_spi_bus_write(&cmd, 1))) + return rv; + + if ((rv = ec_spi_bus_read(&cmd, 1))) + return rv; + + return cmd; +} + +static int ec_spi_cmd_write_enable(void) +{ + int status, rv; + uint8_t cmd; + + if ((rv = ec_spi_reset())) + return rv; + + cmd = 0x06; /* SPI Write Enable */ + + if ((rv = ec_spi_bus_write(&cmd, 1))) + return rv; + + do { + status = ec_spi_cmd_status(); + } while (status > 0 && (status & 3) != 2); + + return 0; +} + +static int ec_spi_cmd_write_disable(void) +{ + int status, rv; + uint8_t cmd; + + if ((rv = ec_spi_reset())) + return rv; + + cmd = 0x04; /* SPI Write Disable */ + + if ((rv = ec_spi_bus_write(&cmd, 1))) + return rv; + + do { + status = ec_spi_cmd_status(); + } while (status > 0 && (status & 3) != 0); + + return 0; +} + +/* Erase a sector at addr. Returns 0 on success <0 on error. */ +static int ec_spi_erase_sector(uint32_t addr) +{ + int status, rv; + uint8_t buf[4] = { + [0] = 0xD7, /* SPI Sector Erase */ + [1] = (addr >> 16) & 0xFF, + [2] = (addr >> 8) & 0xFF, + [3] = addr & 0xFF, + }; + + if ((rv = ec_spi_cmd_write_enable())) + return rv; + + if ((rv = ec_spi_reset())) + return rv; + + if ((rv = ec_spi_bus_write(buf, 4))) + return rv; + + do { + status = ec_spi_cmd_status(); + } while (status > 0 && (status & 1) != 0); + + if ((rv = ec_spi_cmd_write_disable())) + return rv; + + return 0; +} + +/* + * Erase the entire chip sector by sector. + * Chip / bulk erase doesn't work on this hardware. + * Returns erased byte count on success and <0 on error. + */ +static int ec_spi_erase_chip(void) +{ + int rv; + uint32_t addr; + + for (addr = 0; addr < CONFIG_EC_DASHARO_EC_FLASH_SIZE; addr += SPI_SECTOR_SIZE) + if ((rv = ec_spi_erase_sector(addr))) + return rv; + + return addr; +} + +/* + * Program an entire chip with a given image. + * Returns written byte count on success and <0 on error. + */ +static int ec_spi_image_write(uint8_t *image, ssize_t size) +{ + int status, rv; + uint32_t addr; + uint8_t buf[6] = {0}; + + if ((rv = ec_spi_cmd_write_enable())) + return rv; + + /* SPI AAI Word Program */ + buf[0] = 0xAD; + + for (addr = 0; addr < size; addr += 2) { + if ((rv = ec_spi_reset())) + return rv; + + if (addr == 0) { + /* 1st cmd bytes 1,2,3 are the address */ + buf[4] = image[0]; + buf[5] = image[1]; + + rv = ec_spi_bus_write(buf, 6); + } else { + buf[1] = image[addr]; + buf[2] = image[addr + 1]; + + rv = ec_spi_bus_write(buf, 3); + } + + if (rv) + return rv; + + do { + status = ec_spi_cmd_status(); + } while (status > 0 && (status & 1) != 0); + } + + if ((rv = ec_spi_cmd_write_disable())) + return rv; + + return addr; +} + +/* Read a sector into dest. Returns 0 on success and <0 on error. */ +static int ec_spi_read_sector(uint8_t *dest, uint32_t addr) +{ + int rv; + uint8_t buf[5] = { + [0] = 0x0B, /* SPI Read */ + [1] = (addr >> 16) & 0xFF, + [2] = (addr >> 8) & 0xFF, + [3] = addr & 0xFF, + [4] = 0, + }; + + if ((rv = ec_spi_reset())) + return rv; + + if ((rv = ec_spi_bus_write(buf, 5))) + return rv; + + if ((rv = ec_spi_bus_read(dest, SPI_SECTOR_SIZE))) + return rv; + + return 0; +} + +/* Verify an image sector by sector. Returns 0 on success and <0 on error. */ +static int ec_spi_image_verify(uint8_t *image, ssize_t image_sz) +{ + uint8_t *sector; + uint32_t addr; + int rv; + + sector = malloc(SPI_SECTOR_SIZE); + if (!sector) + return -1; + rv = 0; + + for (addr = 0; + addr < CONFIG_EC_DASHARO_EC_FLASH_SIZE && addr + SPI_SECTOR_SIZE < image_sz; + addr += SPI_SECTOR_SIZE) { + if ((rv = ec_spi_read_sector(sector, addr))) + goto exit; + + if ((rv = -memcmp(sector, image + addr, SPI_SECTOR_SIZE))) + goto exit; + } + + if (addr == image_sz) + goto exit; + + if ((rv = ec_spi_read_sector(sector, addr))) + goto exit; + + if ((rv = -memcmp(sector, image + addr, image_sz % SPI_SECTOR_SIZE))) + goto exit; + +exit: + free(sector); + return rv; +} + +/* Sync the EC firmware with an image contained in CBFS. */ +static void dasharo_ec_fw_sync(void *unused) +{ + size_t image_sz; + char *image; + char img_board_str[64]; + char img_version_str[64]; + char cur_board_str[64]; + char cur_version_str[64]; + uint8_t smfi_cmd; + int rv; + + if (!CONFIG(EC_DASHARO_EC_UPDATE)) + return; + + if (vboot_recovery_mode_enabled()) { + printk(BIOS_DEBUG, "EC: skipping update in recovery mode.\n"); + return; + } + + image = malloc(CONFIG_EC_DASHARO_EC_FLASH_SIZE); + if (image == NULL) { + printk(BIOS_ERR, "EC: failed to allocate memory for update."); + return; + } + + if (!(image_sz = cbfs_load("ec.rom", image, CONFIG_EC_DASHARO_EC_FLASH_SIZE))) { + printk(BIOS_ERR, "EC: failed to load update from CBFS."); + goto cleanup; + } + + printk(BIOS_DEBUG, "EC: update found (%ld bytes)\n", image_sz); + + if (!image_sz || image_sz % 2 || image_sz > CONFIG_EC_DASHARO_EC_FLASH_SIZE) { + printk(BIOS_ERR, "EC: incorrect update size.\n"); + goto cleanup; + } + + if (!firmware_str(image, image_sz, "76EC_BOARD=", img_board_str, + ARRAY_SIZE(img_board_str))) { + printk(BIOS_ERR, "EC: could not determine update target board.\n"); + goto cleanup; + } + + if (!firmware_str(image, image_sz, "76EC_VERSION=", img_version_str, + ARRAY_SIZE(img_version_str))) { + printk(BIOS_ERR, "EC: could not determine update version.\n"); + goto cleanup; + } + + printk(BIOS_DEBUG, "EC: update target: %s\n", img_board_str); + printk(BIOS_DEBUG, "EC: update version: %s\n", img_version_str); + + dasharo_ec_read_board((uint8_t *)cur_board_str); + dasharo_ec_read_version((uint8_t *)cur_version_str); + + if (strcmp(img_board_str, cur_board_str)) { + printk(BIOS_ERR, "EC: update target mismatch detected! Found %s, expected %s\n", + img_board_str, cur_board_str); + goto cleanup; + } + + printk(BIOS_DEBUG, "EC: current version: %s\n", cur_version_str); + if (!strcmp(img_version_str, cur_version_str)) { + printk(BIOS_DEBUG, "EC: update not needed.\n"); + goto cleanup; + } else { + printk(BIOS_INFO, "EC: update required!\n"); + } + + if ((ec_read(0x10) & 0x01) != 0x01) { + printk(BIOS_WARNING, "EC: AC adapter not connected, skipping update.\n"); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_NO_AC); + goto cleanup; + } + + smfi_cmd = CMD_SPI_FLAG_SCRATCH; + if (dasharo_ec_smfi_cmd(CMD_SPI, 1, &smfi_cmd)) { + printk(BIOS_ERR, "EC: failed to jump to scratch ROM!\n"); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_SCRATCH); + goto cleanup; + } + + rv = ec_spi_erase_chip(); + if (rv < 0) { + printk(BIOS_CRIT, "EC: erase failed!\n"); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_ERASE); + goto cleanup; + } + printk(BIOS_DEBUG, "EC: erased %d bytes\n", rv); + + rv = ec_spi_image_write((uint8_t *)image, image_sz); + if (rv < 0) { + printk(BIOS_ALERT, "EC: update failed!\n"); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_PROGRAM); + goto cleanup; + } + printk(BIOS_DEBUG, "EC: wrote %d bytes\n", rv); + + rv = ec_spi_image_verify((uint8_t *)image, image_sz); + if (rv < 0) { + printk(BIOS_ALERT, "EC: update verification failed!\n"); + } else { + printk(BIOS_DEBUG, "EC: update verified.\n"); + } + + smfi_cmd = CMD_SPI_FLAG_DISABLE; + if (dasharo_ec_smfi_cmd(CMD_SPI, 1, &smfi_cmd)) { + printk(BIOS_ERR, "EC: failed to disable SPI bus!\n"); + goto cleanup; + } + + smfi_cmd = 0; + if (dasharo_ec_smfi_cmd(CMD_RESET, 1, &smfi_cmd)) { + printk(BIOS_ERR, "EC: failed to trigger reset!\n"); + goto cleanup; + } + +cleanup: + free(image); + return; +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, dasharo_ec_fw_sync, NULL); diff --git a/src/ec/dasharo/ec/dasharo_ec.h b/src/ec/dasharo/ec/dasharo_ec.h index f313b0d..d3fa1ab 100644 --- a/src/ec/dasharo/ec/dasharo_ec.h +++ b/src/ec/dasharo/ec/dasharo_ec.h @@ -11,7 +11,18 @@ * request_data can be NULL if request_size is 0. reply_data/reply_size are * the reply payload, reply_data can be NULL if reply_size is 0. */ -bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data, - uint8_t request_size, uint8_t *reply_data, uint8_t reply_size); +bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data, uint8_t request_size, + uint8_t *reply_data, uint8_t reply_size); + +enum ec_update_error { + /* AC adapter is not connected. */ + EC_UPDATE_ERR_NO_AC, + /* EC did not jump to scratch ROM */ + EC_UPDATE_ERR_SCRATCH, + /* EC erase failed */ + EC_UPDATE_ERR_ERASE, + /* Programming EC failed */ + EC_UPDATE_ERR_PROGRAM, +}; #endif diff --git a/src/ec/dasharo/ec/smbios.c b/src/ec/dasharo/ec/smbios.c deleted file mode 100644 index e55d5f0..0000000 --- a/src/ec/dasharo/ec/smbios.c +++ /dev/null @@ -1,9 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <smbios.h> - -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - // TODO: Read wake source from EC. - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} -- To view, visit https://review.coreboot.org/c/coreboot/+/82672?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5600487afcb0a4b261d9ff85e3b2c73535a23f3d Gerrit-Change-Number: 82672 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com>

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[XL] Change in coreboot[main]: ec/dasharo/ec: add support for Dasharo EC
by Michał Kopeć (Code Review) 27 May '24

27 May '24

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82671?usp=email ) Change subject: ec/dasharo/ec: add support for Dasharo EC ...................................................................... ec/dasharo/ec: add support for Dasharo EC Initial commit is a copy of ec/system76/ec with string changes. Dasharo-specific features will be added in subsequent commits. Change-Id: Ic7c3d9413488026548514963eb78accc28e41e06 Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- A src/ec/dasharo/ec/Kconfig A src/ec/dasharo/ec/Makefile.mk A src/ec/dasharo/ec/acpi/ac.asl A src/ec/dasharo/ec/acpi/battery.asl A src/ec/dasharo/ec/acpi/battery_thresholds.asl A src/ec/dasharo/ec/acpi/buttons.asl A src/ec/dasharo/ec/acpi/ec.asl A src/ec/dasharo/ec/acpi/ec_ram.asl A src/ec/dasharo/ec/acpi/hid.asl A src/ec/dasharo/ec/acpi/lid.asl A src/ec/dasharo/ec/acpi/s76.asl A src/ec/dasharo/ec/dasharo_ec.c A src/ec/dasharo/ec/dasharo_ec.h A src/ec/dasharo/ec/smbios.c 14 files changed, 1,045 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/82671/1 diff --git a/src/ec/dasharo/ec/Kconfig b/src/ec/dasharo/ec/Kconfig new file mode 100644 index 0000000..1a007fa --- /dev/null +++ b/src/ec/dasharo/ec/Kconfig @@ -0,0 +1,21 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config EC_DASHARO_EC + bool + help + Dasharo EC + +config EC_DASHARO_EC_BAT_THRESHOLDS + depends on EC_DASHARO_EC + bool + default y + +config EC_DASHARO_EC_DGPU + depends on EC_DASHARO_EC + bool + default n + +config EC_DASHARO_EC_OLED + depends on EC_DASHARO_EC + bool + default n diff --git a/src/ec/dasharo/ec/Makefile.mk b/src/ec/dasharo/ec/Makefile.mk new file mode 100644 index 0000000..247bcd4 --- /dev/null +++ b/src/ec/dasharo/ec/Makefile.mk @@ -0,0 +1,10 @@ +## SPDX-License-Identifier: GPL-2.0-only +ifeq ($(CONFIG_EC_DASHARO_EC),y) + +all-y += dasharo_ec.c + +ramstage-y += smbios.c + +smm-$(CONFIG_DEBUG_SMI) += dasharo_ec.c + +endif diff --git a/src/ec/dasharo/ec/acpi/ac.asl b/src/ec/dasharo/ec/acpi/ac.asl new file mode 100644 index 0000000..66cf742 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/ac.asl @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (AC) +{ + Name (_HID, "ACPI0003" /* Power Source Device */) + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + + Name (ACFG, 1) + + Method (_PSR, 0, NotSerialized) // _PSR: Power Source + { + Return (ACFG) + } + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } +} diff --git a/src/ec/dasharo/ec/acpi/battery.asl b/src/ec/dasharo/ec/acpi/battery.asl new file mode 100644 index 0000000..106f3d1 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/battery.asl @@ -0,0 +1,248 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (BAT0) +{ + Name (_HID, EisaId ("PNP0C0A") /* Control Method Battery */) + Name (_UID, 0) + Name (_PCL, Package (0x01) // _PCL: Power Consumer List + { + _SB + }) + Name (BFCC, 0) + Method (_STA, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.ECOK) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Return (0x1F) + } + Else + { + Return (0x0F) + } + } + Else + { + Return (0x0F) + } + } + + Name (PBIF, Package (0x0D) + { + 1, // 0 - Power Unit + 0xFFFFFFFF, // 1 - Design Capacity + 0xFFFFFFFF, // 2 - Last Full Charge Capacity + 1, // 3 - Battery Technology + 0xFFFFFFFF, // 4 - Design Voltage + 0, // 5 - Design Capacity of Warning + 0, // 6 - Design Capacity of Low + 0x40, // 7 - Battery Capacity Granularity 1 + 0x40, // 8 - Battery Capacity Granularity 2 + " ", // 9 - Model Number + " ", // 10 - Serial Number + " ", // 11 - Battery Type + " " // 12 - OEM Information + }) + Method (IVBI, 0, NotSerialized) + { + PBIF [1] = 0xFFFFFFFF + PBIF [2] = 0xFFFFFFFF + PBIF [4] = 0xFFFFFFFF + PBIF [9] = " " + PBIF [10] = " " + PBIF [11] = " " + PBIF [12] = " " + BFCC = 0 + } + + Method (UPBI, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF) + PBIF [1] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF) + PBIF [2] = Local0 + BFCC = Local0 + Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF) + PBIF [4] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF) + PBIF [5] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF) + PBIF [6] = Local0 + PBIF [9] = "BAT" + PBIF [10] = "0001" + PBIF [11] = "LION" + PBIF [12] = "Notebook" + } + Else + { + IVBI () + } + } + + Method (_BIF, 0, NotSerialized) // _BIF: Battery Information + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBI () + } + Else + { + IVBI () + } + + Return (PBIF) /* \_SB_.BAT0.PBIF */ + } + + Name (PBIX, Package () + { + 0, // 0 - Revision + 1, // 1 - Power Unit: mAh + 0xFFFFFFFF, // 2 - Design Capacity + 0xFFFFFFFF, // 3 - Last Full Charge Capacity + 1, // 4 - Battery Technology: Rechargeable + 0xFFFFFFFF, // 5 - Design Voltage + 0, // 6 - Design Capacity of Warning + 0, // 7 - Design Capacity of Low + 0, // 8 - Cycle Count + 98000, // 9 - Measurement Accuracy + 0xFFFFFFFF, // 10 - Max Sampling Time + 0xFFFFFFFF, // 11 - Min Sampling Time + 0xFFFFFFFF, // 12 - Max Averaging Interval + 0xFFFFFFFF, // 13 - Min Averaging Interval + 0x40, // 14 - Battery Capacity Granularity 1 + 0x40, // 15 - Battery Capacity Granularity 2 + " ", // 16 - Model Number + " ", // 17 - Serial Number + " ", // 18 - Battery Type + " " // 19 - OEM Information + }) + + Method (IVBX, 0, NotSerialized) + { + PBIX [2] = 0xFFFFFFFF + PBIX [3] = 0xFFFFFFFF + PBIX [5] = 0xFFFFFFFF + PBIX [16] = " " + PBIX [17] = " " + PBIX [18] = " " + PBIX [19] = " " + BFCC = 0 + } + + Method (UPBX, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = (^^PCI0.LPCB.EC0.BDC0 & 0xFFFF) + PBIX [2] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BFC0 & 0xFFFF) + PBIX [3] = Local0 + BFCC = Local0 + Local0 = (^^PCI0.LPCB.EC0.BDV0 & 0xFFFF) + PBIX [5] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCW0 & 0xFFFF) + PBIX [6] = Local0 + Local0 = (^^PCI0.LPCB.EC0.BCL0 & 0xFFFF) + PBIX [7] = Local0 + LOCAL0 = ^^PCI0.LPCB.EC0.CYC0 + PBIX [8] = LOCAL0 + PBIX [16] = "BAT" + PBIX [17] = "0001" + PBIX [18] = "LION" + PBIX [19] = "Notebook" + } + Else + { + IVBX () + } + } + + // _BIX: Battery Information Extended + Method (_BIX, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBX () + } + Else + { + IVBX () + } + Return (PBIX) /* \_SB_.BAT0.PBIX */ + } + + Name (PBST, Package (0x04) + { + 0, // 0 - Battery state + 0xFFFFFFFF, // 1 - Battery present rate + 0xFFFFFFFF, // 2 - Battery remaining capacity + 0xFFFFFFFF // 3 - Battery present voltage + }) + Method (IVBS, 0, NotSerialized) + { + PBST [0] = 0 + PBST [1] = 0xFFFFFFFF + PBST [2] = 0xFFFFFFFF + PBST [3] = 0xFFFFFFFF + } + + Method (UPBS, 0, NotSerialized) + { + If (^^PCI0.LPCB.EC0.BAT0) + { + Local0 = 0 + Local1 = 0 + If (^^AC.ACFG) + { + If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02)) + { + Local0 |= 0x02 + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) + } + } + Else + { + Local0 |= 1 + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) + } + + Local7 = (Local1 & 0x8000) + If ((Local7 == 0x8000)) + { + Local1 ^= 0xFFFF + } + + Local2 = (^^PCI0.LPCB.EC0.BRC0 & 0xFFFF) + Local3 = (^^PCI0.LPCB.EC0.BPV0 & 0xFFFF) + PBST [0] = Local0 + PBST [1] = Local1 + PBST [2] = Local2 + PBST [3] = Local3 + If ((BFCC != ^^PCI0.LPCB.EC0.BFC0)) + { + Notify (BAT0, 0x81) // Information Change + } + } + Else + { + IVBS () + } + } + + Method (_BST, 0, NotSerialized) // _BST: Battery Status + { + If (^^PCI0.LPCB.EC0.ECOK) + { + UPBS () + } + Else + { + IVBS () + } + + Return (PBST) /* \_SB_.BAT0.PBST */ + } +} diff --git a/src/ec/dasharo/ec/acpi/battery_thresholds.asl b/src/ec/dasharo/ec/acpi/battery_thresholds.asl new file mode 100644 index 0000000..3bb1330 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/battery_thresholds.asl @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Field (ERAM, ByteAcc, Lock, Preserve) +{ + Offset (0xBC), + BTL0, 8, /* BAT0 charging start threshold */ + BTH0, 8, /* BAT0 charging end threshold */ +} + +/* + * Get battery charging threshold + * + * Arg0: 0: Start threshold + * 1: Stop threshold + */ +Method (GBCT, 1, NotSerialized) +{ + If (Arg0 == 0) { + Return (BTL0) + } + + If (Arg0 == 1) { + Return (BTH0) + } + + Return (0xFF) +} + +/* + * Set battery charging threshold + * + * Arg0: 0: Start threshold + * 1: Stop threshold + * Arg1: Percentage + */ +Method (SBCT, 2, NotSerialized) +{ + If (Arg1 <= 100) { + If (Arg0 == 0) { + BTL0 = Arg1 + } + If (Arg0 == 1) { + BTH0 = Arg1 + } + } +} diff --git a/src/ec/dasharo/ec/acpi/buttons.asl b/src/ec/dasharo/ec/acpi/buttons.asl new file mode 100644 index 0000000..ae85c67 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/buttons.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (PWRB) +{ + Name (_HID, EisaId ("PNP0C0C")) + Name (_PRW, Package () { EC_GPE_SWI, 3 }) +} + +Device (SLPB) +{ + Name (_HID, EisaId ("PNP0C0E")) + Name (_PRW, Package () { EC_GPE_SWI, 3 }) +} diff --git a/src/ec/dasharo/ec/acpi/ec.asl b/src/ec/dasharo/ec/acpi/ec.asl new file mode 100644 index 0000000..e4fcdeb --- /dev/null +++ b/src/ec/dasharo/ec/acpi/ec.asl @@ -0,0 +1,241 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB) { + #include "ac.asl" + #include "battery.asl" + #include "buttons.asl" + #include "hid.asl" + #include "lid.asl" + #include "s76.asl" +} + +Device (\_SB.PCI0.LPCB.EC0) +{ + Name (_HID, EisaId ("PNP0C09") /* Embedded Controller Device */) + Name (_GPE, EC_GPE_SCI) // _GPE: General Purpose Events + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0062, // Range Minimum + 0x0062, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0066, // Range Minimum + 0x0066, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + }) + + #include "ec_ram.asl" + + Name (ECOK, 0) + Method (_REG, 2, Serialized) // _REG: Region Availability + { + Printf ("EC: _REG %o %o", ToHexString(Arg0), ToHexString(Arg1)) + If ((Arg0 == 0x03) && (Arg1 == 1)) { + // Enable hardware touchpad lock, airplane mode, and keyboard backlight keys + ECOS = 1 + + // Enable software display brightness keys + WINF = 1 + + // Set current AC state + ^^^^AC.ACFG = ADP + // Update battery information and status + ^^^^BAT0.UPBI() + ^^^^BAT0.UPBS() + + // Notify of changes + Notify(^^^^AC, 0) + Notify(^^^^BAT0, 0) + + PNOT () + + // EC is now available + ECOK = Arg1 + + // Reset Dasharo Device + ^^^^S76D.RSET() + } + } + + Name (S3OS, 0) + Method (PTS, 1, Serialized) { + Printf ("EC: PTS: %o", ToHexString(Arg0)) + If (ECOK) { + // Save ECOS during sleep + S3OS = ECOS + + // Clear wake cause + WFNO = 0 + } + } + + Method (WAK, 1, Serialized) { + Printf ("EC: WAK: %o", ToHexString(Arg0)) + If (ECOK) { + // Restore ECOS after sleep + ECOS = S3OS + + // Set current AC state + ^^^^AC.ACFG = ADP + + // Update battery information and status + ^^^^BAT0.UPBI() + ^^^^BAT0.UPBS() + + // Notify of changes + Notify(^^^^AC, 0) + Notify(^^^^BAT0, 0) + } + } + + Method (_Q0A, 0, NotSerialized) // Touchpad Toggle + { + Printf ("EC: Touchpad Toggle") + } + + Method (_Q0B, 0, NotSerialized) // Screen Toggle + { + Printf ("EC: Screen Toggle") +#if CONFIG(EC_DASHARO_EC_OLED) + Notify (^^^^S76D, 0x85) +#endif // CONFIG(EC_DASHARO_EC_OLED) + } + + Method (_Q0C, 0, NotSerialized) // Mute + { + Printf ("EC: Mute") + } + + Method (_Q0D, 0, NotSerialized) // Keyboard Backlight + { + Printf ("EC: Keyboard Backlight") + } + + Method (_Q0E, 0, NotSerialized) // Volume Down + { + Printf ("EC: Volume Down") + } + + Method (_Q0F, 0, NotSerialized) // Volume Up + { + Printf ("EC: Volume Up") + } + + Method (_Q10, 0, NotSerialized) // Switch Video Mode + { + Printf ("EC: Switch Video Mode") + } + + Method (_Q11, 0, NotSerialized) // Brightness Down + { + Printf ("EC: Brightness Down") + if (^^^^HIDD.HRDY) { + ^^^^HIDD.HPEM (20) + } + } + + Method (_Q12, 0, NotSerialized) // Brightness Up + { + Printf ("EC: Brightness Up") + if (^^^^HIDD.HRDY) { + ^^^^HIDD.HPEM (19) + } + } + + Method (_Q13, 0, NotSerialized) // Camera Toggle + { + Printf ("EC: Camera Toggle") + } + + Method (_Q14, 0, NotSerialized) // Airplane Mode + { + Printf ("EC: Airplane Mode") + if (^^^^HIDD.HRDY) { + ^^^^HIDD.HPEM (8) + } + // TODO: hardware airplane mode + } + + Method (_Q15, 0, NotSerialized) // Suspend Button + { + Printf ("EC: Suspend Button") + Notify (SLPB, 0x80) + } + + Method (_Q16, 0, NotSerialized) // AC Detect + { + Printf ("EC: AC Detect") + ^^^^AC.ACFG = ADP + Notify (AC, 0x80) // Status Change + If (BAT0) + { + Notify (^^^^BAT0, 0x81) // Information Change + Notify (^^^^BAT0, 0x80) // Status Change + } + } + + Method (_Q17, 0, NotSerialized) // BAT0 Update + { + Printf ("EC: BAT0 Update (17)") + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q19, 0, NotSerialized) // BAT0 Update + { + Printf ("EC: BAT0 Update (19)") + Notify (^^^^BAT0, 0x81) // Information Change + } + + Method (_Q1B, 0, NotSerialized) // Lid Close + { + Printf ("EC: Lid Close") + Notify (LID0, 0x80) + } + + Method (_Q1C, 0, NotSerialized) // Thermal Trip + { + Printf ("EC: Thermal Trip") + /* TODO + Notify (\_TZ.TZ0, 0x81) // Thermal Trip Point Change + Notify (\_TZ.TZ0, 0x80) // Thermal Status Change + */ + } + + Method (_Q1D, 0, NotSerialized) // Power Button + { + Printf ("EC: Power Button") + Notify (PWRB, 0x80) + } + + Method (_Q50, 0, NotSerialized) // Other Events + { + Local0 = OEM4 + If (Local0 == 0x8A) { + Printf ("EC: White Keyboard Backlight") + Notify (^^^^S76D, 0x80) + } ElseIf (Local0 == 0x9F) { + Printf ("EC: Color Keyboard Toggle") + Notify (^^^^S76D, 0x81) + } ElseIf (Local0 == 0x81) { + Printf ("EC: Color Keyboard Down") + Notify (^^^^S76D, 0x82) + } ElseIf (Local0 == 0x82) { + Printf ("EC: Color Keyboard Up") + Notify (^^^^S76D, 0x83) + } ElseIf (Local0 == 0x80) { + Printf ("EC: Color Keyboard Color Change") + Notify (^^^^S76D, 0x84) + } Else { + Printf ("EC: Other: %o", ToHexString(Local0)) + } + } + + #if CONFIG(EC_DASHARO_EC_BAT_THRESHOLDS) + #include "battery_thresholds.asl" + #endif +} diff --git a/src/ec/dasharo/ec/acpi/ec_ram.asl b/src/ec/dasharo/ec/acpi/ec_ram.asl new file mode 100644 index 0000000..cb5bcf1 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/ec_ram.asl @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +OperationRegion (ERAM, EmbeddedControl, 0, 0xFF) +Field (ERAM, ByteAcc, Lock, Preserve) +{ + Offset (0x03), + LSTE, 1, // Lid is open + , 1, + LWKE, 1, // Lid wake + , 5, + Offset (0x07), + TMP1, 8, // CPU temperature + Offset (0x10), + ADP, 1, // AC adapter connected + , 1, + BAT0, 1, // Battery connected + , 5, + WFNO, 8, // Wake cause (not implemented) + Offset (0x16), + BDC0, 32, // Battery design capacity + BFC0, 32, // Battery full capacity + Offset (0x22), + BDV0, 32, // Battery design voltage + BST0, 32, // Battery status + BPR0, 32, // Battery current + BRC0, 32, // Battery remaining capacity + BPV0, 32, // Battery voltage + Offset (0x3A), + BCW0, 32, + BCL0, 32, + CYC0, 16, // Battery cycle count + Offset (0x68), + ECOS, 8, // Detected OS, 0 = no ACPI, 1 = ACPI but no driver, 2 = ACPI with driver + Offset (0xC8), + OEM1, 8, + OEM2, 8, + OEM3, 16, + OEM4, 8, // Extra SCI data + Offset (0xCD), + TMP2, 8, // GPU temperature + DUT1, 8, // Fan 1 duty + DUT2, 8, // Fan 2 duty + RPM1, 16, // Fan 1 RPM + RPM2, 16, // Fan 2 RPM + Offset (0xD9), + AIRP, 8, // Airplane mode LED + WINF, 8, // Enable ACPI brightness controls + Offset (0xF8), + FCMD, 8, + FDAT, 8, + FBUF, 8, + FBF1, 8, + FBF2, 8, + FBF3, 8, +} diff --git a/src/ec/dasharo/ec/acpi/hid.asl b/src/ec/dasharo/ec/acpi/hid.asl new file mode 100644 index 0000000..eb5f420 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/hid.asl @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (HIDD) +{ + Name (_HID, "INT33D5") + Name (HBSY, 0) + Name (HIDX, 0) + Name (HRDY, 0) + + Method (HDEM, 0, Serialized) + { + HBSY = 0 + Return (HIDX) + } + + Method (HDMM, 0, Serialized) + { + Return (0) + } + + Method (HDSM, 1, Serialized) + { + HRDY = Arg0 + } + + Method (HPEM, 1, Serialized) + { + HBSY = 1 + HIDX = Arg0 + + Notify (HIDD, 0xC0) + Local0 = 0 + While ((Local0 < 0xFA) && HBSY) + { + Sleep (0x04) + Local0++ + } + + If (HBSY == 1) + { + HBSY = 0 + HIDX = 0 + Return (1) + } + Else + { + Return (0) + } + } +} diff --git a/src/ec/dasharo/ec/acpi/lid.asl b/src/ec/dasharo/ec/acpi/lid.asl new file mode 100644 index 0000000..0a64341 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/lid.asl @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Device (LID0) +{ + Name (_HID, EisaId ("PNP0C0D")) + Name (_PRW, Package () { EC_GPE_SWI, 3 }) + + Method (_LID, 0, NotSerialized) { + Printf ("LID: _LID") + If (^^PCI0.LPCB.EC0.ECOK) { + Return (^^PCI0.LPCB.EC0.LSTE) + } Else { + Return (1) + } + } + + Method (_PSW, 1, NotSerialized) { + Printf ("LID: _PSW: %o", ToHexString(Arg0)) + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.LWKE = Arg0 + } + } +} diff --git a/src/ec/dasharo/ec/acpi/s76.asl b/src/ec/dasharo/ec/acpi/s76.asl new file mode 100644 index 0000000..f23f857 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/s76.asl @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// Notifications: +// 0x80 - hardware backlight toggle +// 0x81 - backlight toggle +// 0x82 - backlight down +// 0x83 - backlight up +// 0x84 - backlight color change +// 0x85 - OLED screen toggle +Device (S76D) { + Name (_HID, "17761776") + Name (_UID, 0) + // Hide the device so that Windows does not warn about a missing driver. + Name (_STA, 0xB) + + Method (RSET, 0, Serialized) { + Printf ("S76D: RSET") + SAPL(0) + SKBB(0) + SKBC(0xFFFFFF) + } + + Method (INIT, 0, Serialized) { + Printf ("S76D: INIT") + RSET() + If (^^PCI0.LPCB.EC0.ECOK) { + // Set flags to use software control + ^^PCI0.LPCB.EC0.ECOS = 2 + Return (0) + } Else { + Return (1) + } + } + + Method (FINI, 0, Serialized) { + Printf ("S76D: FINI") + RSET() + If (^^PCI0.LPCB.EC0.ECOK) { + // Set flags to use hardware control + ^^PCI0.LPCB.EC0.ECOS = 1 + Return (0) + } Else { + Return (1) + } + } + + // Get Airplane LED + Method (GAPL, 0, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + If (^^PCI0.LPCB.EC0.AIRP & 0x40) { + Return (1) + } + } + Return (0) + } + + // Set Airplane LED + Method (SAPL, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0) { + ^^PCI0.LPCB.EC0.AIRP |= 0x40 + } Else { + ^^PCI0.LPCB.EC0.AIRP &= 0xBF + } + } + } + + // Get Keyboard Backlight Kind + // 0 - No backlight + // 1 - White backlight + // 2 - RGB backlight + Method (GKBK, 0, Serialized) { + Local0 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 2 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + Local0 = ^^PCI0.LPCB.EC0.FBUF + } + Return (Local0) + } + + // Get Keyboard Brightness + Method (GKBB, 0, Serialized) { + Local0 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 1 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + Local0 = ^^PCI0.LPCB.EC0.FBUF + } + Return (Local0) + } + + // Set Keyboard Brightness + Method (SKBB, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 0 + ^^PCI0.LPCB.EC0.FBUF = Arg0 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + } + } + + // Get Keyboard Color + Method (GKBC, 0, Serialized) { + Local0 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 4 + ^^PCI0.LPCB.EC0.FCMD = 0xCA + Local0 = ^^PCI0.LPCB.EC0.FBUF + Local0 |= (^^PCI0.LPCB.EC0.FBF1) << 16 + Local0 |= (^^PCI0.LPCB.EC0.FBF2) << 8 + } + Return (Local0) + } + + // Set Keyboard Color + Method (SKBC, 1, Serialized) { + If (^^PCI0.LPCB.EC0.ECOK) { + ^^PCI0.LPCB.EC0.FDAT = 3 + ^^PCI0.LPCB.EC0.FBUF = (Arg0 & 0xFF) + ^^PCI0.LPCB.EC0.FBF1 = ((Arg0 >> 16) & 0xFF) + ^^PCI0.LPCB.EC0.FBF2 = ((Arg0 >> 8) & 0xFF) + ^^PCI0.LPCB.EC0.FCMD = 0xCA + } + } + + // Fan names + Method (NFAN, 0, Serialized) { + Return (Package() { + "CPU fan", +#if CONFIG(EC_DASHARO_EC_DGPU) + "GPU fan", +#endif + }) + } + + // Get fan duty cycle and RPM as a single value + Method (GFAN, 1, Serialized) { + Local0 = 0 + Local1 = 0 + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0 == 0) { + Local0 = ^^PCI0.LPCB.EC0.DUT1 + Local1 = ^^PCI0.LPCB.EC0.RPM1 + } ElseIf (Arg0 == 1) { + Local0 = ^^PCI0.LPCB.EC0.DUT2 + Local1 = ^^PCI0.LPCB.EC0.RPM2 + } + } + If (Local1 != 0) { + // 60 * (EC frequency / 120) / 2 + Local1 = 2156250 / Local1 + } + Return ((Local1 << 8) | Local0) + } + + // Temperature names + Method (NTMP, 0, Serialized) { + Return (Package() { + "CPU temp", +#if CONFIG(EC_DASHARO_EC_DGPU) + "GPU temp", +#endif + }) + } + + // Get temperature + Method (GTMP, 1, Serialized) { + Local0 = 0; + If (^^PCI0.LPCB.EC0.ECOK) { + If (Arg0 == 0) { + Local0 = ^^PCI0.LPCB.EC0.TMP1 + } ElseIf (Arg0 == 1) { + Local0 = ^^PCI0.LPCB.EC0.TMP2 + } + } + Return (Local0) + } +} diff --git a/src/ec/dasharo/ec/dasharo_ec.c b/src/ec/dasharo/ec/dasharo_ec.c new file mode 100644 index 0000000..97c9613 --- /dev/null +++ b/src/ec/dasharo/ec/dasharo_ec.c @@ -0,0 +1,112 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "dasharo_ec.h" +#include <arch/io.h> +#include <console/dasharo_ec.h> +#include <console/console.h> +#include <timer.h> + +// This is the command region for Dasharo EC firmware. It must be +// enabled for LPC in the mainboard. +#define DASHARO_EC_BASE 0x0E00 +#define DASHARO_EC_SIZE 256 + +#define REG_CMD 0 +#define REG_RESULT 1 +#define REG_DATA 2 // Start of command data + +// When command register is 0, command is complete +#define CMD_FINISHED 0 + +#define RESULT_OK 0 + +// Print command. Registers are unique for each command +#define CMD_PRINT 4 +#define CMD_PRINT_REG_FLAGS 2 +#define CMD_PRINT_REG_LEN 3 +#define CMD_PRINT_REG_DATA 4 + +static inline uint8_t dasharo_ec_read(uint8_t addr) +{ + return inb(DASHARO_EC_BASE + (uint16_t)addr); +} + +static inline void dasharo_ec_write(uint8_t addr, uint8_t data) +{ + outb(data, DASHARO_EC_BASE + (uint16_t)addr); +} + +void dasharo_ec_init(void) +{ + // Clear entire command region + for (int i = 0; i < DASHARO_EC_SIZE; i++) + dasharo_ec_write((uint8_t)i, 0); +} + +void dasharo_ec_flush(void) +{ + dasharo_ec_write(REG_CMD, CMD_PRINT); + + // Wait for command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + dasharo_ec_write(CMD_PRINT_REG_LEN, 0); +} + +void dasharo_ec_print(uint8_t byte) +{ + uint8_t len = dasharo_ec_read(CMD_PRINT_REG_LEN); + dasharo_ec_write(CMD_PRINT_REG_DATA + len, byte); + dasharo_ec_write(CMD_PRINT_REG_LEN, len + 1); + + // If we hit the end of the buffer, or were given a newline, flush + if (byte == '\n' || len >= (DASHARO_EC_SIZE - CMD_PRINT_REG_DATA)) + dasharo_ec_flush(); +} + +bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data, + uint8_t request_size, uint8_t *reply_data, uint8_t reply_size) +{ + if (request_size > DASHARO_EC_SIZE - REG_DATA || + reply_size > DASHARO_EC_SIZE - REG_DATA) { + printk(BIOS_ERR, "EC command %d too long - request size %u, reply size %u\n", + cmd, request_size, reply_size); + return false; + } + + /* If any data were buffered by dasharo_ec_print(), flush it first */ + uint8_t buffered_len = dasharo_ec_read(CMD_PRINT_REG_LEN); + if (buffered_len > 0) + dasharo_ec_flush(); + + /* Write the data */ + uint8_t i; + for (i = 0; i < request_size; ++i) + dasharo_ec_write(REG_DATA + i, request_data[i]); + + /* Write the command */ + dasharo_ec_write(REG_CMD, cmd); + + /* Wait for the command to complete */ + bool ret = true; + int elapsed = wait_ms(1000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + if (elapsed == 0) { + /* Timed out: fail the command, don't attempt to read a reply. */ + printk(BIOS_WARNING, "EC command %d timed out - request size %d, reply size %d\n", + cmd, request_size, reply_size); + ret = false; + } else { + /* Read the reply */ + for (i = 0; i < reply_size; ++i) + reply_data[i] = dasharo_ec_read(REG_DATA+i); + /* Check the reply status */ + ret = (dasharo_ec_read(REG_RESULT) == RESULT_OK); + } + + /* Reset the flags and length so we can buffer console prints again */ + dasharo_ec_write(CMD_PRINT_REG_FLAGS, 0); + dasharo_ec_write(CMD_PRINT_REG_LEN, 0); + + return ret; +} diff --git a/src/ec/dasharo/ec/dasharo_ec.h b/src/ec/dasharo/ec/dasharo_ec.h new file mode 100644 index 0000000..f313b0d --- /dev/null +++ b/src/ec/dasharo/ec/dasharo_ec.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DASHARO_EC_H +#define DASHARO_EC_H + +#include <stdbool.h> +#include <stdint.h> + +/* + * Send a command to the EC. request_data/request_size are the request payload, + * request_data can be NULL if request_size is 0. reply_data/reply_size are + * the reply payload, reply_data can be NULL if reply_size is 0. + */ +bool dasharo_ec_cmd(uint8_t cmd, const uint8_t *request_data, + uint8_t request_size, uint8_t *reply_data, uint8_t reply_size); + +#endif diff --git a/src/ec/dasharo/ec/smbios.c b/src/ec/dasharo/ec/smbios.c new file mode 100644 index 0000000..e55d5f0 --- /dev/null +++ b/src/ec/dasharo/ec/smbios.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <smbios.h> + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + // TODO: Read wake source from EC. + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/82671?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7c3d9413488026548514963eb78accc28e41e06 Gerrit-Change-Number: 82671 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com>

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[XL] Change in coreboot[main]: vc/intel/fsp2_0: Add EagleStream FSP headers
by Fabian Meyer (Code Review) 27 May '24

27 May '24

Fabian Meyer has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/82202?usp=email ) Change subject: vc/intel/fsp2_0: Add EagleStream FSP headers ...................................................................... Abandoned Superseded by CB:80360 -- To view, visit https://review.coreboot.org/c/coreboot/+/82202?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I12bf38ba04fe83b718db969dfe1b8575e4a0b1e5 Gerrit-Change-Number: 82202 Gerrit-PatchSet: 3 Gerrit-Owner: Fabian Meyer <fabian(a)meyfa.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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