coreboot-gerrit May 2024

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[M] Change in coreboot[main]: sio/nuvoton: Implement a common ramstage ACPI LDN helper
by Nico Huber (Code Review) 27 May '24

27 May '24

Attention is currently required from: Keith Hui, Paul Menzel. Nico Huber has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82632?usp=email ) Change subject: sio/nuvoton: Implement a common ramstage ACPI LDN helper ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > Now that I think about it, in the future I'll want to make the port role swapping automatic if keybo […] You mean pc_keyboard_init(), right? That's kind of always deprecated and disabled by default, AIUI (payloads just do it better, except for odd situations with Linux and quirky hardware, i.e. ThinkPad ECs). So I'd just try to implement the smallest possible detection code and put that in LDN A. After all, you'd want this code to work no matter if keyboard init is done in coreboot, I guess. -- To view, visit https://review.coreboot.org/c/coreboot/+/82632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibaddcaa2d77c5b06ddfbb6dbaac00df5e72dd4bd Gerrit-Change-Number: 82632 Gerrit-PatchSet: 5 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Mon, 27 May 2024 14:46:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: sio/nuvoton: Add Kconfig for shared PS/2 port
by Paul Menzel (Code Review) 27 May '24

27 May '24

Attention is currently required from: Felix Held, Keith Hui. Paul Menzel has posted comments on this change by Keith Hui. ( https://review.coreboot.org/c/coreboot/+/82631?usp=email ) Change subject: sio/nuvoton: Add Kconfig for shared PS/2 port ...................................................................... Patch Set 2: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82631/comment/0172eda4_ae7fb51a?us… : PS1, Line 11: On these boards (where a Y-cable cannot allow both : keyboard and mouse to work off the same port), if a PS/2 keyboard is : not present, SIO should be configured to swap its role to mouse, to : allow the OS to find and initialize any mouse connected. > It is definitely board dependent. […] Thank you for the thorough explanation. -- To view, visit https://review.coreboot.org/c/coreboot/+/82631?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I156b15c6ba233cbe8b9ba4d2cfbca6836ad7483a Gerrit-Change-Number: 82631 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 27 May 2024 14:17:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/pujjoga: Update touchscreen IC settings
by Paul Menzel (Code Review) 27 May '24

27 May '24

Attention is currently required from: Dinesh Gehlot, Felix Held, Kapil Porwal, Leo Chou, Nick Vaccaro, Roger Wang, Shou-Chieh Hsu. Paul Menzel has posted comments on this change by Roger Wang. ( https://review.coreboot.org/c/coreboot/+/82427?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/pujjoga: Update touchscreen IC settings ...................................................................... Patch Set 13: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82427/comment/d7ea1163_fe24cc8a?us… : PS10, Line 9: remove 3 unused : touchscreens. According to the information provided by the key-part : team. > Yes, The system only have Goodix touchscreen on Sundance. Excuse my ignorance. The commit message says `nissa/var/pujjoga`. What does Sundance have to do with it? Were the removed parts just copied and pasted? -- To view, visit https://review.coreboot.org/c/coreboot/+/82427?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e6349e80431aadf27cd72b8439b01f95348071d Gerrit-Change-Number: 82427 Gerrit-PatchSet: 13 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Attention: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Attention: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 27 May 2024 14:16:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com>

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[S] Change in coreboot[main]: soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility
by Paul Menzel (Code Review) 27 May '24

27 May '24

Attention is currently required from: Appukuttan V K, Subrata Banik. Paul Menzel has posted comments on this change by Appukuttan V K. ( https://review.coreboot.org/c/coreboot/+/82177?usp=email ) Change subject: soc/intel/meteorlake: Adjust FSP parameters for FSP2.4 compatibility ...................................................................... Patch Set 18: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82177/comment/257d171e_fe3fb8f2?us… : PS18, Line 10: the FSP2.4 : specification Maybe something like: …, that supports 64-bit builds for the first time … -- To view, visit https://review.coreboot.org/c/coreboot/+/82177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ide220f60184135a6488f4472f69a471e2b383e2a Gerrit-Change-Number: 82177 Gerrit-PatchSet: 18 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Mon, 27 May 2024 14:14:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)
by Felix Held (Code Review) 27 May '24

27 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email ) Change subject: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1) ...................................................................... mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1) AOOSTAR R1 is a Chinese NAS based on Intel N100 (Alder Lake N), with two 3.5" HDD slots, an M.2 NVMe 2280 SSD slot and a single DDR4-3200 SODIMM slot up to 32GB. It also comes with 2x 2.5Gb Intel NICs, Intel AX200 WiFi + BT and USB-C Alt-DP Power Delivery. Working: - DDR4 RAM (tested with Crucial 16GB 3200MHz CL22) - Automatic FAN control (IT8613E Super I/O) - M.2 NVME slot - 2x SATA ports (Issue on 3.5" HDD, see below) - USB 2.0 ports - USB 3.0 ports - USB-C port with Alt-DP and PD - HDMI / DisplayPort ports - 2x 2.5Gb NICs - WiFi + BT - MicroSD card reader - ASPM (Unavailable on stock) - Linux (Arch Linux, kernel 6.8.7-arch1-1) UEFI booting with EDK2 - Windows 10 UEFI booting with EDK2 Broken: - Power button (OFF->ON broken, ON->OFF works) - 3.5" SATA HDDs (Detected only after reboot) Untested: - Internal audio - S3 My motivation for doing this port is enabling ASPM, as it makes a great difference on idle power consumption (from 8.4W to 5W measured from the wall). The last remaining annoyance of this port is the power button not working. I spent a few hours double checking the Super I/O registers but then I gave up. A workaround for this is to use the "ON after power loss" feature and reconnect the power cord to turn on the board. It's not a big problem for a NAS that will stay ON 24/7. Any hint on the power button or 3.5" HDD issue is welcome. VBT extracted from vendor UEFI firmware version 1AXFE 0.01 x64 (Build date and time 11/29/2023 10:57:44) Compiled with FSP GOP video initialization, using IFD descriptor and ME blob extracted from vendor UEFI firmware (see above). The board can be flashed externally using a 1.8V adapter, I used a CH341a modded for 3.3V I/O. Internal flashing works, as flash is not read/write protected. Patchset 5: Re-enabled dptf, added default options to Kconfig. Patchset 7: Configured USB port mapping and overcurrent, USB3.0 works Patchset 8: Fixed microSD card reader Patchset 13: Change Super I/O Fan configuration to reduce fan noise Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Signed-off-by: Federico Amedeo Izzo <federico(a)izzo.pro> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82010 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- A src/mainboard/aoostar/Kconfig A src/mainboard/aoostar/Kconfig.name A src/mainboard/aoostar/wtr_r1/Kconfig A src/mainboard/aoostar/wtr_r1/Kconfig.name A src/mainboard/aoostar/wtr_r1/Makefile.mk A src/mainboard/aoostar/wtr_r1/board_info.txt A src/mainboard/aoostar/wtr_r1/bootblock.c A src/mainboard/aoostar/wtr_r1/data.vbt A src/mainboard/aoostar/wtr_r1/devicetree.cb A src/mainboard/aoostar/wtr_r1/dsdt.asl A src/mainboard/aoostar/wtr_r1/gpio.h A src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c 12 files changed, 726 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/aoostar/Kconfig b/src/mainboard/aoostar/Kconfig new file mode 100644 index 0000000..170ea88 --- /dev/null +++ b/src/mainboard/aoostar/Kconfig @@ -0,0 +1,18 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if VENDOR_AOOSTAR + +choice + prompt "Mainboard model" + +source "src/mainboard/aoostar/*/Kconfig.name" + +endchoice + +source "src/mainboard/aoostar/*/Kconfig" + +config MAINBOARD_VENDOR + string + default "AOOSTAR" + +endif # VENDOR_AOOSTAR diff --git a/src/mainboard/aoostar/Kconfig.name b/src/mainboard/aoostar/Kconfig.name new file mode 100644 index 0000000..e763b3f --- /dev/null +++ b/src/mainboard/aoostar/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config VENDOR_AOOSTAR + bool "AOOSTAR" diff --git a/src/mainboard/aoostar/wtr_r1/Kconfig b/src/mainboard/aoostar/wtr_r1/Kconfig new file mode 100644 index 0000000..fd7ddbf --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/Kconfig @@ -0,0 +1,47 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_AOOSTAR_WTR_R1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_I2C_GENERIC + select DRIVERS_INTEL_DPTF + select DRIVERS_SPI_ACPI + select DRIVERS_USB_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SUPERIO_ITE_IT8613E + select DRIVERS_UART_8250IO + select USE_LEGACY_8254_TIMER + select SOC_INTEL_ALDERLAKE_PCH_N + +config MAINBOARD_DIR + default "aoostar/wtr_r1" + +config MAINBOARD_PART_NUMBER + default "WTR R1" + +config MAINBOARD_FAMILY + string + default "AOOSTAR_WTR_R1" + +config PCIEXP_ASPM + default y + +# Setting this makes NVMe SSD not work +config PCIEXP_L1_SUB_STATE + default n + +# Setting this makes 2.5Gb NICs not work +config PCIEXP_CLK_PM + default n + +# This platform has limited means to display POST codes +config NO_POST + default y + +endif #BOARD_AOOSTAR_WTR_R1 diff --git a/src/mainboard/aoostar/wtr_r1/Kconfig.name b/src/mainboard/aoostar/wtr_r1/Kconfig.name new file mode 100644 index 0000000..45bfdec --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_AOOSTAR_WTR_R1 + bool "WTR R1" diff --git a/src/mainboard/aoostar/wtr_r1/Makefile.mk b/src/mainboard/aoostar/wtr_r1/Makefile.mk new file mode 100644 index 0000000..72915ef --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += romstage_fsp_params.c diff --git a/src/mainboard/aoostar/wtr_r1/board_info.txt b/src/mainboard/aoostar/wtr_r1/board_info.txt new file mode 100644 index 0000000..363cd53 --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: AOOSTAR +Board name: WTR R1 +Board URL: https://aoostar.com/products/aoostar-r1-2bay-nas-intel-n100-mini-pc-with-w1… +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2023 diff --git a/src/mainboard/aoostar/wtr_r1/bootblock.c b/src/mainboard/aoostar/wtr_r1/bootblock.c new file mode 100644 index 0000000..d494f9a --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/bootblock.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8613e/it8613e.h> + +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) + +void bootblock_mainboard_early_init(void) +{ + /* Set up GPIOs on Super I/O. */ + ite_reg_write(GPIO_DEV, 0x25, 0x01); // Enable Pin GP10 + ite_reg_write(GPIO_DEV, 0x27, 0x02); // Enable Pin GP31 + ite_reg_write(GPIO_DEV, 0x28, 0x01); // Enable Pin GP40 + ite_reg_write(GPIO_DEV, 0x29, 0x01); // Enable Pin GP50 + ite_reg_write(GPIO_DEV, 0x2c, 0x41); // Internal Voltage Divider for ACC3 + ite_reg_write(GPIO_DEV, 0xbc, 0xc0); // GP56, GP57 Internal pullup + ite_reg_write(GPIO_DEV, 0xbd, 0x03); // GP60, GP61 Internal pullup + ite_reg_write(GPIO_DEV, 0xc3, 0x41); // GP40, GP46 Simple I/O function + ite_set_3vsbsw(GPIO_DEV, true); + ite_delay_pwrgd3(GPIO_DEV); +} + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/aoostar/wtr_r1/data.vbt b/src/mainboard/aoostar/wtr_r1/data.vbt new file mode 100644 index 0000000..f25d9d9 --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/data.vbt Binary files differ diff --git a/src/mainboard/aoostar/wtr_r1/devicetree.cb b/src/mainboard/aoostar/wtr_r1/devicetree.cb new file mode 100644 index 0000000..101bb99 --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/devicetree.cb @@ -0,0 +1,212 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/alderlake + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + register "sagv" = "SaGv_Enabled" + + register "dptf_enable" = "1" + + register "s0ix_enable" = "1" + + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + # Configure external V1P05/Vnn/VnnSx Rails + register "ext_fivr_settings" = "{ + .configure_ext_fivr = 1, + .v1p05_enable_bitmap = FIVR_ENABLE_ALL_SX & ~FIVR_ENABLE_S0, + .vnn_enable_bitmap = FIVR_ENABLE_ALL_SX, + .vnn_sx_enable_bitmap = FIVR_ENABLE_ALL_SX, + .v1p05_supported_voltage_bitmap = FIVR_VOLTAGE_NORMAL, + .vnn_supported_voltage_bitmap = FIVR_VOLTAGE_MIN_ACTIVE, + .v1p05_voltage_mv = 1050, + .vnn_voltage_mv = 780, + .vnn_sx_voltage_mv = 1050, + .v1p05_icc_max_ma = 500, + .vnn_icc_max_ma = 500, + }" + + device domain 0 on + device ref igpu on + register "ddi_portA_config" = "1" + register "ddi_portB_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + end + device ref dtt on end + device ref crashlog off end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)" # USB3/2 Type A upper + end + device ref xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_TYPE_C(OC0), /* Type-C */ + [1] = USB2_PORT_MID(OC_SKIP), /* microSD card reader */ + [2] = USB2_PORT_MID(OC3), /* USB2 Type A upper */ + [3] = USB2_PORT_MID(OC3), /* USB2 Type A lower */ + [4] = USB2_PORT_MID(OC3), /* USB3/2 Type A upper */ + [5] = USB2_PORT_MID(OC3), /* USB3/2 Type A lower */ + [7] = USB2_PORT_MID(OC_SKIP), /* M.2 WLAN */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), /* Type-C */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* microSD card reader */ + [5] = USB3_PORT_DEFAULT(OC3), /* USB3/2 Type A lower */ + [6] = USB3_PORT_DEFAULT(OC3), /* USB3/2 Type A upper */ + }" + end + device ref cnvi_wifi on + register "cnvi_bt_core" = "true" + register "cnvi_bt_audio_offload" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + end + device ref i2c1 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref i2c2 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C2]" = "PchSerialIoPci" + end + device ref i2c3 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci" + end + device ref sata on + register "sata_salp_support" = "1" + register "sata_ports_enable" = "{ + [0] = 1, + [1] = 1, + }" + register "sata_ports_dev_slp" = "{ + [0] = 1, + [1] = 1, + }" + end + device ref i2c5 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci" + end + device ref pcie_rp3 on + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth2X" + end + device ref pcie_rp7 on # LAN1 + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + end + device ref pcie_rp9 on # LAN2 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + end + device ref pcie_rp10 on + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_CLK_REQ_DETECT, + }" + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2/E 2230 (M2_WIFI1)" "SlotDataBusWidth1X" + end + device ref pch_espi on + # Needed for ITE SuperIO + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c03e1" + register "gen4_dec" = "0x001c02e1" + chip superio/ite/it8613e + register "TMPIN1.mode" = "THERMAL_RESISTOR" + register "ec.vin_mask" = "VIN_ALL" + # CPU_FAN1 + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" + register "FAN2.smart.tmpin" = " 1" + register "FAN2.smart.tmp_off" = "32" # Vendor default: 30 + register "FAN2.smart.tmp_start" = "35" + register "FAN2.smart.tmp_full" = "96" + register "FAN2.smart.tmp_delta" = " 1" # Vendor default: 2 + register "FAN2.smart.pwm_start" = "30" # Vendor default: 40 + register "FAN2.smart.slope" = " 1" + # SYSFANCN1 + register "FAN3.mode" = "FAN_SMART_SOFTWARE" + register "FAN3.smart.pwm_start" = "80" + # SYS_FAN1 + register "FAN4.mode" = "FAN_SMART_SOFTWARE" + register "FAN4.smart.pwm_start" = "127" + + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # COM 1 + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa30 + io 0x62 = 0xa20 + irq 0x70 = 0x00 + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 on # GPIO + io 0x60 = 0x000 + io 0x62 = 0xa00 + irq 0x70 = 0x00 + irq 0x71 = 0x01 + end + device pnp 2e.a off end # CIR + end + end + device ref uart0 on + register "serial_io_uart_mode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + }" + end + device ref gspi0 on + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + }" + end + device ref ish on end + device ref hda on + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + end + device ref smbus on end + end +end diff --git a/src/mainboard/aoostar/wtr_r1/dsdt.asl b/src/mainboard/aoostar/wtr_r1/dsdt.asl new file mode 100644 index 0000000..58c147e --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +#include <gpio.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> +} diff --git a/src/mainboard/aoostar/wtr_r1/gpio.h b/src/mainboard/aoostar/wtr_r1/gpio.h new file mode 100644 index 0000000..067b9ce --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/gpio.h @@ -0,0 +1,330 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include <gpio.h> + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ + PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* VRALERT# */ + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), /* PMCALERT# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), /* SPKR */ + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_CFG_GPO(GPP_B18, 0, DEEP), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_GPO(GPP_B23, 0, DEEP), + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), /* GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), /* GSPI1_CLK_LOOPBK */ + + /* ------- GPIO Group GPP_T ------- */ + PAD_NC(GPP_T0, NONE), + PAD_NC(GPP_T1, NONE), + PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2), /* FUSA_DIAGTEST_EN */ + PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2), /* FUSA_DIAGTEST_MODE */ + PAD_NC(GPP_T4, NONE), + PAD_NC(GPP_T5, NONE), + PAD_NC(GPP_T6, NONE), + PAD_NC(GPP_T7, NONE), + PAD_NC(GPP_T8, NONE), + PAD_NC(GPP_T9, NONE), + PAD_NC(GPP_T10, NONE), + PAD_NC(GPP_T11, NONE), + PAD_NC(GPP_T12, NONE), + PAD_NC(GPP_T13, NONE), + PAD_NC(GPP_T14, NONE), + PAD_NC(GPP_T15, NONE), + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* ESPI_IO0 */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* ESPI_IO1 */ + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* ESPI_IO2 */ + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* ESPI_IO3 */ + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* ESPI_CS0# */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* ESPI_ALERT1# */ + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* ESPI_RESET# */ + PAD_NC(GPP_A11, NONE), + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), /* SATAXPCIE1 */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* USB_OC1# */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* USB_OC2# */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* USB_OC3# */ + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDSP_HPDB */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* DDSP_HPD1 */ + PAD_NC(GPP_A20, NONE), + PAD_CFG_GPO(GPP_A21, 1, PLTRST), + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), /* DDPC_CTRLDATA */ + PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), /* ESPI_CS1# */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), /* GPP_ESPI_CLK_LOOPBK */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_I ------- */ + PAD_NC(GPP_I0, NONE), + PAD_NC(GPP_I1, NONE), + PAD_NC(GPP_I2, NONE), + PAD_NC(GPP_I3, NONE), + PAD_NC(GPP_I4, NONE), + PAD_NC(GPP_I5, NONE), + PAD_NC(GPP_I6, NONE), + PAD_NC(GPP_I7, NONE), + PAD_NC(GPP_I8, NONE), + PAD_NC(GPP_I9, NONE), + PAD_NC(GPP_I10, NONE), + PAD_NC(GPP_I11, NONE), + PAD_NC(GPP_I12, NONE), + PAD_NC(GPP_I13, NONE), + PAD_NC(GPP_I14, NONE), + PAD_NC(GPP_I15, NONE), + PAD_NC(GPP_I16, NONE), + PAD_NC(GPP_I17, NONE), + PAD_NC(GPP_I18, NONE), + PAD_NC(GPP_I19, NONE), + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), + PAD_CFG_GPO(GPP_H1, 0, DEEP), + PAD_CFG_GPO(GPP_H2, 0, DEEP), + PAD_CFG_GPO(GPP_H3, 1, PLTRST), + PAD_NC(GPP_H4, NONE), + PAD_NC(GPP_H5, NONE), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, NONE), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), /* n/a */ + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDPB_CTRLCLK */ + PAD_NC(GPP_H16, NONE), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* SRCCLKREQ4# */ + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* SRCCLKREQ1# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* SRCCLKREQ3# */ + PAD_CFG_NF(GPP_D9, NATIVE, DEEP, NF5), /* BSSB_LS2_RX */ + PAD_CFG_NF(GPP_D10, NATIVE, DEEP, NF5), /* BSSB_LS2_TX */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF5), /* BSSB_LS3_RX */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF5), /* BSSB_LS3_TX */ + PAD_NC(GPP_D13, NONE), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* UART1_RXD */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* UART1_TXD */ + PAD_NC(GPP_D19, NONE), + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), /* GPP_GSPI2_CLK_LOOPBK */ + + /* ------- GPIO Group vGPIO ------- */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), /* GPP_VGPIO_6 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), /* GPP_VGPIO_7 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), /* GPP_VGPIO_8 */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), /* GPP_VGPIO_9 */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), /* GPP_VGPIO_10 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), /* GPP_VGPIO_11 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), /* GPP_VGPIO_12 */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), /* GPP_VGPIO_13 */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), /* GPP_VGPIO_18 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), /* GPP_VGPIO_19 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), /* GPP_VGPIO_20 */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), /* GPP_VGPIO_21 */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), /* GPP_VGPIO_22 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), /* GPP_VGPIO_23 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), /* GPP_VGPIO_24 */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), /* GPP_VGPIO_25 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), /* GPP_VGPIO_30 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), /* GPP_VGPIO_31 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), /* GPP_VGPIO_32 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), /* GPP_VGPIO_33 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* GPP_VGPIO_34 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* GPP_VGPIO_35 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* GPP_VGPIO_36 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* GPP_VGPIO_37 */ + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* BATLOW# */ + PAD_CFG_NF(GPD1, NONE, PWROK, NF1), /* ACPRESENT */ + PAD_CFG_GPO(GPD2, 1, PLTRST), + PAD_CFG_NF(GPD3, NONE, PWROK, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */ + PAD_CFG_GPO(GPD7, 0, PWROK), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */ + PAD_CFG_GPO(GPD11, 0, PWROK), + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), /* GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), /* GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), /* GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), /* GPD_WAKEB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), /* GPD_DRAM_RESETB */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMBDATA */ + PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), /* SMBALERT# */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0DATA */ + PAD_CFG_TERM_GPO(GPP_C5, 1, DN_20K, PLTRST), + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), /* SML1CLK */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), /* SML1DATA */ + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), /* CNV_PA_BLANKING */ + PAD_CFG_GPO(GPP_F7, 0, DEEP), + PAD_NC(GPP_F8, NONE), + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* BOOTMPC */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* Reserved */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* Reserved */ + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), /* n/a */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_NF(GPP_E0, UP_20K, DEEP, NF1), /* SATAXPCIE0 */ + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_CFG_TERM_GPO(GPP_E6, 1, DN_20K, PLTRST), + PAD_NC(GPP_E7, NONE), + PAD_CFG_GPO(GPP_E8, 0, PLTRST), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */ + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA */ + PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2), /* Reserved */ + PAD_CFG_GPO(GPP_E16, 0, PLTRST), + PAD_NC(GPP_E17, NONE), + PAD_NC(GPP_E18, NATIVE), + PAD_NC(GPP_E19, NATIVE), + PAD_CFG_NF(GPP_E20, NATIVE, DEEP, NF5), /* BSSB_LS1_RX */ + PAD_CFG_NF(GPP_E21, NATIVE, DEEP, NF5), /* BSSB_LS1_TX */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), /* DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DDPA_CTRLDATA */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1), /* HDA_SDO */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1), /* HDA_SDI0 */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), /* HDA_RST# */ + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c b/src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c new file mode 100644 index 0000000..1477bc0 --- /dev/null +++ b/src/mainboard/aoostar/wtr_r1/romstage_fsp_params.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <soc/meminit.h> + +#include "gpio.h" + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + /* According to DOC #573387 rcomp values no longer have to be provided */ + /* DDR DIMM configuration does not need to set DQ/DQS maps */ + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, + + .LpDdrDqDqsReTraining = 1, + + .ddr_config = { + .dq_pins_interleaved = false, + }, +}; + +static const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus[0] = { .addr_dimm[0] = 0x50, }, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + /* + * Alder Lake common meminit block driver considers bus width to be 128-bit and + * populates the meminit data accordingly. Alder Lake-N has single memory controller + * with 64-bit bus width. By setting half_populated to true, only the bottom half is + * populated. + * TODO: Implement __weak variant_is_half_populated(void) function. + */ + const bool half_populated = true; + + memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, half_populated); + + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 17 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Brandon Weeks <bweeks(a)google.com>

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[L] Change in coreboot[main]: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1)
by Felix Held (Code Review) 27 May '24

27 May '24

Attention is currently required from: Federico Amedeo Izzo, Felix Singer, Paul Menzel. Felix Held has posted comments on this change by Federico Amedeo Izzo. ( https://review.coreboot.org/c/coreboot/+/82010?usp=email ) Change subject: mb/aoostar: Add Alder Lake based AOOSTAR R1 (WTR_R1) ...................................................................... Patch Set 16: (1 comment) File src/mainboard/aoostar/wtr_r1/gpio.h: PS14: > Thank you for the heads up! I figured out running `intelp2m` with `-n` does exactly that. […] ah, good to know that the intelp2m tool has a command line switch to generate code using the higher level macros -- To view, visit https://review.coreboot.org/c/coreboot/+/82010?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9414eb742b6b90459e010b038c1994537e9801a5 Gerrit-Change-Number: 82010 Gerrit-PatchSet: 16 Gerrit-Owner: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Brandon Weeks <bweeks(a)google.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Federico Amedeo Izzo <federico(a)izzo.pro> Gerrit-Comment-Date: Mon, 27 May 2024 14:07:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Federico Amedeo Izzo <federico(a)izzo.pro> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: tree: Use <stdio.h> for snprintf
by Elyes Haouas (Code Review) 27 May '24

27 May '24

Attention is currently required from: Alexander Couzens, Andrey Petrov, Arthur Heymans, Caveh Jalali, Christian Walter, Cliff Huang, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Forest Mittelberg, Hung-Te Lin, Jakub Czapiga, Jason Nien, Johnny Lin, Jonathan Zhang, Julius Werner, Jérémy Compostella, Kapil Porwal, Lance Zhao, Lean Sheng Tan, Martin Roth, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Piotr Król, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Yidi Lin, Yu-Ping Wu. Hello Alexander Couzens, Andrey Petrov, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Forest Mittelberg, Hung-Te Lin, Jakub Czapiga, Jason Nien, Johnny Lin, Jonathan Zhang, Julius Werner, Jérémy Compostella, Kapil Porwal, Lance Zhao, Lean Sheng Tan, Martin Roth, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Piotr Król, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82665?usp=email to look at the new patch set (#4). Change subject: tree: Use <stdio.h> for snprintf ...................................................................... tree: Use <stdio.h> for snprintf <stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/acpi/acpigen.c M src/acpi/acpigen_dptf.c M src/acpi/acpigen_usb.c M src/acpi/device.c M src/arch/arm64/smbios.c M src/arch/x86/smbios.c M src/console/vsprintf.c M src/cpu/x86/smm/smm_module_loader.c M src/device/device_util.c M src/device/dram/ddr2.c M src/device/pci_rom.c M src/drivers/acpi/thermal_zone/thermal_zone.c M src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c M src/drivers/generic/gpio_keys/gpio_keys.c M src/drivers/i2c/cs35l53/cs35l53.c M src/drivers/i2c/generic/generic.c M src/drivers/i2c/gpiomux/bus/bus.c M src/drivers/i2c/gpiomux/mux/mux.c M src/drivers/i2c/hid/hid.c M src/drivers/i2c/max98390/max98390.c M src/drivers/i2c/max98396/max98396.c M src/drivers/i2c/rt1011/rt1011.c M src/drivers/i2c/rt5645/rt5645.c M src/drivers/i2c/sx9310/sx9310.c M src/drivers/i2c/sx9324/sx9324.c M src/drivers/i2c/sx9360/sx9360.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/fsp2_0/util.c M src/drivers/intel/gma/acpi.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/pmc_mux/conn/conn.c M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/nxp/uwb/uwb.c M src/drivers/ocp/dmi/smbios.c M src/drivers/spi/acpi/acpi.c M src/drivers/uart/acpi/acpi.c M src/drivers/usb/hub/acpi.c M src/drivers/usb/pci_xhci/pci_xhci.c M src/drivers/wifi/generic/acpi.c M src/ec/clevo/it5570e/ssdt.c M src/ec/google/chromeec/audio_codec/audio_codec.c M src/ec/google/chromeec/ec_dptf_helpers.c M src/ec/google/chromeec/ec_smbios.c M src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c M src/ec/google/chromeec/mux/conn/conn.c M src/ec/lenovo/h8/h8.c M src/ec/lenovo/h8/ssdt.c M src/include/stdio.h M src/include/string.h M src/lib/device_tree.c M src/lib/fit.c M src/lib/smbios.c M src/lib/smbios_defaults.c M src/lib/ux_locales.c M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kukui/mainboard.c M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/poppy/variants/nautilus/mainboard.c M src/mainboard/google/poppy/variants/rammus/mainboard.c M src/mainboard/google/reef/mainboard.c M src/mainboard/google/rex/mainboard.c M src/mainboard/google/volteer/mainboard.c M src/mainboard/ibm/sbp1/ramstage.c M src/mainboard/intel/adlrvp/mainboard.c M src/mainboard/intel/mtlrvp/mainboard.c M src/mainboard/intel/tglrvp/mainboard.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/lenovo/s230u/mainboard.c M src/mainboard/ocp/deltalake/ramstage.c M src/mainboard/pcengines/apu2/mainboard.c M src/mainboard/prodrive/atlas/mainboard.c M src/mainboard/prodrive/atlas/vpd.c M src/mainboard/prodrive/hermes/mainboard.c M src/mainboard/prodrive/hermes/smbios.c M src/security/tpm/tspi/crtm.c M src/soc/cavium/cn81xx/soc.c M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/xeon_sp/acpi.c M src/soc/mediatek/common/display.c M src/southbridge/intel/common/rcba_pirq.c M src/southbridge/intel/lynxpoint/acpi.c M src/superio/common/ssdt.c M src/vendorcode/amd/opensil/genoa_poc/ramstage.c M src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-config.c M src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-test.c M src/vendorcode/cavium/bdk/libbdk-hal/bdk-config.c M src/vendorcode/cavium/bdk/libbdk-hal/device/bdk-device.c M src/vendorcode/cavium/bdk/libdram/dram-init-ddr3.c M src/vendorcode/google/smbios.c M tests/lib/lzma-test.c M tests/stubs/die.c M util/cbfstool/flashmap/kv_pair.c 94 files changed, 94 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/82665/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/82665?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa 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[XS] Change in coreboot[main]: libpayload/libc: Include region device APIs
by Kapil Porwal (Code Review) 27 May '24

27 May '24

Attention is currently required from: Eran Mitrani, Kapil Porwal. Hello Dinesh Gehlot, Eran Mitrani, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82659?usp=email to look at the new patch set (#2). Change subject: libpayload/libc: Include region device APIs ...................................................................... libpayload/libc: Include region device APIs Include region.c & mem_pool.c to use below APIs in depthcharge - - rdev_readat - rdev_chain - rdev_eraseat - rdev_writeat - mmap_helper_rdev_mmap - mmap_helper_rdev_munmap BUG=b:305902595 TEST=Verify region device in depthcharge on Screebo Change-Id: I92a2504fcbf9035bdf3435c83eb6d5512c07a692 Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> --- M payloads/libpayload/libc/Makefile.mk 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/82659/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82659?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92a2504fcbf9035bdf3435c83eb6d5512c07a692 Gerrit-Change-Number: 82659 Gerrit-PatchSet: 2 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>

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[XS] Change in coreboot[main]: tree: Remove unused <stdarg.h>
by Maximilian Brune (Code Review) 27 May '24

27 May '24

Attention is currently required from: Elyes Haouas, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Maximilian Brune has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/82664?usp=email ) Change subject: tree: Remove unused <stdarg.h> ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82664?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07ffc65b7feefb8ec4ab8dd268113f9ed8d24685 Gerrit-Change-Number: 82664 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Mon, 27 May 2024 13:16:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: ec/dasharo/ec: add support for Dasharo EC
by Maciej Pijanowski (Code Review) 27 May '24

27 May '24

Attention is currently required from: Michał Kopeć, Michał Żygowski. Maciej Pijanowski has posted comments on this change by Michał Kopeć. ( https://review.coreboot.org/c/coreboot/+/82671?usp=email ) Change subject: ec/dasharo/ec: add support for Dasharo EC ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82671/comment/56514ca0_739029b4?us… : PS1, Line 11: Should we mention that: 1. We follow a similar "process" as in: https://review.coreboot.org/c/coreboot/+/52390/3 2. Which was the tree revision we used as a copy? It might be useful in the future? -- To view, visit https://review.coreboot.org/c/coreboot/+/82671?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7c3d9413488026548514963eb78accc28e41e06 Gerrit-Change-Number: 82671 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Comment-Date: Mon, 27 May 2024 13:09:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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