coreboot-gerrit May 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/intel/mtl/acpi/gpio.asl: fix missing gpio.h include
by Michał Kopeć (Code Review) 27 May '24

27 May '24

Michał Kopeć has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82674?usp=email ) Change subject: soc/intel/mtl/acpi/gpio.asl: fix missing gpio.h include ...................................................................... soc/intel/mtl/acpi/gpio.asl: fix missing gpio.h include This change fixes building NovaCustom V540TU, which previously errored out due to missing MISCCFG_GPIO_PM_CONFIG_BITS definition. Replace soc/gpio_defs.h with gpio.h which includes everything we need, same as it was done for ADL in change 71266, and other SoCs. TEST=Build and boot NovaCustom V540TU Change-Id: I52a495f696258fc63752dd8e66e318e144bb768e Signed-off-by: Michał Kopeć <michal.kopec(a)3mdeb.com> --- M src/soc/intel/meteorlake/acpi/gpio.asl 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/82674/1 diff --git a/src/soc/intel/meteorlake/acpi/gpio.asl b/src/soc/intel/meteorlake/acpi/gpio.asl index 440ee75..effc4d2 100644 --- a/src/soc/intel/meteorlake/acpi/gpio.asl +++ b/src/soc/intel/meteorlake/acpi/gpio.asl @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <soc/gpio_defs.h> +#include <gpio.h> #include <soc/intel/common/acpi/gpio.asl> #include <soc/intel/common/block/acpi/acpi/gpio_op.asl> #include <soc/irq.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/82674?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52a495f696258fc63752dd8e66e318e144bb768e Gerrit-Change-Number: 82674 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Kopeć <michal.kopec(a)3mdeb.com>

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[M] Change in coreboot[main]: tree: Use <stdio.h> for snprintf
by Elyes Haouas (Code Review) 27 May '24

27 May '24

Attention is currently required from: Alexander Couzens, Andrey Petrov, Arthur Heymans, Caveh Jalali, Christian Walter, Cliff Huang, Dinesh Gehlot, Elyes Haouas, Eran Mitrani, Forest Mittelberg, Hung-Te Lin, Jakub Czapiga, Jason Nien, Johnny Lin, Jonathan Zhang, Julius Werner, Jérémy Compostella, Kapil Porwal, Lance Zhao, Lean Sheng Tan, Martin Roth, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Piotr Król, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Yidi Lin, Yu-Ping Wu. Hello Alexander Couzens, Andrey Petrov, Angel Pons, Arthur Heymans, Caveh Jalali, Christian Walter, Cliff Huang, Dinesh Gehlot, Eran Mitrani, Forest Mittelberg, Hung-Te Lin, Jakub Czapiga, Jason Nien, Johnny Lin, Jonathan Zhang, Julius Werner, Jérémy Compostella, Kapil Porwal, Lance Zhao, Lean Sheng Tan, Martin Roth, Michał Żygowski, Nick Vaccaro, Patrick Rudolph, Piotr Król, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, Tim Chu, Tim Wawrzynczak, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82665?usp=email to look at the new patch set (#3). Change subject: tree: Use <stdio.h> for snprintf ...................................................................... tree: Use <stdio.h> for snprintf <stdio.h> header is used for input/output operations (such as printf, scanf, fopen, etc.). Although some input/output functions can manipulate strings, they do not need to directly include <string.h> because they are declared independently. Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/acpi/acpigen.c M src/acpi/acpigen_dptf.c M src/acpi/acpigen_usb.c M src/acpi/device.c M src/arch/arm64/smbios.c M src/arch/x86/smbios.c M src/console/vsprintf.c M src/cpu/x86/smm/smm_module_loader.c M src/device/device_util.c M src/device/dram/ddr2.c M src/device/pci_rom.c M src/drivers/acpi/thermal_zone/thermal_zone.c M src/drivers/amd/i2s_machine_dev/i2s_machine_dev.c M src/drivers/generic/gpio_keys/gpio_keys.c M src/drivers/i2c/cs35l53/cs35l53.c M src/drivers/i2c/generic/generic.c M src/drivers/i2c/gpiomux/bus/bus.c M src/drivers/i2c/gpiomux/mux/mux.c M src/drivers/i2c/hid/hid.c M src/drivers/i2c/max98390/max98390.c M src/drivers/i2c/max98396/max98396.c M src/drivers/i2c/rt1011/rt1011.c M src/drivers/i2c/rt5645/rt5645.c M src/drivers/i2c/sx9310/sx9310.c M src/drivers/i2c/sx9324/sx9324.c M src/drivers/i2c/sx9360/sx9360.c M src/drivers/intel/dptf/dptf.c M src/drivers/intel/fsp2_0/util.c M src/drivers/intel/gma/acpi.c M src/drivers/intel/mipi_camera/camera.c M src/drivers/intel/pmc_mux/conn/conn.c M src/drivers/intel/usb4/retimer/retimer.c M src/drivers/nxp/uwb/uwb.c M src/drivers/ocp/dmi/smbios.c M src/drivers/spi/acpi/acpi.c M src/drivers/uart/acpi/acpi.c M src/drivers/usb/hub/acpi.c M src/drivers/usb/pci_xhci/pci_xhci.c M src/drivers/wifi/generic/acpi.c M src/ec/clevo/it5570e/ssdt.c M src/ec/google/chromeec/audio_codec/audio_codec.c M src/ec/google/chromeec/ec_dptf_helpers.c M src/ec/google/chromeec/ec_smbios.c M src/ec/google/chromeec/i2c_tunnel/i2c_tunnel.c M src/ec/google/chromeec/mux/conn/conn.c M src/ec/lenovo/h8/h8.c M src/ec/lenovo/h8/ssdt.c M src/include/stdio.h M src/include/string.h M src/lib/device_tree.c M src/lib/fit.c M src/lib/smbios.c M src/lib/smbios_defaults.c M src/lib/ux_locales.c M src/mainboard/google/fizz/mainboard.c M src/mainboard/google/gru/sdram_configs.c M src/mainboard/google/kahlee/mainboard.c M src/mainboard/google/kukui/mainboard.c M src/mainboard/google/poppy/variants/nami/mainboard.c M src/mainboard/google/poppy/variants/nautilus/mainboard.c M src/mainboard/google/poppy/variants/rammus/mainboard.c M src/mainboard/google/reef/mainboard.c M src/mainboard/google/rex/mainboard.c M src/mainboard/google/volteer/mainboard.c M src/mainboard/ibm/sbp1/ramstage.c M src/mainboard/intel/adlrvp/mainboard.c M src/mainboard/intel/mtlrvp/mainboard.c M src/mainboard/intel/tglrvp/mainboard.c M src/mainboard/kontron/986lcd-m/mainboard.c M src/mainboard/lenovo/s230u/mainboard.c M src/mainboard/ocp/deltalake/ramstage.c M src/mainboard/pcengines/apu2/mainboard.c M src/mainboard/prodrive/atlas/mainboard.c M src/mainboard/prodrive/atlas/vpd.c M src/mainboard/prodrive/hermes/mainboard.c M src/mainboard/prodrive/hermes/smbios.c M src/security/tpm/tspi/crtm.c M src/soc/cavium/cn81xx/soc.c M src/soc/intel/common/block/acpi/cpu_hybrid.c M src/soc/intel/xeon_sp/acpi.c M src/soc/mediatek/common/display.c M src/southbridge/intel/common/rcba_pirq.c M src/southbridge/intel/lynxpoint/acpi.c M src/superio/common/ssdt.c M src/vendorcode/amd/opensil/genoa_poc/ramstage.c M src/vendorcode/cavium/bdk/libbdk-dram/bdk-dram-config.c M src/vendorcode/google/smbios.c M tests/lib/lzma-test.c M tests/stubs/die.c M util/cbfstool/flashmap/kv_pair.c 90 files changed, 90 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/82665/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/82665?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibe2a4ff6f68843a6d99cfdfe182cf2dd922802aa Gerrit-Change-Number: 82665 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: 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[M] Change in coreboot[main]: mb/google/ovis/var/deku: Set PsysPL2 value to 178W
by Felix Held (Code Review) 27 May '24

27 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82200?usp=email ) Change subject: mb/google/ovis/var/deku: Set PsysPL2 value to 178W ...................................................................... mb/google/ovis/var/deku: Set PsysPL2 value to 178W Adjust setting as recommended by power team. Add ramstage.c in Makefile.inc to set psys_pl2_watts in variant_devtree_update(). Also copy CPU power limit values from ovis baseboard. BUG=b:320410462 BRANCH=firmware-rex-15709.B TEST=FSP debug emerge-ovis coreboot intelfsp check overrides setting [INFO] CPU PsysPL2 = 178 Watts [INFO] Overriding PsysPL2 (178) [INFO] Overriding power limits PL1 (mW) (19000,28000) PL2 (mW) (64000, 64000) PL4 (W) (120) Change-Id: I9ce3a8f843a87e81d404778aaf250b876b6801eb Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82200 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Derek Huang <derekhuang(a)google.com> --- M src/mainboard/google/rex/variants/deku/Makefile.mk M src/mainboard/google/rex/variants/deku/overridetree.cb A src/mainboard/google/rex/variants/deku/ramstage.c 3 files changed, 52 insertions(+), 0 deletions(-) Approvals: Sumeet R Pawnikar: Looks good to me, approved Derek Huang: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/deku/Makefile.mk b/src/mainboard/google/rex/variants/deku/Makefile.mk index 91f031e..090dd5b 100644 --- a/src/mainboard/google/rex/variants/deku/Makefile.mk +++ b/src/mainboard/google/rex/variants/deku/Makefile.mk @@ -3,3 +3,4 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index 496af45..fcacbea 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -64,6 +64,7 @@ }" register "psys_pmax_watts" = "180" + register "psys_pl2_watts" = "178" # As per doc 640982, Intel MTL-U 28W CPU supports FVM on GT and SA # The ICC Limit is represented in 1/4 A increments, i.e., a value of 400 = 100A diff --git a/src/mainboard/google/rex/variants/deku/ramstage.c b/src/mainboard/google/rex/variants/deku/ramstage.c new file mode 100644 index 0000000..7cb324d --- /dev/null +++ b/src/mainboard/google/rex/variants/deku/ramstage.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> +#include <chip.h> +#include <intelblocks/power_limit.h> + +/* + * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), + * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) + * Following values are for performance config as per document #640982 + */ +const struct cpu_tdp_power_limits variant_limits[] = { + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_1, + .cpu_tdp = 28, + .pl1_min_power = 19000, + .pl1_max_power = 28000, + .pl2_min_power = 64000, + .pl2_max_power = 64000, + .pl4_power = 120000 + }, + { + .mch_id = PCI_DID_INTEL_MTL_P_ID_3, + .cpu_tdp = 28, + .pl1_min_power = 19000, + .pl1_max_power = 28000, + .pl2_min_power = 64000, + .pl2_max_power = 64000, + .pl4_power = 120000 + }, +}; + +void variant_devtree_update(void) +{ + struct soc_power_limits_config *soc_config; + struct soc_intel_meteorlake_config *config = config_of_soc(); + + soc_config = variant_get_soc_power_limit_config(); + if (soc_config == NULL) + return; + + if (config->psys_pl2_watts) { + soc_config->tdp_psyspl2 = config->psys_pl2_watts; + printk(BIOS_INFO, "Overriding PsysPL2 (%u)\n", soc_config->tdp_psyspl2); + } + + const struct cpu_tdp_power_limits *limits = variant_limits; + size_t total_entries = ARRAY_SIZE(variant_limits); + variant_update_cpu_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/82200?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ce3a8f843a87e81d404778aaf250b876b6801eb Gerrit-Change-Number: 82200 Gerrit-PatchSet: 34 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/ovis/var/deku: Increase TDP PL1 value from 28 W to 33 W
by Felix Held (Code Review) 27 May '24

27 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82615?usp=email ) Change subject: mb/google/ovis/var/deku: Increase TDP PL1 value from 28 W to 33 W ...................................................................... mb/google/ovis/var/deku: Increase TDP PL1 value from 28 W to 33 W Adjust settings as recommended by thermal team. Set PL1 max value tdp_pl1_override from 28W to 33W. PL2, PL4 remain the same as CPU default. BUG=b:308704811 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot chromeos-bootimage built bootleg and verified test result by thermal team Change-Id: Iad0bca913496dda666ba9bcfe5f6fce1a6396692 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82615 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: Sumeet R Pawnikar: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index 8344e3b..496af45 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -30,6 +30,12 @@ # Temporary setting TCC of 105C = Tj max (110) - TCC_Offset (5) register "tcc_offset" = "5" + register "power_limits_config[MTL_P_682_482_CORE]" = "{ + .tdp_pl1_override = 33, + .tdp_pl2_override = 64, + .tdp_pl4 = 120, + }" + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, -- To view, visit https://review.coreboot.org/c/coreboot/+/82615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iad0bca913496dda666ba9bcfe5f6fce1a6396692 Gerrit-Change-Number: 82615 Gerrit-PatchSet: 3 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/ovis/var/deku: Set TCC_offset to 5
by Felix Held (Code Review) 27 May '24

27 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82614?usp=email ) Change subject: mb/google/ovis/var/deku: Set TCC_offset to 5 ...................................................................... mb/google/ovis/var/deku: Set TCC_offset to 5 Adjust settings as recommended by thermal team. Set tcc_offset value to 5 in devicetree. BUG=b:308704811 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot chromeos-bootimage built bootleg and verified test result by thermal team Change-Id: I30f54ae6017c54c91ff9b432bba0ebd5bfc65ab9 Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82614 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index 5e3f250..8344e3b 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -27,6 +27,9 @@ [DDI_PORT_4] = DDI_ENABLE_HPD, }" + # Temporary setting TCC of 105C = Tj max (110) - TCC_Offset (5) + register "tcc_offset" = "5" + register "serial_io_i2c_mode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoDisabled, [PchSerialIoIndexI2C1] = PchSerialIoDisabled, -- To view, visit https://review.coreboot.org/c/coreboot/+/82614?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I30f54ae6017c54c91ff9b432bba0ebd5bfc65ab9 Gerrit-Change-Number: 82614 Gerrit-PatchSet: 2 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/rex/var/deku: Update DPTF parameters
by Felix Held (Code Review) 27 May '24

27 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82434?usp=email ) Change subject: mb/google/rex/var/deku: Update DPTF parameters ...................................................................... mb/google/rex/var/deku: Update DPTF parameters Adjust settings as recommended by thermal team. Update DPTF parameters based on b:308704811#comment4. BUG=b:308704811 BRANCH=firmware-rex-15709.B TEST=emerge-ovis coreboot chromeos-bootimage built bootleg and verified test result by thermal team Change-Id: I710682771bd0679ae4b44dd43be68f60e8984b2e Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82434 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/rex/variants/deku/overridetree.cb 1 file changed, 34 insertions(+), 0 deletions(-) Approvals: Subrata Banik: Looks good to me, approved Sumeet R Pawnikar: Looks good to me, approved Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb index 775dbc7..5e3f250 100644 --- a/src/mainboard/google/rex/variants/deku/overridetree.cb +++ b/src/mainboard/google/rex/variants/deku/overridetree.cb @@ -70,6 +70,40 @@ device domain 0 on device ref dtt on chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DDR_SOC"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""IMVP_SOC"" + register "options.tsr[3].desc" = ""NVME"" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 65, 1000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + }" + + ## Power Limits Control + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 28000, + .max_power = 28000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 64000, + .max_power = 64000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + device generic 0 alias dptf_policy on end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/82434?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I710682771bd0679ae4b44dd43be68f60e8984b2e Gerrit-Change-Number: 82434 Gerrit-PatchSet: 7 Gerrit-Owner: Tony Huang <tony-huang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/asus/p8z77-m: Drop GPIO by I/O
by Keith Hui (Code Review) 27 May '24

27 May '24

Attention is currently required from: Fabian Groffen, Felix Held, Keith Hui. Keith Hui has posted comments on this change by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/75145?usp=email ) Change subject: mb/asus/p8z77-m: Drop GPIO by I/O ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > so this patch isn't necessary and shouldn't be submitted, right? […] Oh yeah right. I didn't set up a LPC generic decode for it. Silly me. -- To view, visit https://review.coreboot.org/c/coreboot/+/75145?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22654f3c77082bf163ab7000ec467ab7085a0534 Gerrit-Change-Number: 75145 Gerrit-PatchSet: 4 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Comment-Date: Mon, 27 May 2024 12:51:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: mb/asus/p8z77-m: Drop GPIO by I/O
by Felix Held (Code Review) 27 May '24

27 May '24

Attention is currently required from: Fabian Groffen, Keith Hui, Keith Hui. Felix Held has posted comments on this change by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/75145?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/asus/p8z77-m: Drop GPIO by I/O ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: > I finally tested on hardware. CB:81926 did fix the underlying issue. […] so this patch isn't necessary and shouldn't be submitted, right? on the block not working: haven't checked, but that might be due to a missing lpc decode range. haven't decode the magic value of gen1_dec; if that one is another io window, there are more of those lpc decode range registers -- To view, visit https://review.coreboot.org/c/coreboot/+/75145?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I22654f3c77082bf163ab7000ec467ab7085a0534 Gerrit-Change-Number: 75145 Gerrit-PatchSet: 4 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Comment-Date: Mon, 27 May 2024 12:48:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Keith Hui <buurin(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: security/memory_clear: fix wrong size of reserved memory range
by Felix Held (Code Review) 27 May '24

27 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82397?usp=email ) Change subject: security/memory_clear: fix wrong size of reserved memory range ...................................................................... security/memory_clear: fix wrong size of reserved memory range The code used to reserve MEMSET_PAE_PGTL_SIZE (20 KiB) for page used for clearing the memory above 4 GiB that was assumed to be 2 MiB page. memset_pae() checks only the alignment and not the size of this region, so no error was reported by it. In most cases this reserved memory in 2-4 MiB range, and because this range isn't usually used by coreboot (architectural stuff is located in lower 1 MiB, coreboot tables and ramstage are close to TOLUM and payload isn't yet loaded when the broken code is executed), it never caused any problems. Change MEMSET_PAE_PGTL_SIZE to MEMSET_PAE_VMEM_SIZE and fix wrong macro definition to reserve properly sized region. Change-Id: I0df15b0d1767196fe70be14d94428ccdf8dbd5d3 Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82397 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/security/memory/memory_clear.c 1 file changed, 2 insertions(+), 2 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Sergii Dmytruk: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 03c6f8b..996b1d3 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -6,8 +6,8 @@ #define memset_pae(a, b, c, d, e) 0 #define MEMSET_PAE_PGTL_ALIGN 0 #define MEMSET_PAE_PGTL_SIZE 0 -#define MEMSET_PAE_PGTL_SIZE 0 #define MEMSET_PAE_VMEM_ALIGN 0 +#define MEMSET_PAE_VMEM_SIZE 0 #endif #include <memrange.h> @@ -92,7 +92,7 @@ BM_MEM_TABLE); vmem_addr = get_free_memory_range(&mem, MEMSET_PAE_VMEM_ALIGN, - MEMSET_PAE_PGTL_SIZE); + MEMSET_PAE_VMEM_SIZE); printk(BIOS_SPEW, "%s: pgtbl at %p, virt memory at %p\n", __func__, (void *)pgtbl, (void *)vmem_addr); -- To view, visit https://review.coreboot.org/c/coreboot/+/82397?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0df15b0d1767196fe70be14d94428ccdf8dbd5d3 Gerrit-Change-Number: 82397 Gerrit-PatchSet: 2 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: acpi/acpi_apic;arch/x86/acpi: better document ACPI_NO_PCAT_8259 case
by Felix Held (Code Review) 27 May '24

27 May '24

Attention is currently required from: Cliff Huang, Eric Lai, Felix Held, Jérémy Compostella, Lance Zhao, Nico Huber, Tim Wawrzynczak. Hello Cliff Huang, Eric Lai, Jérémy Compostella, Lance Zhao, Nico Huber, Tim Wawrzynczak, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82643?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Code-Review+2 by Eric Lai, Code-Review+2 by Tim Wawrzynczak, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: acpi/acpi_apic;arch/x86/acpi: better document ACPI_NO_PCAT_8259 case ...................................................................... acpi/acpi_apic;arch/x86/acpi: better document ACPI_NO_PCAT_8259 case Both acpi_create_madt_sci_override and acpi_sci_int have special handling for the ACPI_NO_PCAT_8259 case, but those cases weren't exactly obvious, so add a comment with the reason for that. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ia6dcf59d5ab9226c61e9c4af95a73a07771b71d1 --- M src/acpi/acpi_apic.c M src/arch/x86/acpi.c 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/82643/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6dcf59d5ab9226c61e9c4af95a73a07771b71d1 Gerrit-Change-Number: 82643 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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coreboot-gerrit May 2024