coreboot-gerrit May 2024

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[M] Change in coreboot[main]: cpu/x86/pae/pgtbl.c: extract reusable code from memset_pae()
by Felix Held (Code Review) 29 May '24

29 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82249?usp=email ) Change subject: cpu/x86/pae/pgtbl.c: extract reusable code from memset_pae() ...................................................................... cpu/x86/pae/pgtbl.c: extract reusable code from memset_pae() Code dealing with PAE can be used outside of memset_pae(). This change extracts creation of identity mapped pagetables to init_pae_pagetables() and mapping of single 2 MiB map to pae_map_2M_page(). Both functions are exported in include/cpu/x86/pae.h to allow use outside of pgtbl.c. MEMSET_PAE_* macros were renamed to PAE_* since they no longer apply only to memset_pae(). Change-Id: I8aa80eb246ff0e77e1f51d71933d3d00ab75aaeb Signed-off-by: Krystian Hebel <krystian.hebel(a)3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82249 Reviewed-by: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/cpu/x86/pae/pgtbl.c M src/include/cpu/x86/pae.h M src/security/memory/memory_clear.c 3 files changed, 115 insertions(+), 50 deletions(-) Approvals: build bot (Jenkins): Verified Sergii Dmytruk: Looks good to me, approved diff --git a/src/cpu/x86/pae/pgtbl.c b/src/cpu/x86/pae/pgtbl.c index e1803aa..3df6122 100644 --- a/src/cpu/x86/pae/pgtbl.c +++ b/src/cpu/x86/pae/pgtbl.c @@ -101,6 +101,97 @@ } /* + * Prepare PAE pagetables that identity map the whole 32-bit address space using + * 2 MiB pages. The PAT are set to all cacheable, but MTRRs still apply. CR3 is + * loaded and PAE is enabled by this function. + * + * Requires a scratch memory for pagetables. + * + * @param pgtbl Where pagetables reside, must be 4 KiB aligned and 20 KiB in + * size. + * Content at physical address isn't preserved. + * @return 0 on success, 1 on error + */ +int init_pae_pagetables(void *pgtbl) +{ + struct pg_table *pgtbl_buf = (struct pg_table *)pgtbl; + struct pde *pd = pgtbl_buf->pd, *pdp = pgtbl_buf->pdp; + + printk(BIOS_DEBUG, "%s: Using address %p for page tables\n", + __func__, pgtbl_buf); + + /* Cover some basic error conditions */ + if (!IS_ALIGNED((uintptr_t)pgtbl_buf, s4KiB)) { + printk(BIOS_ERR, "%s: Invalid alignment\n", __func__); + return 1; + } + + paging_disable_pae(); + + /* Point the page directory pointers at the page directories. */ + memset(pgtbl_buf->pdp, 0, sizeof(pgtbl_buf->pdp)); + + pdp[0].addr_lo = ((uintptr_t)&pd[512*0]) | PDPTE_PRES; + pdp[1].addr_lo = ((uintptr_t)&pd[512*1]) | PDPTE_PRES; + pdp[2].addr_lo = ((uintptr_t)&pd[512*2]) | PDPTE_PRES; + pdp[3].addr_lo = ((uintptr_t)&pd[512*3]) | PDPTE_PRES; + + /* Identity map the whole 32-bit address space */ + for (size_t i = 0; i < 2048; i++) { + pd[i].addr_lo = (i << PDE_IDX_SHIFT) | PDE_PS | PDE_PRES | PDE_RW; + pd[i].addr_hi = 0; + } + + paging_enable_pae_cr3((uintptr_t)pdp); + + return 0; +} + +/* + * Map single 2 MiB page in pagetables created by init_pae_pagetables(). + * + * The function does not check if the page was already non identity mapped, + * this allows callers to reuse one page without having to explicitly unmap it + * between calls. + * + * @param pgtbl Where pagetables created by init_pae_pagetables() reside. + * Content at physical address is preserved except for single + * entry corresponding to vmem_addr. + * @param paddr Physical memory address to map. Function prints a warning if + * it isn't aligned to 2 MiB. + * @param vmem_addr Where the virtual non identity mapped page resides, must + * be at least 2 MiB in size. Function prints a warning if it + * isn't aligned to 2 MiB. + * Content at physical address is preserved. + * @return 0 on success, 1 on error + */ +void pae_map_2M_page(void *pgtbl, uint64_t paddr, void *vmem_addr) +{ + struct pg_table *pgtbl_buf = (struct pg_table *)pgtbl; + struct pde *pd; + + if (!IS_ALIGNED(paddr, s2MiB)) { + printk(BIOS_WARNING, "%s: Aligning physical address to 2MiB\n", + __func__); + paddr = ALIGN_DOWN(paddr, s2MiB); + } + + if (!IS_ALIGNED((uintptr_t)vmem_addr, s2MiB)) { + printk(BIOS_WARNING, "%s: Aligning virtual address to 2MiB\n", + __func__); + vmem_addr = (void *)ALIGN_DOWN((uintptr_t)vmem_addr, s2MiB); + } + + /* Map a page using PAE at virtual address vmem_addr. */ + pd = &pgtbl_buf->pd[((uintptr_t)vmem_addr) >> PDE_IDX_SHIFT]; + pd->addr_lo = paddr | PDE_PS | PDE_PRES | PDE_RW; + pd->addr_hi = paddr >> 32; + + /* Update page tables */ + asm volatile ("invlpg (%0)" :: "b"(vmem_addr) : "memory"); +} + +/* * Use PAE to map a page and then memset it with the pattern specified. * In order to use PAE pagetables for virtual addressing are set up and reloaded * on a 2MiB boundary. After the function is done, virtual addressing mode is @@ -130,22 +221,18 @@ int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl, void *vmem_addr) { - struct pg_table *pgtbl_buf = (struct pg_table *)pgtbl; ssize_t offset; + const uintptr_t pgtbl_s = (uintptr_t)pgtbl; + const uintptr_t pgtbl_e = pgtbl_s + sizeof(struct pg_table); printk(BIOS_DEBUG, "%s: Using virtual address %p as scratchpad\n", __func__, vmem_addr); - printk(BIOS_DEBUG, "%s: Using address %p for page tables\n", - __func__, pgtbl_buf); /* Cover some basic error conditions */ - if (!IS_ALIGNED((uintptr_t)pgtbl_buf, s4KiB) || - !IS_ALIGNED((uintptr_t)vmem_addr, s2MiB)) { + if (!IS_ALIGNED((uintptr_t)vmem_addr, s2MiB)) { printk(BIOS_ERR, "%s: Invalid alignment\n", __func__); return 1; } - const uintptr_t pgtbl_s = (uintptr_t)pgtbl_buf; - const uintptr_t pgtbl_e = pgtbl_s + sizeof(struct pg_table); if (OVERLAP(dest, dest + length, pgtbl_s, pgtbl_e)) { printk(BIOS_ERR, "%s: destination overlaps page tables\n", @@ -160,31 +247,12 @@ return 1; } - paging_disable_pae(); - - struct pde *pd = pgtbl_buf->pd, *pdp = pgtbl_buf->pdp; - /* Point the page directory pointers at the page directories. */ - memset(pgtbl_buf->pdp, 0, sizeof(pgtbl_buf->pdp)); - - pdp[0].addr_lo = ((uintptr_t)&pd[512*0]) | PDPTE_PRES; - pdp[1].addr_lo = ((uintptr_t)&pd[512*1]) | PDPTE_PRES; - pdp[2].addr_lo = ((uintptr_t)&pd[512*2]) | PDPTE_PRES; - pdp[3].addr_lo = ((uintptr_t)&pd[512*3]) | PDPTE_PRES; + if (init_pae_pagetables(pgtbl)) + return 1; offset = dest - ALIGN_DOWN(dest, s2MiB); dest = ALIGN_DOWN(dest, s2MiB); - /* Identity map the whole 32-bit address space */ - for (size_t i = 0; i < 2048; i++) { - pd[i].addr_lo = (i << PDE_IDX_SHIFT) | PDE_PS | PDE_PRES | PDE_RW; - pd[i].addr_hi = 0; - } - - /* Get pointer to PD that's not identity mapped */ - pd = &pgtbl_buf->pd[((uintptr_t)vmem_addr) >> PDE_IDX_SHIFT]; - - paging_enable_pae_cr3((uintptr_t)pdp); - do { const size_t len = MIN(length, s2MiB - offset); @@ -192,11 +260,7 @@ * Map a page using PAE at virtual address vmem_addr. * dest is already 2 MiB aligned. */ - pd->addr_lo = dest | PDE_PS | PDE_PRES | PDE_RW; - pd->addr_hi = dest >> 32; - - /* Update page tables */ - asm volatile ("invlpg (%0)" :: "b"(vmem_addr) : "memory"); + pae_map_2M_page(pgtbl, dest, vmem_addr); printk(BIOS_SPEW, "%s: Clearing %llx[%lx] - %zx\n", __func__, dest + offset, (uintptr_t)vmem_addr + offset, len); diff --git a/src/include/cpu/x86/pae.h b/src/include/cpu/x86/pae.h index d1cf734..e4b0a2c 100644 --- a/src/include/cpu/x86/pae.h +++ b/src/include/cpu/x86/pae.h @@ -35,11 +35,15 @@ * failure. */ int paging_enable_for_car(const char *pdpt_name, const char *pt_name); -/* To be used with memset_pae */ -#define MEMSET_PAE_VMEM_ALIGN (2 * MiB) -#define MEMSET_PAE_VMEM_SIZE (2 * MiB) -#define MEMSET_PAE_PGTL_ALIGN (4 * KiB) -#define MEMSET_PAE_PGTL_SIZE (20 * KiB) +/* To be used with memset_pae and pae_map_2M_page */ +#define PAE_VMEM_ALIGN (2 * MiB) +#define PAE_VMEM_SIZE (2 * MiB) +#define PAE_PGTL_ALIGN (4 * KiB) +#define PAE_PGTL_SIZE (20 * KiB) + +int init_pae_pagetables(void *pgtbl); + +void pae_map_2M_page(void *pgtbl, uint64_t paddr, void *vmem_addr); int memset_pae(uint64_t dest, unsigned char pat, uint64_t length, void *pgtbl, void *vmem_addr); diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 996b1d3..9af3205 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -4,10 +4,10 @@ #include <cpu/x86/pae.h> #else #define memset_pae(a, b, c, d, e) 0 -#define MEMSET_PAE_PGTL_ALIGN 0 -#define MEMSET_PAE_PGTL_SIZE 0 -#define MEMSET_PAE_VMEM_ALIGN 0 -#define MEMSET_PAE_VMEM_SIZE 0 +#define PAE_PGTL_ALIGN 0 +#define PAE_PGTL_SIZE 0 +#define PAE_VMEM_ALIGN 0 +#define PAE_VMEM_SIZE 0 #endif #include <memrange.h> @@ -84,15 +84,12 @@ if (ENV_X86) { /* Find space for PAE enabled memset */ - pgtbl = get_free_memory_range(&mem, MEMSET_PAE_PGTL_ALIGN, - MEMSET_PAE_PGTL_SIZE); + pgtbl = get_free_memory_range(&mem, PAE_PGTL_ALIGN, PAE_PGTL_SIZE); /* Don't touch page tables while clearing */ - memranges_insert(&mem, pgtbl, MEMSET_PAE_PGTL_SIZE, - BM_MEM_TABLE); + memranges_insert(&mem, pgtbl, PAE_PGTL_SIZE, BM_MEM_TABLE); - vmem_addr = get_free_memory_range(&mem, MEMSET_PAE_VMEM_ALIGN, - MEMSET_PAE_VMEM_SIZE); + vmem_addr = get_free_memory_range(&mem, PAE_VMEM_ALIGN, PAE_VMEM_SIZE); printk(BIOS_SPEW, "%s: pgtbl at %p, virt memory at %p\n", __func__, (void *)pgtbl, (void *)vmem_addr); @@ -128,9 +125,9 @@ if (ENV_X86) { /* Clear previously skipped memory reserved for pagetables */ printk(BIOS_DEBUG, "%s: Clearing DRAM %016lx-%016lx\n", - __func__, pgtbl, pgtbl + MEMSET_PAE_PGTL_SIZE); + __func__, pgtbl, pgtbl + PAE_PGTL_SIZE); - memset((void *)pgtbl, 0, MEMSET_PAE_PGTL_SIZE); + memset((void *)pgtbl, 0, PAE_PGTL_SIZE); } memranges_teardown(&mem); -- To view, visit https://review.coreboot.org/c/coreboot/+/82249?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8aa80eb246ff0e77e1f51d71933d3d00ab75aaeb Gerrit-Change-Number: 82249 Gerrit-PatchSet: 4 Gerrit-Owner: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/sundance: Add WWAN power off sequence
by Felix Held (Code Review) 29 May '24

29 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82683?usp=email ) Change subject: mb/google/nissa/var/sundance: Add WWAN power off sequence ...................................................................... mb/google/nissa/var/sundance: Add WWAN power off sequence Sundance support FM101 WWAN, use wwan_power.asl to handle the power off sequence BUG=b:343139385 TEST=Build and boot on sundance Change-Id: I82085172db370ab5a6c0f77afe6042c53b89e43e Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82683 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/sundance/include/variant/gpio.h 2 files changed, 5 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index fcc2e63..366d2dd 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -413,6 +413,7 @@ config BOARD_GOOGLE_SUNDANCE select BOARD_GOOGLE_BASEBOARD_NISSA select DRIVERS_GENERIC_GPIO_KEYS + select HAVE_WWAN_POWER_SEQUENCE config BOARD_GOOGLE_PUJJOGA select BOARD_GOOGLE_BASEBOARD_NISSA diff --git a/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h b/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h index c4fe342..c96b01f 100644 --- a/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/sundance/include/variant/gpio.h @@ -5,4 +5,8 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_D6 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 + #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/82683?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I82085172db370ab5a6c0f77afe6042c53b89e43e Gerrit-Change-Number: 82683 Gerrit-PatchSet: 2 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/nissa/var/pujjoga: Update touchscreen IC settings
by Felix Held (Code Review) 29 May '24

29 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82427?usp=email ) Change subject: mb/google/nissa/var/pujjoga: Update touchscreen IC settings ...................................................................... mb/google/nissa/var/pujjoga: Update touchscreen IC settings Modify the Goodix touchscreen from new vendor and remove 3 unused touchscreens. According to the information provided by the key-part team. BUG=b:340689681 TEST=Build and check Goodix touchscreen can work. Change-Id: I1e6349e80431aadf27cd72b8439b01f95348071d Signed-off-by: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82427 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/pujjoga/overridetree.cb 1 file changed, 7 insertions(+), 40 deletions(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb index 2804e16..5641b06 100644 --- a/src/mainboard/google/brya/variants/pujjoga/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjoga/overridetree.cb @@ -146,53 +146,20 @@ device domain 0 on device ref i2c1 on chip drivers/i2c/hid - register "generic.hid" = ""ELAN901C"" - register "generic.desc" = ""ELAN Touchscreen"" + register "generic.hid" = ""GDIX0000"" + register "generic.desc" = ""Goodix Touchscreen"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" register "generic.detect" = "1" - register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "20" - register "generic.reset_off_delay_ms" = "2" - register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_delay_ms" = "280" - register "generic.stop_off_delay_ms" = "2" register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 10 on end - end - chip drivers/i2c/hid - register "generic.hid" = ""PARA3406"" - register "generic.desc" = ""Parade Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.detect" = "1" + register "generic.enable_delay_ms" = "20" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "20" - register "generic.reset_off_delay_ms" = "2" + register "generic.reset_delay_ms" = "180" + register "generic.reset_off_delay_ms" = "3" register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)" - register "generic.stop_delay_ms" = "280" - register "generic.stop_off_delay_ms" = "2" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "1" + register "generic.stop_off_delay_ms" = "1" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 24 on end - end - chip drivers/i2c/hid - register "generic.hid" = ""GTCH7503"" - register "generic.desc" = ""G2TOUCH Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)" - register "generic.detect" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)" - register "generic.reset_delay_ms" = "50" - register "generic.enable_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)" - register "generic.enable_delay_ms" = "1" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 40 on end + device i2c 5d on end end chip drivers/generic/gpio_keys register "name" = ""PENH"" -- To view, visit https://review.coreboot.org/c/coreboot/+/82427?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1e6349e80431aadf27cd72b8439b01f95348071d Gerrit-Change-Number: 82427 Gerrit-PatchSet: 14 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jerry2 Huang <jerry2.huang(a)lcfc.corp-partner.google.com> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/sundance: Update eMMC DLL settings
by Felix Held (Code Review) 29 May '24

29 May '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/82602?usp=email ) Change subject: mb/google/nissa/var/sundance: Update eMMC DLL settings ...................................................................... mb/google/nissa/var/sundance: Update eMMC DLL settings Currently Samsung eMMC (KLMBG2JETD-B041) can't power on to OS nomally. According to Intel provides eMMC DLL delay patch that tuning on each Sundance different eMMC system to modify some system can't boot to OS problem. BUG=b:342057438 TEST=Build and check each SKU eMMC can work. Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57 Signed-off-by: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82602 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/sundance/overridetree.cb 1 file changed, 45 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/sundance/overridetree.cb b/src/mainboard/google/brya/variants/sundance/overridetree.cb index 2f944d4..b4c7b5e 100644 --- a/src/mainboard/google/brya/variants/sundance/overridetree.cb +++ b/src/mainboard/google/brya/variants/sundance/overridetree.cb @@ -9,6 +9,51 @@ register "sagv" = "SaGv_Enabled" + # EMMC Tx CMD Delay + # Refer to EDS-Vol2-42.3.7. + # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39, total 625ps. + # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39, total 625ps. + register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-42.3.8. + # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78, total 465ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79, total 465ps. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x909" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-42.3.9. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79, total 3500ps. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78, total 5250ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79, total 5000ps. + # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79, total 5000ps. + register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C2A2828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-42.3.10. + # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119, total 3500ps. + # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78, total 3375ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119, total 3250ps. + # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119, total 3375ps. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C1B1A1B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-42.3.12. + # [17:16] stands for Rx Clock before Output Buffer, + # 00: Rx clock after output buffer, + # 01: Rx clock before output buffer, + # 10: Automatic selection based on working mode. + # 11: Reserved + # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39, total 0ps. + # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79, total 5000ps. + register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x10028" + + # EMMC Rx Strobe Delay + # Refer to EDS-Vol2-42.3.11. + # [14:8] Rx Strobe Delay DLL 1 (HS400 Mode), each 125ps, range: 0 - 39, total 2625ps. + # [6:0] Rx Strobe Delay DLL 2 (HS400 Mode), each 125ps, range: 0 - 39, total 2625ps. + register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x11515" + # SOC Aux orientation override: # This is a bitfield that corresponds to up to 4 TCSS ports. # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. -- To view, visit https://review.coreboot.org/c/coreboot/+/82602?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29d4305bbe5f91d822d947cae942b654e80a8a57 Gerrit-Change-Number: 82602 Gerrit-PatchSet: 20 Gerrit-Owner: Roger Wang <roger2.wang(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-CC: Varshit Pandya <15mece14(a)nirmauni.ac.in>

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[M] Change in coreboot[main]: mb/razer/blade_stealth_kbl: Add H3Q variant
by Reagan (Code Review) 29 May '24

29 May '24

Attention is currently required from: Felix Singer, Nico Huber, Paul Menzel. Hello Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82506?usp=email to look at the new patch set (#9). Change subject: mb/razer/blade_stealth_kbl: Add H3Q variant ...................................................................... mb/razer/blade_stealth_kbl: Add H3Q variant The Razer Blade Stealth Kaby Lake has 2 variants. One is the H2U variant, as originally committed, with the SKU number RZ09-01962, also known as the 2016 model, and the H3Q model with SKU numbers RZ09-01963 and RZ09-01964, known as the Mid 2017 model. This commit adds support for the H3Q model. With respect to coreboot, there are few known differences: 1. Only the H2U has TPM. 2. The USB ports are different. 3. The screen size (and therefore VBIOS Table) is different. 4. The hda_verb is very slightly different. Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4 Signed-off-by: Reagan Bohan <xbjfk.github(a)gmail.com> --- M src/mainboard/razer/blade_stealth_kbl/Kconfig M src/mainboard/razer/blade_stealth_kbl/Kconfig.name M src/mainboard/razer/blade_stealth_kbl/Makefile.mk M src/mainboard/razer/blade_stealth_kbl/board_info.txt M src/mainboard/razer/blade_stealth_kbl/devicetree.cb A src/mainboard/razer/blade_stealth_kbl/variants/h2u/board_info.txt R src/mainboard/razer/blade_stealth_kbl/variants/h2u/hda_verb.c A src/mainboard/razer/blade_stealth_kbl/variants/h2u/overridetree.cb A src/mainboard/razer/blade_stealth_kbl/variants/h3q/board_info.txt C src/mainboard/razer/blade_stealth_kbl/variants/h3q/hda_verb.c A src/mainboard/razer/blade_stealth_kbl/variants/h3q/overridetree.cb 11 files changed, 114 insertions(+), 46 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/82506/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/82506?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4 Gerrit-Change-Number: 82506 Gerrit-PatchSet: 9 Gerrit-Owner: Reagan <xbjfk.github(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: util/smmstoretool: explain what happens when no store is found
by Sergii Dmytruk (Code Review) 29 May '24

29 May '24

Attention is currently required from: Maciej Pijanowski. Sergii Dmytruk has posted comments on this change by Maciej Pijanowski. ( https://review.coreboot.org/c/coreboot/+/82692?usp=email ) Change subject: util/smmstoretool: explain what happens when no store is found ...................................................................... Patch Set 2: (1 comment) File util/smmstoretool/storage.c: https://review.coreboot.org/c/coreboot/+/82692/comment/b3fab015_1401cebd?us… : PS2, Line 53: fprintf(stderr, : "Variable store has not been found in the binary and will " : "be initialized now.\nIt is expected if release binary is " : "used, as variable store normally is initialized on the " : "first boot of the platform.\n"); I'd format the message differently (also somewhat updated it, e.g. "binary" was too generic): ```suggestion fprintf(stderr, "\nThe variable store has not been found in the ROM image\n" "and is about to be initialized. This situation is normal\n" "for a release image, as the variable store is usually\n" "initialized on the first boot of the platform.\n\n"); ``` I just don't like unusually long strings in the output and long sequence of ungrouped sentences are hard to read as well (e.g. like `flashrom` does), this version produces the following output: ``` No firmware volume header present No valid firmware volume was found The variable store has not been found in the ROM image and is about to be initialized. This situation is normal for a release image, as the variable store is usually initialized on the first boot of the platform. Successfully created variable store in "coreboot.rom" ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/82692?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa2678f5ae7c243811484c0567ced97ae0b3fc0a Gerrit-Change-Number: 82692 Gerrit-PatchSet: 2 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 29 May 2024 12:25:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/razer/blade_stealth_kbl: add panel_cfg
by Reagan (Code Review) 29 May '24

29 May '24

Attention is currently required from: Nico Huber, Paul Menzel. Reagan has posted comments on this change by Reagan. ( https://review.coreboot.org/c/coreboot/+/82458?usp=email ) Change subject: mb/razer/blade_stealth_kbl: add panel_cfg ...................................................................... Patch Set 14: (1 comment) File src/mainboard/razer/blade_stealth_kbl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/82458/comment/26c98a58_66d83f9d?us… : PS13, Line 163: .backlight_off_delay_ms = 5000, /* T12 */ > Alas, the VBT values are not in *ms*. I think it's 1/10th of a ms (most […] Done. You are right, it is in 100us. At src/soc/intel/skylake/graphics.c, the ms number is multiplied by 10. Annoyingly, `intel_reg` does not know these registers exist on Gen7+ - I had to manually enter the register address. I also checked the stock firmware, and interestingly the registers are the same as on the doc. Additionally, to get the same register values as the stock firmware `down_delay_ms` would need to be 50 and `cycle_delay_ms` 500. Why could this be, despite all VBIOS tables from the stock firmware having the values I used? -- To view, visit https://review.coreboot.org/c/coreboot/+/82458?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4c8b26ffb7a70d08655986084a714206d9d0c96a Gerrit-Change-Number: 82458 Gerrit-PatchSet: 14 Gerrit-Owner: Reagan <xbjfk.github(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 29 May 2024 12:22:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de>

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[XS] Change in coreboot[main]: tree: Remove duplicated <arch/mmio.h>
by Elyes Haouas (Code Review) 29 May '24

29 May '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82693?usp=email ) Change subject: tree: Remove duplicated <arch/mmio.h> ...................................................................... tree: Remove duplicated <arch/mmio.h> <device/mmio.h> is supposed to chain-include <soc/gpio.h> Change-Id: I08f7480650b42df1613994146a026bd1e12dbf66 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/soc/sifive/fu740/gpio.c M src/soc/sifive/fu740/sdram.c 2 files changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/82693/1 diff --git a/src/soc/sifive/fu740/gpio.c b/src/soc/sifive/fu740/gpio.c index d5576f2..21bdb89 100644 --- a/src/soc/sifive/fu740/gpio.c +++ b/src/soc/sifive/fu740/gpio.c @@ -3,7 +3,6 @@ #include <soc/addressmap.h> #include <soc/gpio.h> #include <stdint.h> -#include <arch/mmio.h> #include <assert.h> #include <device/mmio.h> #include <gpio.h> diff --git a/src/soc/sifive/fu740/sdram.c b/src/soc/sifive/fu740/sdram.c index 167d5a4..61dbb2e 100644 --- a/src/soc/sifive/fu740/sdram.c +++ b/src/soc/sifive/fu740/sdram.c @@ -5,7 +5,6 @@ #ifndef _SIFIVE_SDRAM_H #define _SIFIVE_SDRAM_H -#include <arch/mmio.h> #include <console/console.h> #include <device/mmio.h> #include <soc/addressmap.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/82693?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I08f7480650b42df1613994146a026bd1e12dbf66 Gerrit-Change-Number: 82693 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[S] Change in coreboot[main]: tree: Remove duplicated <soc/gpio.h>
by Elyes Haouas (Code Review) 29 May '24

29 May '24

Attention is currently required from: Alexander Couzens, Elyes Haouas, Julius Werner, Michał Żygowski, Philipp Hug, Piotr Król, Ron Minnich. Hello Alexander Couzens, Julius Werner, Michał Kopeć, Michał Żygowski, Philipp Hug, Piotr Król, Ron Minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82691?usp=email to look at the new patch set (#3). Change subject: tree: Remove duplicated <soc/gpio.h> ...................................................................... tree: Remove duplicated <soc/gpio.h> <gpio.h> is supposed to chain-include <soc/gpio.h>. Change-Id: Ib25581bd2c8dd38cdd0396561ce5f9a782365f14 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/mainboard/lenovo/m900_tiny/ramstage.c M src/mainboard/msi/ms7d25/die.c M src/mainboard/msi/ms7e06/die.c M src/mainboard/protectli/vault_cml/die.c M src/soc/qualcomm/common/pcie_common.c M src/soc/qualcomm/common/qspi.c M src/soc/qualcomm/sc7280/pcie.c M src/soc/rockchip/common/gpio.c M src/soc/rockchip/rk3288/display.c M src/soc/rockchip/rk3288/gpio.c M src/soc/rockchip/rk3399/display.c M src/soc/rockchip/rk3399/gpio.c M src/soc/sifive/fu740/clock.c M src/soc/sifive/fu740/gpio.c 14 files changed, 0 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/82691/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/82691?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib25581bd2c8dd38cdd0396561ce5f9a782365f14 Gerrit-Change-Number: 82691 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Attention: Ron Minnich <rminnich(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com>

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[XS] Change in coreboot[main]: util/smmstoretool: explain what happens when no store is found
by Maciej Pijanowski (Code Review) 29 May '24

29 May '24

Attention is currently required from: Sergii Dmytruk. Hello Sergii Dmytruk, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82692?usp=email to look at the new patch set (#2). Change subject: util/smmstoretool: explain what happens when no store is found ...................................................................... util/smmstoretool: explain what happens when no store is found We are going to expose ths tool to end users, and want to take care that the presented information can be consumed by them. The current code simply prints below warnings if we use release binary available for end-user to download: No firmware volume header present No valid firmware volume was found It will be concerning and not clear to end users, they might not understant why it happens, what are the implications, and whether it is something that they should worry about. This commit tries to explain what actually happens here. Change-Id: Iaa2678f5ae7c243811484c0567ced97ae0b3fc0a Signed-off-by: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> --- M util/smmstoretool/storage.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/82692/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82692?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa2678f5ae7c243811484c0567ced97ae0b3fc0a Gerrit-Change-Number: 82692 Gerrit-PatchSet: 2 Gerrit-Owner: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com>

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