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Change subject: util/smmstoretool: explain what happens when no store is found
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
I have not looked much into the code, just run the tool. Please correct me if I am wrong here.
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Change subject: util/smmstoretool: explain what happens when no store is found
......................................................................
util/smmstoretool: explain what happens when no store is found
We are going to expose ths tool to end users, and want to take
care that the presented information can be consumed by them.
The current code simply prints below warnings if we use release
binary available for end-user to download:
No firmware volume header present
No valid firmware volume was found
It will be concerning and not clear to end users, they might not
understant why it happens, what are the implciations, and whether
it is something that they should worry about.
This commit tries to explain what actually happens here.
Change-Id: Iaa2678f5ae7c243811484c0567ced97ae0b3fc0a
Signed-off-by: Maciej Pijanowski <maciej.pijanowski(a)3mdeb.com>
---
M util/smmstoretool/storage.c
1 file changed, 6 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/82692/1
diff --git a/util/smmstoretool/storage.c b/util/smmstoretool/storage.c
index 8a02384..b077a47 100644
--- a/util/smmstoretool/storage.c
+++ b/util/smmstoretool/storage.c
@@ -50,6 +50,12 @@
goto error;
}
+ fprintf(stderr,
+ "Variable store has not been found in the binary and will "
+ "be initialized now.\nIt is expected if release binary is "
+ "used, as variable store normally is initialized on the "
+ "first boot of the platform.\n");
+
if (!fv_init(storage->region)) {
fprintf(stderr,
"Failed to create variable store in \"%s\"\n",
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Change subject: util/lint: Add lint rule to avoid duplicated includes
......................................................................
util/lint: Add lint rule to avoid duplicated includes
Change-Id: Ia14c73f0bffa6ee4b73254d71836f793af8771c4
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
A util/lint/lint-stable-031-includes
1 file changed, 57 insertions(+), 0 deletions(-)
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Change subject: mb/razer/blade_stealth_kbl: Add H3Q variant
......................................................................
Patch Set 8:
(4 comments)
File src/mainboard/razer/blade_stealth_kbl/Kconfig:
https://review.coreboot.org/c/coreboot/+/82506/comment/ab95b207_466d634b?us… :
PS6, Line 4: def_bool n
> Sure, will do.
Done
File src/mainboard/razer/blade_stealth_kbl/variants/h2u/overridetree.cb:
PS6:
> Add missing SPDX license identifier.
Done
File src/mainboard/razer/blade_stealth_kbl/variants/h3q/overridetree.cb:
PS6:
> Add missing SPDX license identifier.
Done
https://review.coreboot.org/c/coreboot/+/82506/comment/e897b8b4_1b59ba67?us… :
PS6, Line 7: OC_SKIP
> Sorry, I totally forgot about this! @icon on Matrix kindly explained how to find the pins for this, […]
Oh, you are @icon :). Thanks for the pointers, I added them correct pins.
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Change subject: tree: Remove duplicated <soc/gpio.h>
......................................................................
Patch Set 2: Code-Review+2
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I'd like you to reexamine a change. Please visit
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Change subject: mb/razer/blade_stealth_kbl: Add H3Q variant
......................................................................
mb/razer/blade_stealth_kbl: Add H3Q variant
The Razer Blade Stealth Kaby Lake has 2 variants. One is the H2U
variant, as originally committed, with the SKU number RZ09-01962, also
known as the 2016 model, and the H3Q model with SKU numbers RZ09-01963
and RZ09-01964, known as the Mid 2017 model. This commit adds support
for the H3Q model. With respect to coreboot, there are few known
differences:
1. Only the H2U has TPM.
2. The USB ports are different.
3. The screen size (and therefore VBIOS Table) is different.
4. The hda_verb is very slightly different.
Change-Id: I493a651e52c2eb938daa67a05e9caaa784020fa4
Signed-off-by: Reagan Bohan <xbjfk.github(a)gmail.com>
---
M src/mainboard/razer/blade_stealth_kbl/Kconfig
M src/mainboard/razer/blade_stealth_kbl/Kconfig.name
M src/mainboard/razer/blade_stealth_kbl/Makefile.mk
M src/mainboard/razer/blade_stealth_kbl/board_info.txt
M src/mainboard/razer/blade_stealth_kbl/devicetree.cb
A src/mainboard/razer/blade_stealth_kbl/variants/h2u/board_info.txt
R src/mainboard/razer/blade_stealth_kbl/variants/h2u/hda_verb.c
A src/mainboard/razer/blade_stealth_kbl/variants/h2u/overridetree.cb
A src/mainboard/razer/blade_stealth_kbl/variants/h3q/board_info.txt
C src/mainboard/razer/blade_stealth_kbl/variants/h3q/hda_verb.c
A src/mainboard/razer/blade_stealth_kbl/variants/h3q/overridetree.cb
11 files changed, 114 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/82506/8
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Reagan has posted comments on this change by Nico Huber. ( https://review.coreboot.org/c/coreboot/+/79917?usp=email )
Change subject: soc/intel/skylake: Drop redundant PcieRpEnable
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/razer/blade_stealth_kbl/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/79917/comment/bff37a19_053403ae?us… :
PS2, Line 190: device ref pcie_rp1 on end
> I don't have this board, but based on what I found on librem_skl, I bet this is supposed to be pcie_ […]
I happen to have a very similar board (see CB:82506). You are indeed correct. For some reason root port 3 is remapped to 1c.0 (I'm not sure what PCIe remapping is or why it occurs). It seems the author added `device 1c.0`, so this wasn't caught. Then in CB:79326, it switched to `pcie_rp1`. I get a warning in the coreboot console related to this, and using `pcie_rp3` fixes it.
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Change subject: util/lint: Add lint rule to avoid duplicated includes
......................................................................
Patch Set 10:
(1 comment)
File util/lint/lint-stable-031-includes:
https://review.coreboot.org/c/coreboot/+/81907/comment/b40b781c_aae9c145?us… :
PS5, Line 56: check_duplicates '<arch/pci_ops.h>' '<device/pci_ops.h>'
> about <string.h>, I found it here https://review.coreboot.org/c/coreboot/+/39468 […]
The rules I've used are in `Documentation/contributing/coding_style.md` section 'Headers and includes'
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Verified+1 by build bot (Jenkins)
Change subject: util/lint: Add lint rule to avoid duplicated includes
......................................................................
util/lint: Add lint rule to avoid duplicated includes
Change-Id: Ia14c73f0bffa6ee4b73254d71836f793af8771c4
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
A util/lint/lint-stable-031-includes
1 file changed, 56 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/81907/10
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I'd like you to reexamine a change. Please visit
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Change subject: tree: Remove duplicated <soc/gpio.h>
......................................................................
tree: Remove duplicated <soc/gpio.h>
<gpio.h> is supposed to provide <soc/gpio.h>.
Change-Id: Ib25581bd2c8dd38cdd0396561ce5f9a782365f14
Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr>
---
M src/mainboard/lenovo/m900_tiny/ramstage.c
M src/mainboard/msi/ms7d25/die.c
M src/mainboard/msi/ms7e06/die.c
M src/mainboard/protectli/vault_cml/die.c
M src/soc/qualcomm/common/pcie_common.c
M src/soc/qualcomm/common/qspi.c
M src/soc/qualcomm/sc7280/pcie.c
M src/soc/rockchip/common/gpio.c
M src/soc/rockchip/rk3288/display.c
M src/soc/rockchip/rk3288/gpio.c
M src/soc/rockchip/rk3399/display.c
M src/soc/rockchip/rk3399/gpio.c
M src/soc/sifive/fu740/clock.c
M src/soc/sifive/fu740/gpio.c
14 files changed, 0 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/82691/2
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