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Change subject: soc/intel/xeon_sp/gnr: Add IIO config utils
......................................................................
soc/intel/xeon_sp/gnr: Add IIO config utils
Add IIO configuration utils shared in GNR boards to handle the
complex IIO configuration settings.
TEST=Build and boot on intel/archercity CRB
Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Co-authored-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/gnr/Makefile.mk
A src/soc/intel/xeon_sp/gnr/include/soc/iio.h
A src/soc/intel/xeon_sp/gnr/soc_iio.c
3 files changed, 200 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/81318/44
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
soc/intel/xeon_sp: Add Granite Rapids initial codes
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.
This patch initially sets the code set up as a build target with
Granite Rapids N-1 FSP (src/vc/intel/fsp/fsp2_0/graniterapids).
1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmitsburg PCH)'s codes are reused.
2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.
Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Co-authored-by: Gang Chen <gang.c.chen(a)intel.com>
Co-authored-by: Jincheng Li <jincheng.li(a)intel.com>
---
M src/soc/intel/xeon_sp/Makefile.mk
A src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/Kconfig
A src/soc/intel/xeon_sp/gnr/Makefile.mk
A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl
A src/soc/intel/xeon_sp/gnr/chip.c
A src/soc/intel/xeon_sp/gnr/chip.h
A src/soc/intel/xeon_sp/gnr/chipset.cb
A src/soc/intel/xeon_sp/gnr/cpu.c
A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h
A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h
A src/soc/intel/xeon_sp/gnr/ramstage.c
A src/soc/intel/xeon_sp/gnr/romstage.c
A src/soc/intel/xeon_sp/gnr/soc_acpi.c
A src/soc/intel/xeon_sp/gnr/soc_util.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
M src/soc/intel/xeon_sp/spr/cpu.c
M src/soc/intel/xeon_sp/spr/soc_acpi.c
20 files changed, 1,122 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/54
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Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email )
Change subject: block/fast_spi: Use read32p/write32p for spi rw
......................................................................
Patch Set 2:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82079/comment/c3033f71_8ec44b19 :
PS2, Line 7: spi
SPI
https://review.coreboot.org/c/coreboot/+/82079/comment/20848c33_104dc6a8 :
PS2, Line 9: impl.
No need to abbreviate words in the commit message.
https://review.coreboot.org/c/coreboot/+/82079/comment/ea6a0127_06559644 :
PS2, Line 15: TEST=Build and boot mtl 64-bit and verified MRC cache working.
Any boot time difference?
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Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email )
Change subject: block/fast_spi: Use read32p/write32p for spi rw
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82079/comment/df7cb749_1f70679f :
PS2, Line 9: The memcpy impl. for
: x86_64 changed to 8 byte copy and due to 4 byte limit, spi rw fails. MRC
: cache rw regression observed in existing X86_64 platforms. Hence update
: rw ops to use read32p/write32p.
Maybe change this to say that the hardware only accepts at most dword transactions at most which won't work with the current 64bit implementation of memcpy?
File src/soc/intel/common/block/fast_spi/fast_spi_flash.c:
https://review.coreboot.org/c/coreboot/+/82079/comment/cfbf4466_bb5eabfe :
PS2, Line 80: const uint8_t *byte_ptr = (const uint8_t *)data;
: size_t bytes_to_copy;
: union {
: uint32_t full;
: uint8_t bytes[4];
: } dword;
:
: for (size_t i = 0; i < len; i += 4) {
: dword.full = 0;
:
: bytes_to_copy = (len - i < 4) ? len - i : 4;
: for (size_t j = 0; j < bytes_to_copy; j++)
: dword.bytes[j] = byte_ptr[i + j];
:
: write32p(ctx->mmio_base + SPIBAR_FDATA(i >> 2), dword.full);
: }
I think the HW accepts at most dword transactions, but also word and byte ones. Which is why the 32bit memcpy worked.
This code isn't efficient. Just loop over dwords and put them into SPIBAR_FDATA, then for the remaining bytes do it bytewise (just like 32bit memcpy)?
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Change subject: [MTL-x64]arch/x86: Update X86_64 memcpy for 4 byte copy
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> In current implementation fast_spi uses memcpy() and it is clear that the change in memcpy() broke it.
> We can make memcpy() to any no. of bytes, but it shouldn't break existing code that depend on memcpy() and cause regression on existing platforms. Also saying using memcpy() is "wrong" is wrong. It's a valid approach.
>
It's really not a valid approach to rely on specific internals of memcpy if your hardware specifically needs 32bit MMIO. And your "shouldn't break existing code" is also inappropriate: that fast_spi code is wrong, not memcpy...
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Change subject: drivers/crb: Check for PTT before attempting to initialize CRB TPM
......................................................................
Patch Set 2: Code-Review+2
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