coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

1 participants
3293 discussions

[S] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Support fast boot
by Shuo Liu (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Chen, Gang C, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/82080?usp=email to review the following change. Change subject: soc/intel/xeon_sp/gnr: Support fast boot ...................................................................... soc/intel/xeon_sp/gnr: Support fast boot Fast boot will used pre-saved hardware configuration data to accelerate the boot process, e.g. DDR training is skipped by using pre-saved training data. Change-Id: Ib5dc76176b16ea1be5dd9b05a375c9179411f590 Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h M src/soc/intel/xeon_sp/gnr/romstage.c 2 files changed, 24 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/82080/1 diff --git a/src/soc/intel/xeon_sp/gnr/include/soc/vpd.h b/src/soc/intel/xeon_sp/gnr/include/soc/vpd.h new file mode 100644 index 0000000..ae0fceb --- /dev/null +++ b/src/soc/intel/xeon_sp/gnr/include/soc/vpd.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _SOC_VPD_H_ +#define _SOC_VPD_H_ + +#define FAST_BOOT_EN "fast_boot_en" /* 1 or 0: enable or disable fast boot for warm/cold reset */ +#define FAST_BOOT_EN_DEFAULT 1 /* Default value when this VPD variable is not found */ + +#endif /* _SOC_VPD_H_ */ diff --git a/src/soc/intel/xeon_sp/gnr/romstage.c b/src/soc/intel/xeon_sp/gnr/romstage.c index 10a2318..dda4364 100644 --- a/src/soc/intel/xeon_sp/gnr/romstage.c +++ b/src/soc/intel/xeon_sp/gnr/romstage.c @@ -13,6 +13,7 @@ #include <string.h> #include <soc/soc_util.h> #include <soc/ddr.h> +#include <soc/vpd.h> #include "chip.h" @@ -68,6 +69,20 @@ m_cfg->serialDebugMsgLvl = config->serial_debug_msg_lvl; m_cfg->SerialIoUartDebugIoBase = config->serial_io_uart_debug_io_base; + /* FAST_BOOT_EN */ + uint8_t val = FAST_BOOT_EN_DEFAULT; + vpd_get_bool(FAST_BOOT_EN, VPD_RW_THEN_RO, &val); + m_cfg->AttemptFastBoot = val; + m_cfg->AttemptFastBootCold = val; + + FSPM_ARCHx_UPD *arch_upd = &mupd->FspmArchUpd; + if ((arch_upd->NvsBufferPtr != 0) && (val != FAST_BOOT_EN_DEFAULT)) { + arch_upd->BootMode = + FSP_BOOT_WITH_FULL_CONFIGURATION; + printk(BIOS_NOTICE, "Reset BootMode as " + "FSP_BOOT_WITH_FULL_CONFIGURATION.\n"); + } + /* Board level settings */ mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/82080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib5dc76176b16ea1be5dd9b05a375c9179411f590 Gerrit-Change-Number: 82080 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Add IIO config utils
by Shuo Liu (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Martin L Roth, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu. Hello Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81318?usp=email to look at the new patch set (#44). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp/gnr: Add IIO config utils ...................................................................... soc/intel/xeon_sp/gnr: Add IIO config utils Add IIO configuration utils shared in GNR boards to handle the complex IIO configuration settings. TEST=Build and boot on intel/archercity CRB Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Co-authored-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/gnr/Makefile.mk A src/soc/intel/xeon_sp/gnr/include/soc/iio.h A src/soc/intel/xeon_sp/gnr/soc_iio.c 3 files changed, 200 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/81318/44 -- To view, visit https://review.coreboot.org/c/coreboot/+/81318?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7146761db6f73a0c4b0d31b010c0d30a42bf690 Gerrit-Change-Number: 81318 Gerrit-PatchSet: 44 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu. Hello Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81316?usp=email to look at the new patch set (#54). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... soc/intel/xeon_sp: Add Granite Rapids initial codes coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single IO-APIC Xeon-SP platform. The same set of codes is also used for SRF (Sierra Forest) SoC. This patch initially sets the code set up as a build target with Granite Rapids N-1 FSP (src/vc/intel/fsp/fsp2_0/graniterapids). 1. All register definitions are forked from SPR (Sapphire Rapids) and EBG (Emmitsburg PCH)'s codes are reused. 2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later. Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Co-authored-by: Gang Chen <gang.c.chen(a)intel.com> Co-authored-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/Makefile.mk A src/soc/intel/xeon_sp/chip_gen6.c A src/soc/intel/xeon_sp/gnr/Kconfig A src/soc/intel/xeon_sp/gnr/Makefile.mk A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl A src/soc/intel/xeon_sp/gnr/chip.c A src/soc/intel/xeon_sp/gnr/chip.h A src/soc/intel/xeon_sp/gnr/chipset.cb A src/soc/intel/xeon_sp/gnr/cpu.c A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h A src/soc/intel/xeon_sp/gnr/ramstage.c A src/soc/intel/xeon_sp/gnr/romstage.c A src/soc/intel/xeon_sp/gnr/soc_acpi.c A src/soc/intel/xeon_sp/gnr/soc_util.c M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/spr/cpu.c M src/soc/intel/xeon_sp/spr/soc_acpi.c 20 files changed, 1,122 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/54 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 54 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: mb/google/corsola/var/wugtrio: Add STA_ER88577 MIPI panel
by Paul Menzel (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Haikun Zhou, Hung-Te Lin, Yang Wu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82055?usp=email ) Change subject: mb/google/corsola/var/wugtrio: Add STA_ER88577 MIPI panel ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82055?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I279d431d80ca0770540d88e213d4aeafe77038ce Gerrit-Change-Number: 82055 Gerrit-PatchSet: 6 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haikun Zhou <zhouhaikun5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Haikun Zhou <zhouhaikun5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 13:29:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for spi rw
by Paul Menzel (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Arthur Heymans, Ashish Kumar Mishra, Saurabh Mishra, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email ) Change subject: block/fast_spi: Use read32p/write32p for spi rw ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82079/comment/c3033f71_8ec44b19 : PS2, Line 7: spi SPI https://review.coreboot.org/c/coreboot/+/82079/comment/20848c33_104dc6a8 : PS2, Line 9: impl. No need to abbreviate words in the commit message. https://review.coreboot.org/c/coreboot/+/82079/comment/ea6a0127_06559644 : PS2, Line 15: TEST=Build and boot mtl 64-bit and verified MRC cache working. Any boot time difference? -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 24 Apr 2024 13:28:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/corsola/var/wugtrio: Add STA_ER88577 MIPI panel
by Haikun Zhou (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yang Wu. Haikun Zhou has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82055?usp=email ) Change subject: mb/google/corsola/var/wugtrio: Add STA_ER88577 MIPI panel ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82055/comment/12d732df_eb490993 : PS5, Line 7: wugtrio > yes Done -- To view, visit https://review.coreboot.org/c/coreboot/+/82055?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I279d431d80ca0770540d88e213d4aeafe77038ce Gerrit-Change-Number: 82055 Gerrit-PatchSet: 6 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haikun Zhou <zhouhaikun5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 12:44:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Haikun Zhou <zhouhaikun5(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for spi rw
by Angel Pons (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Arthur Heymans, Ashish Kumar Mishra, Saurabh Mishra, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email ) Change subject: block/fast_spi: Use read32p/write32p for spi rw ...................................................................... Patch Set 2: (2 comments) File src/soc/intel/common/block/fast_spi/fast_spi_flash.c: https://review.coreboot.org/c/coreboot/+/82079/comment/6fe9ab94_a7bd729b : PS2, Line 80: const uint8_t *byte_ptr = (const uint8_t *)data; : size_t bytes_to_copy; : union { : uint32_t full; : uint8_t bytes[4]; : } dword; : : for (size_t i = 0; i < len; i += 4) { : dword.full = 0; : : bytes_to_copy = (len - i < 4) ? len - i : 4; : for (size_t j = 0; j < bytes_to_copy; j++) : dword.bytes[j] = byte_ptr[i + j]; : : write32p(ctx->mmio_base + SPIBAR_FDATA(i >> 2), dword.full); : } > I think the HW accepts at most dword transactions, but also word and byte ones. […] This is what I suggested in CB:81959 but back then I wasn't sure if the hardware can also accept smaller width transactions: ``` static void fill_xfer_fifo(struct fast_spi_flash_ctx *ctx, const uint8_t *data, size_t len) { /* FDATAn requires 32-bit accesses */ const uint32_t *dwords = (const uint32_t *)data; for (size_t i = 0; i < len / 4; i++) write32p(ctx->mmio_base + SPIBAR_FDATA(i), dwords[i]); if (len % 4) { uint32_t last_dword = 0; for (size_t i = 0; i < len % 4; i++) last_dword |= data[len / 4 + i] << (i * 8); write32p(ctx->mmio_base + SPIBAR_FDATA(len / 4), last_dword); } } ``` But if the hardware can tolerate byte-width transactions: ``` static void fill_xfer_fifo(struct fast_spi_flash_ctx *ctx, const uint8_t *data, size_t len) { const uint32_t *dwords = (const uint32_t *)data; for (size_t i = 0; i < len / 4; i++) write32p(ctx->mmio_base + SPIBAR_FDATA(i), dwords[i]); for (size_t i = 0; i < len % 4; i++) write8p(ctx->mmio_base + SPIBAR_FDATA(len / 4) + i, data[len / 4 + i]) } ``` Maximum code simplicity would be to only use byte reads/writes, but I'm not sure if there's a performance impact: ``` static void fill_xfer_fifo(struct fast_spi_flash_ctx *ctx, const uint8_t *data, size_t len) { for (size_t i = 0; i < len; i++) write8p(ctx->mmio_base + SPIBAR_FDATA(0) + i, data[i]) } ``` https://review.coreboot.org/c/coreboot/+/82079/comment/3da4f8b5_53039b2c : PS2, Line 99: static void drain_xfer_fifo(struct fast_spi_flash_ctx *ctx, void *dest, My original suggestion from CB:81959 is: ``` static void drain_xfer_fifo(struct fast_spi_flash_ctx *ctx, uint8_t *dest, size_t len) { /* FDATAn requires 32-bit accesses */ uint32_t *dwords = (uint32_t *)data; for (size_t i = 0; i < len / 4; i++) dwords[i] = read32p(ctx->mmio_base + SPIBAR_FDATA(i)); if (len % 4) { const uint32_t last_dword = read32p(ctx->mmio_base + SPIBAR_FDATA(len / 4)); for (size_t i = 0; i < len % 4; i++) data[len / 4 + i] = (uint8_t)(last_dword >> (i * 8)); } } ``` But if the hardware can tolerate byte-width transactions: ``` static void drain_xfer_fifo(struct fast_spi_flash_ctx *ctx, uint8_t *dest, size_t len) { uint32_t *dwords = (uint32_t *)data; for (size_t i = 0; i < len / 4; i++) dwords[i] = read32p(ctx->mmio_base + SPIBAR_FDATA(i)); for (size_t i = 0; i < len % 4; i++) data[len / 4 + i] = read8p(ctx->mmio_base + SPIBAR_FDATA(len / 4) + i); } ``` Maximum code simplicity would be to only use byte reads/writes, but I'm not sure if there's a performance impact: ``` static void drain_xfer_fifo(struct fast_spi_flash_ctx *ctx, uint8_t *dest, size_t len) { for (size_t i = 0; i < len % 4; i++) data[i] = read8p(ctx->mmio_base + SPIBAR_FDATA(0) + i); } ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 24 Apr 2024 12:42:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/google/corsola/wugtrio: Add STA_ER88577 MIPI panel
by Yu-Ping Wu (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Haikun Zhou, Hung-Te Lin, Paul Menzel, Yang Wu. Yu-Ping Wu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82055?usp=email ) Change subject: mb/google/corsola/wugtrio: Add STA_ER88577 MIPI panel ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82055/comment/41323305_2575ff73 : PS5, Line 7: wugtrio > hi, you meain "mb/google/corsola/var/wugtrio: Add STA_ER88577 MIPI panel"? yes -- To view, visit https://review.coreboot.org/c/coreboot/+/82055?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I279d431d80ca0770540d88e213d4aeafe77038ce Gerrit-Change-Number: 82055 Gerrit-PatchSet: 5 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haikun Zhou <zhouhaikun5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Haikun Zhou <zhouhaikun5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 12:35:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Haikun Zhou <zhouhaikun5(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for spi rw
by Arthur Heymans (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Ashish Kumar Mishra, Saurabh Mishra, Subrata Banik. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email ) Change subject: block/fast_spi: Use read32p/write32p for spi rw ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82079/comment/df7cb749_1f70679f : PS2, Line 9: The memcpy impl. for : x86_64 changed to 8 byte copy and due to 4 byte limit, spi rw fails. MRC : cache rw regression observed in existing X86_64 platforms. Hence update : rw ops to use read32p/write32p. Maybe change this to say that the hardware only accepts at most dword transactions at most which won't work with the current 64bit implementation of memcpy? File src/soc/intel/common/block/fast_spi/fast_spi_flash.c: https://review.coreboot.org/c/coreboot/+/82079/comment/cfbf4466_bb5eabfe : PS2, Line 80: const uint8_t *byte_ptr = (const uint8_t *)data; : size_t bytes_to_copy; : union { : uint32_t full; : uint8_t bytes[4]; : } dword; : : for (size_t i = 0; i < len; i += 4) { : dword.full = 0; : : bytes_to_copy = (len - i < 4) ? len - i : 4; : for (size_t j = 0; j < bytes_to_copy; j++) : dword.bytes[j] = byte_ptr[i + j]; : : write32p(ctx->mmio_base + SPIBAR_FDATA(i >> 2), dword.full); : } I think the HW accepts at most dword transactions, but also word and byte ones. Which is why the 32bit memcpy worked. This code isn't efficient. Just loop over dwords and put them into SPIBAR_FDATA, then for the remaining bytes do it bytewise (just like 32bit memcpy)? -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 12:18:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: [MTL-x64]arch/x86: Update X86_64 memcpy for 4 byte copy
by Arthur Heymans (Code Review) 24 Apr '24

24 Apr '24

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81959?usp=email ) Change subject: [MTL-x64]arch/x86: Update X86_64 memcpy for 4 byte copy ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > In current implementation fast_spi uses memcpy() and it is clear that the change in memcpy() broke it. > We can make memcpy() to any no. of bytes, but it shouldn't break existing code that depend on memcpy() and cause regression on existing platforms. Also saying using memcpy() is "wrong" is wrong. It's a valid approach. > It's really not a valid approach to rely on specific internals of memcpy if your hardware specifically needs 32bit MMIO. And your "shouldn't break existing code" is also inappropriate: that fast_spi code is wrong, not memcpy... -- To view, visit https://review.coreboot.org/c/coreboot/+/81959?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1110cc18f5aa59c864e3cc04b9e6b3501ec4d54d Gerrit-Change-Number: 81959 Gerrit-PatchSet: 3 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 24 Apr 2024 12:13:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2024