coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
by Appukuttan V K (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Subrata Banik. Appukuttan V K has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81661?usp=email ) Change subject: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned ...................................................................... Patch Set 10: (1 comment) File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/81661/comment/3c79303f_221aa887 : PS10, Line 38: sizeof(uint64_t) > can u please check if `__aligned(4)` works here. […] Yes. Tried x32 with bot 4 and 8 alignment in rex system. Both boots fine and only difference is in the base address. [SPEW ] Fsp TemporaryRamBase - 0xFEF90E88 << 8 Bytes [SPEW ] Fsp TemporaryRamBase - 0xFEF90E84 << 4 Bytes Do you want to change it to 4 for x32 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/81661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Gerrit-Change-Number: 81661 Gerrit-PatchSet: 10 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 16:19:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Support fast boot
by Arthur Heymans (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82080?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Support fast boot ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Patchset: PS1: > Sometimes it is needed to do full boot to retrain memory, e.g. when temperature has big change, when some DIMM is replaced, hence a VPD is needed to control this. Maybe we need to raise this VPD to OCP level and cover SPR as well? If there is no particular demand for then just leave it? Setting the value at mb level and inside the soc code is a bit much ofc, but that's just cleanup after all. -- To view, visit https://review.coreboot.org/c/coreboot/+/82080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib5dc76176b16ea1be5dd9b05a375c9179411f590 Gerrit-Change-Number: 82080 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 16:11:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for spi rw
by Angel Pons (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Arthur Heymans, Ashish Kumar Mishra, Paul Menzel, Saurabh Mishra, Subrata Banik. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email ) Change subject: block/fast_spi: Use read32p/write32p for spi rw ...................................................................... Patch Set 2: (1 comment) File src/soc/intel/common/block/fast_spi/fast_spi_flash.c: https://review.coreboot.org/c/coreboot/+/82079/comment/db7b4704_03eb0d52 : PS2, Line 80: const uint8_t *byte_ptr = (const uint8_t *)data; : size_t bytes_to_copy; : union { : uint32_t full; : uint8_t bytes[4]; : } dword; : : for (size_t i = 0; i < len; i += 4) { : dword.full = 0; : : bytes_to_copy = (len - i < 4) ? len - i : 4; : for (size_t j = 0; j < bytes_to_copy; j++) : dword.bytes[j] = byte_ptr[i + j]; : : write32p(ctx->mmio_base + SPIBAR_FDATA(i >> 2), dword.full); : } > A similar impl. […] OK. Marking this as unresolved until the patch is actually updated. -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 24 Apr 2024 16:03:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Use OCP_VPD drivers
by Angel Pons (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Jincheng Li, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, TangYiwei, Tim Chu. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81317?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Use OCP_VPD drivers ...................................................................... Patch Set 44: (1 comment) File src/soc/intel/xeon_sp/gnr/Kconfig: https://review.coreboot.org/c/coreboot/+/81317/comment/451a1b57_f322efa0 : PS44, Line 19: select OCP_VPD I don't think selecting (requiring) `OCP_VPD` is a good idea. At the very least, please consider doing this: ``` static int get_fsp_mem_log_level(void) { /* TODO: Implement the option API using VPD */ if (CONFIG(OCP_VPD)) return get_int_from_vpd_range(FSP_MEM_LOG_LEVEL, FSP_MEM_LOG_LEVEL_DEFAULT, 0, 4); else return FSP_MEM_LOG_LEVEL_DEFAULT; } static bool get_fsp_log_enable(void) { /* TODO: Implement the option API using VPD */ if (CONFIG(OCP_VPD)) return get_bool_from_vpd(FSP_LOG, FSP_LOG_DEFAULT); else return FSP_LOG_DEFAULT; } void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { /* Prologue omitted for brevity */ m_cfg->serialDebugMsgLvl = get_fsp_mem_log_level(); m_cfg->SerialIoUartDebugEnable = get_fsp_enable_log(); } ``` (Note: not build tested, might need to replace the if statements with preprocessor if the non-VPD case doesn't build) Including the TODOs. Ideally, SoC code would use the option API, and OCP would implement the option API using VPD: ``` void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { /* Prologue omitted for brevity */ m_cfg->serialDebugMsgLvl = get_uint_option("fsp_log_level", DEFAULT_FSP_LOG_LEVEL); m_cfg->SerialIoUartDebugEnable = !!get_uint_option("fsp_enable_log", DEFAULT_FSP_ENABLE_LOG); } ``` This way, if someone else wants to use another option API (e.g. EFI variable store, for use with an edk2 payload), they don't need to change anything in SoC code. I understand that implementing the option API using VPD as a backend is not trivial. So, my suggestion to get this change unblocked is to avoid depending on `OCP_VPD` for now; eventually, the plan is to use the option API for maximum flexibility. -- To view, visit https://review.coreboot.org/c/coreboot/+/81317?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifeca8cf4312ab66ca03188fe25af88a952073130 Gerrit-Change-Number: 81317 Gerrit-PatchSet: 44 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 16:00:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Add Granite Rapids FSP into Xeon-SP
by Paul Menzel (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Shuo Liu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82082?usp=email ) Change subject: MAINTAINERS: Add Granite Rapids FSP into Xeon-SP ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82082?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5170a69d798d0e8198b89f6932a80e6051228ac2 Gerrit-Change-Number: 82082 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 15:32:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: MAINTAINERS: Add Granite Rapids FSP into Xeon-SP
by Paul Menzel (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Shuo Liu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82082?usp=email ) Change subject: MAINTAINERS: Add Granite Rapids FSP into Xeon-SP ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82082/comment/2e003d77_a2883386 : PS2, Line 7: into add … to? -- To view, visit https://review.coreboot.org/c/coreboot/+/82082?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5170a69d798d0e8198b89f6932a80e6051228ac2 Gerrit-Change-Number: 82082 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 15:32:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Paul Menzel (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 55: (8 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81316/comment/56261c74_c7b6078e : PS53, Line 20: > We have to add this after SoC launch since it is shift-left opensource at the moment. […] Acknowledged PS: What does “shift-left” mean? https://review.coreboot.org/c/coreboot/+/81316/comment/980ca802_81706f52 : PS53, Line 21: TEST=Build and boot on intel/archercity CRB > Sorry, here the test means this patch doesn't impact archercity CRB. […] Acknowledged Patchset: PS55: Thank you for addressing my comments so quickly. File src/soc/intel/xeon_sp/gnr/cpu.c: https://review.coreboot.org/c/coreboot/+/81316/comment/83f5daeb_b440676c : PS53, Line 87: return num_virts * soc_get_num_cpus(); > This API calculates the thread counts which correspond to num_virts (logical cores), while num_phys […] Maybe add a comment, because it might be confusing seeing the value in the log message, but then seeing, it’s not used. https://review.coreboot.org/c/coreboot/+/81316/comment/11f536bb_70896832 : PS53, Line 114: printk(BIOS_ERR, "microcode not found in CBFS!\n"); > It will caused the subsequent call to skip the microcode loading. […] The log level should match then? The other log message could also be extended to say, that no updates are applied. – It’s implicit but better be explicit.) https://review.coreboot.org/c/coreboot/+/81316/comment/0f3d8e35_efc477d9 : PS53, Line 116: intel_microcode_load_unlocked(microcode_patch); > Yes. Acknowledged File src/soc/intel/xeon_sp/gnr/include/soc/vpd.h: https://review.coreboot.org/c/coreboot/+/81316/comment/779c5b3f_ebd946bb : PS53, Line 6: #define FAST_BOOT_EN "fast_boot_en" /* 1 or 0: enable or disable fast boot for warm/cold reset */ > https://review.coreboot. […] Thank you. File src/soc/intel/xeon_sp/include/soc/acpi.h: https://review.coreboot.org/c/coreboot/+/81316/comment/80492703_7738ebab : PS53, Line 21: unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current); > We have to keep the declaration to pass build, however, I remove the null implementation, […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 55 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 15:31:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Use OCP_VPD drivers
by Patrick Rudolph (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, David Hendricks, Jincheng Li, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, TangYiwei, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81317?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Use OCP_VPD drivers ...................................................................... Patch Set 44: Code-Review-1 (1 comment) Patchset: PS44: Common code should not select mainboard specific drivers. -- To view, visit https://review.coreboot.org/c/coreboot/+/81317?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifeca8cf4312ab66ca03188fe25af88a952073130 Gerrit-Change-Number: 81317 Gerrit-PatchSet: 44 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 15:24:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP
by Patrick Rudolph (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82081?usp=email ) Change subject: soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82081?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b Gerrit-Change-Number: 82081 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 15:23:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: skyrim/devicetree.cb: Remove BT GPIO delays
by Tim Van Patten (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Jason Nien, Martin L Roth. Tim Van Patten has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/73300?usp=email ) Change subject: skyrim/devicetree.cb: Remove BT GPIO delays ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Abandon this? I've pinged the bug (and CC'ed you), so we can see what the verdict is. -- To view, visit https://review.coreboot.org/c/coreboot/+/73300?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdb6b93832110aed51864b608891edf808643808 Gerrit-Change-Number: 73300 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Van Patten <timvp(a)google.com> Gerrit-Reviewer: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jason Nien <jason.nien(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 15:16:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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coreboot-gerrit April 2024