coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Remove x64-specific assertion from fsp_header
by Arthur Heymans (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Andrey Petrov, Appukuttan V K, Ronak Kanabar. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81662?usp=email ) Change subject: drivers/intel/fsp2_0: Remove x64-specific assertion from fsp_header ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81662?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6013af342670e6377a3fe7641d7d9b52c9b6f57c Gerrit-Change-Number: 81662 Gerrit-PatchSet: 8 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 19:10:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
by Arthur Heymans (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Appukuttan V K, Subrata Banik. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81661?usp=email ) Change subject: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned ...................................................................... Patch Set 10: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81661/comment/4e90bc7c_5e9e4f30 : PS10, Line 15: stack It's a heap really... -- To view, visit https://review.coreboot.org/c/coreboot/+/81661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Gerrit-Change-Number: 81661 Gerrit-PatchSet: 10 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 19:10:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: arch/arm64: Extend cache helper functions
by Lean Sheng Tan (Code Review) 24 Apr '24

24 Apr '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79106?usp=email ) Change subject: arch/arm64: Extend cache helper functions ...................................................................... arch/arm64: Extend cache helper functions This patch extends the cpu_get_cache_info function, so that additional information like size of cache lines can be retrieved. Patch was tested against the qemu-sbsa mainboard. Change-Id: If6fe731dc67ffeaff9344d2bd2627f45185c27de Signed-off-by: David Milosevic <David.Milosevic(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79106 Reviewed-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/arch/arm64/armv8/cache.c M src/arch/arm64/include/armv8/arch/cache.h 2 files changed, 27 insertions(+), 12 deletions(-) Approvals: Maximilian Brune: Looks good to me, approved build bot (Jenkins): Verified Angel Pons: Looks good to me, but someone else must approve Benjamin Doron: Looks good to me, approved diff --git a/src/arch/arm64/armv8/cache.c b/src/arch/arm64/armv8/cache.c index 879ef62..f843ed4 100644 --- a/src/arch/arm64/armv8/cache.c +++ b/src/arch/arm64/armv8/cache.c @@ -46,27 +46,34 @@ } } -void cpu_get_cache_info(enum cache_level level, enum cache_type type, size_t *cache_size, size_t *assoc) +enum cb_err cpu_get_cache_info(const enum cache_level level, const enum cache_type type, + struct cache_info *info) { uint64_t ccsidr_el1; - if (cache_size == NULL || assoc == NULL) - return; + if (info == NULL || level < CACHE_L1 || level > CACHE_L7) + return CB_ERR_ARG; - if (level < CACHE_L1 || level > CACHE_L7) - return; - - /* [0] - Indicates instruction cache; [3:1] - Indicates cache level */ + /* + * select target cache. + * [0] - Indicates instruction cache [3:1] - Indicates cache level + */ raw_write_csselr_el1(((level - 1) << 1) | (type == CACHE_INSTRUCTION)); ccsidr_el1 = raw_read_ccsidr_el1(); /* [2:0] - Indicates (Log2(Number of bytes in cache line) - 4) */ - uint8_t line_length = 1 << ((ccsidr_el1 & 0x7) + 4); + info->line_bytes = (1 << ((ccsidr_el1 & 0x7) + 4)); + /* (Number of sets in cache) - 1 */ - uint64_t num_sets = get_ccsidr_el1_numsets(ccsidr_el1) + 1; + info->numsets = get_ccsidr_el1_numsets(ccsidr_el1) + 1; + /* (Associativity of cache) - 1 */ - *assoc = get_ccsidr_el1_assoc(ccsidr_el1) + 1; - *cache_size = line_length * *assoc * num_sets; + info->associativity = get_ccsidr_el1_assoc(ccsidr_el1) + 1; + + /* computed size of cache in bytes */ + info->size = info->line_bytes * info->associativity * info->numsets; + + return CB_SUCCESS; } unsigned int dcache_line_bytes(void) diff --git a/src/arch/arm64/include/armv8/arch/cache.h b/src/arch/arm64/include/armv8/arch/cache.h index 5097196..da6edfd 100644 --- a/src/arch/arm64/include/armv8/arch/cache.h +++ b/src/arch/arm64/include/armv8/arch/cache.h @@ -31,8 +31,16 @@ CACHE_UNIFIED = 4, }; +struct cache_info { + uint64_t size; // total size of cache in bytes + uint64_t associativity; // number of cache lines in a set + uint64_t numsets; // number of sets in a cache + uint8_t line_bytes; // size of cache line in bytes +}; + enum cache_type cpu_get_cache_type(enum cache_level level); -void cpu_get_cache_info(enum cache_level level, enum cache_type, size_t *cache_size, size_t *assoc); +enum cb_err cpu_get_cache_info(const enum cache_level level, const enum cache_type type, + struct cache_info *info); /* dcache clean by virtual address to PoC */ void dcache_clean_by_mva(void const *addr, size_t len); -- To view, visit https://review.coreboot.org/c/coreboot/+/79106?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If6fe731dc67ffeaff9344d2bd2627f45185c27de Gerrit-Change-Number: 79106 Gerrit-PatchSet: 15 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: arch/arm64: Add EL1/EL2/EL3 support for arm64
by Julius Werner (Code Review) 24 Apr '24

24 Apr '24

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74798?usp=email ) Change subject: arch/arm64: Add EL1/EL2/EL3 support for arm64 ...................................................................... Patch Set 19: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/74798/comment/d283396e_5e8d93b6 : PS5, Line 11: one boots into TF-A first and drops into EL2 for coreboot afterwards. > not treated as a decision to support upstream to run a proprietary BIOS under coreboot (i.e. proprietary BL31). FWIW I don't think we're currently disallowing proprietary BL31s to begin with? That's what CONFIG_ARM64_BL31_EXTERNAL_FILE was made for. I would agree that there may be a new discussion to be had in case someone's proprietary BL31 requires a lot of custom support code to be added to coreboot, but as long as they support the same interface and just want to put their own file into CBFS I don't think we need to take issue with that (it's also pretty impossible to prevent in practice, anyone can run cbfstool manually). -- To view, visit https://review.coreboot.org/c/coreboot/+/74798?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae1c57f0846c8d0585384f7e54102a837e701e7e Gerrit-Change-Number: 74798 Gerrit-PatchSet: 19 Gerrit-Owner: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 18:18:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Comment-In-Reply-To: David Milosevic <David.Milosevic(a)9elements.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: haswell NRI: Post-process selected timings
by Patrick Rudolph (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Felix Held, Nico Huber. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64185?usp=email ) Change subject: haswell NRI: Post-process selected timings ...................................................................... Patch Set 5: (1 comment) File src/northbridge/intel/haswell/native_raminit/lookup_timings.c: https://review.coreboot.org/c/coreboot/+/64185/comment/138f60a9_11f60df4 : PS5, Line 9: uint32_t > i'd be in favor of keeping this as it is for now and only look into changing this once all other pat […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/64185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id02caf858f75b9e08016762b3aefda282b274386 Gerrit-Change-Number: 64185 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 24 Apr 2024 18:02:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: soc/mediatek/mt8188: devapc: set devapc permission for MFG
by Yidi Lin (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Fei Yan, Hung-Te Lin. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82076?usp=email ) Change subject: soc/mediatek/mt8188: devapc: set devapc permission for MFG ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82076/comment/1e3cec9d_3a54d0ca : PS3, Line 9: Set MFG to domain 6. : Set MFG remap in infra and sub infra, so that MFG can switch to protect mode by MFG register. : Set MFG slave MFG_S_S-2 and MFG_S_S-5 permission from NO_PROTECTION to SEC_RW_ONLY for domain 0, : so that only AP in secure mode can access MFG_S_S-2 and MFG_S_S-5. 72 characters per line for the commit message. Patchset: PS3: Please resolve the review comments by selecting the checkbox `Resolved`. -- To view, visit https://review.coreboot.org/c/coreboot/+/82076?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6fb7d85bf9d4d92946a045a274b274abc440e1d Gerrit-Change-Number: 82076 Gerrit-PatchSet: 3 Gerrit-Owner: Fei Yan <fei.yan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Fei Yan <fei.yan(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Fei Yan <fei.yan(a)mediatek.corp-partner.google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 17:50:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: drivers/mipi: Add support for STA_ER88576 panel
by Yidi Lin (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Haikun Zhou, Paul Menzel, Xuxin Xiong, Yang Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82054?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: drivers/mipi: Add support for STA_ER88576 panel ...................................................................... Patch Set 7: Code-Review+2 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82054/comment/f84492a3_862ef741 : PS7, Line 11: about About https://review.coreboot.org/c/coreboot/+/82054/comment/71453360_cad57e53 : PS7, Line 11: about the init code, we communicated with the vendor : through the datasheet to confirm the writing method : of each register value. 72 characters per line for the commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/82054?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I210b23b67fbc102c9926171f1c78f6824820e4b7 Gerrit-Change-Number: 82054 Gerrit-PatchSet: 7 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Haikun Zhou <zhouhaikun5(a)huaqin.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Haikun Zhou <zhouhaikun5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 17:43:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/dell/optiplex_9020: Implement late HWM initialization
by Felix Held (Code Review) 24 Apr '24

24 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81529?usp=email ) Change subject: mb/dell/optiplex_9020: Implement late HWM initialization ...................................................................... mb/dell/optiplex_9020: Implement late HWM initialization There are 4 different chassis types specified by vendor firmware, each with a slightly different HWM configuration. The chassis type to use is determined at runtime by reading a set of 4 PCH GPIOs: 70, 38, 17, and 1. Additionally vendor firmware also provides an option to run the fans at full speed. This is substituted with a coreboot nvram option in this implementation. This was tested to make fan control work on my OptiPlex 7020 SFF. NOTE: This is superficially similar to the OptiPlex 9010's SCH5545 however the OptiPlex 9020's SCH5555 does not use externally programmed EC firmware. Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43 Signed-off-by: Mate Kukri <kukri.mate(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81529 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/dell/optiplex_9020/Makefile.mk M src/mainboard/dell/optiplex_9020/bootblock.c M src/mainboard/dell/optiplex_9020/cmos.default M src/mainboard/dell/optiplex_9020/cmos.layout M src/mainboard/dell/optiplex_9020/mainboard.c A src/mainboard/dell/optiplex_9020/sch5555_ec.c A src/mainboard/dell/optiplex_9020/sch5555_ec.h 7 files changed, 465 insertions(+), 24 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/mainboard/dell/optiplex_9020/Makefile.mk b/src/mainboard/dell/optiplex_9020/Makefile.mk index 6ca2f2a..08e2e53 100644 --- a/src/mainboard/dell/optiplex_9020/Makefile.mk +++ b/src/mainboard/dell/optiplex_9020/Makefile.mk @@ -2,4 +2,5 @@ romstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -bootblock-y += bootblock.c +ramstage-y += sch5555_ec.c +bootblock-y += bootblock.c sch5555_ec.c diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c index 2837cf9..0055910 100644 --- a/src/mainboard/dell/optiplex_9020/bootblock.c +++ b/src/mainboard/dell/optiplex_9020/bootblock.c @@ -4,29 +4,14 @@ #include <device/pnp_ops.h> #include <superio/smsc/sch555x/sch555x.h> #include <southbridge/intel/lynxpoint/pch.h> - -static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val) -{ - // Clear EC-to-Host mailbox - uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); - outb(tmp, SCH555x_EMI_IOBASE + 1); - - // Send address and value to the EC - sch555x_emi_write16(0, (addr1 * 2) | 0x101); - sch555x_emi_write32(4, val | (addr2 << 16)); - - // Wait for acknowledgement message from EC - outb(1, SCH555x_EMI_IOBASE); - size_t timeout = 0; - do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0); -} +#include "sch5555_ec.h" struct ec_init_entry { uint16_t addr; uint8_t val; }; -static void ec_init(void) +static void bootblock_ec_init(void) { /* * Tables from CORE_PEI @@ -42,7 +27,7 @@ }; for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i) - ec_write(2, init_table1[i].addr, init_table1[i].val); + sch5555_mbox_write(2, init_table1[i].addr, init_table1[i].val); static const struct ec_init_entry init_table2[] = { {0x0005, 0x33}, {0x0018, 0x2f}, {0x0019, 0x2f}, {0x001a, 0x2f}, @@ -60,7 +45,7 @@ }; for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i) - ec_write(1, init_table2[i].addr, init_table2[i].val); + sch5555_mbox_write(1, init_table2[i].addr, init_table2[i].val); /* * Table from PeiHwmInit @@ -89,7 +74,7 @@ }; for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i) - ec_write(1, hwm_init_table[i].addr, hwm_init_table[i].val); + sch5555_mbox_write(1, hwm_init_table[i].addr, hwm_init_table[i].val); } #define SCH555x_IOBASE 0x2e @@ -108,9 +93,9 @@ outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1); outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED); - // Magic EC init - ec_init(); + // Perform bootblock EC initialization + bootblock_ec_init(); - // Magic EC init is needed for UART1 initialization to work + // Bootblock EC initialization is required for UART1 to work sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default index cd4046f..6c4a2a1 100644 --- a/src/mainboard/dell/optiplex_9020/cmos.default +++ b/src/mainboard/dell/optiplex_9020/cmos.default @@ -3,3 +3,4 @@ debug_level=Debug nmi=Disable power_on_after_fail=Disable +fan_full_speed=Disable diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout index c9ba76c..d10ad95 100644 --- a/src/mainboard/dell/optiplex_9020/cmos.layout +++ b/src/mainboard/dell/optiplex_9020/cmos.layout @@ -21,6 +21,9 @@ 408 1 e 1 nmi 409 2 e 5 power_on_after_fail +# coreboot config options: EC +412 1 e 1 fan_full_speed + # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c index c834fea..6630a12 100644 --- a/src/mainboard/dell/optiplex_9020/mainboard.c +++ b/src/mainboard/dell/optiplex_9020/mainboard.c @@ -1,7 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <bootstate.h> +#include <cpu/x86/msr.h> #include <device/device.h> #include <drivers/intel/gma/int15.h> +#include <option.h> +#include <southbridge/intel/common/gpio.h> +#include "sch5555_ec.h" static void mainboard_enable(struct device *dev) { @@ -13,3 +18,385 @@ struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, }; + +#define HWM_TAB_ADD_TEMP_TARGET 1 +#define HWM_TAB_PKG_POWER_ANY 0xffff +#define CHASSIS_TYPE_UNKNOWN 0xff + +struct hwm_tab_entry { + uint16_t addr; + uint8_t val; + uint8_t flags; + uint16_t pkg_power; +}; + +struct hwm_tab_entry HWM_TAB3[] = { + { 0x005, 0x33, 0, 0xffff }, + { 0x018, 0x2f, 0, 0xffff }, + { 0x019, 0x2f, 0, 0xffff }, + { 0x01a, 0x2f, 0, 0xffff }, + { 0x080, 0x00, 0, 0xffff }, + { 0x081, 0x00, 0, 0xffff }, + { 0x083, 0xbb, 0, 0xffff }, + { 0x085, 0x8a, 0, 0x0010 }, + { 0x086, 0x4c, 0, 0x0010 }, + { 0x08a, 0x66, 0, 0x0010 }, + { 0x08b, 0x5b, 0, 0x0010 }, + { 0x090, 0x65, 0, 0xffff }, + { 0x091, 0x70, 0, 0xffff }, + { 0x092, 0x86, 0, 0xffff }, + { 0x096, 0xa4, 0, 0xffff }, + { 0x097, 0xa4, 0, 0xffff }, + { 0x098, 0xa4, 0, 0xffff }, + { 0x09b, 0xa4, 0, 0xffff }, + { 0x0a0, 0x0e, 0, 0xffff }, + { 0x0a1, 0x0e, 0, 0xffff }, + { 0x0ae, 0x7c, 0, 0xffff }, + { 0x0af, 0x86, 0, 0xffff }, + { 0x0b0, 0x9a, 0, 0xffff }, + { 0x0b3, 0x9a, 0, 0xffff }, + { 0x0b6, 0x08, 0, 0xffff }, + { 0x0b7, 0x08, 0, 0xffff }, + { 0x0ea, 0x64, 0, 0x0020 }, + { 0x0ea, 0x5c, 0, 0x0010 }, + { 0x0ef, 0xff, 0, 0xffff }, + { 0x0f8, 0x15, 0, 0xffff }, + { 0x0f9, 0x00, 0, 0xffff }, + { 0x0f0, 0x30, 0, 0xffff }, + { 0x0fd, 0x01, 0, 0xffff }, + { 0x1a1, 0x00, 0, 0xffff }, + { 0x1a2, 0x00, 0, 0xffff }, + { 0x1b1, 0x08, 0, 0xffff }, + { 0x1be, 0x99, 0, 0xffff }, + { 0x280, 0xa0, 0, 0x0010 }, + { 0x281, 0x0f, 0, 0x0010 }, + { 0x282, 0x03, 0, 0xffff }, + { 0x283, 0x0a, 0, 0xffff }, + { 0x284, 0x80, 0, 0xffff }, + { 0x285, 0x03, 0, 0xffff }, + { 0x288, 0x68, 0, 0x0010 }, + { 0x289, 0x10, 0, 0x0010 }, + { 0x28a, 0x03, 0, 0xffff }, + { 0x28b, 0x0a, 0, 0xffff }, + { 0x28c, 0x80, 0, 0xffff }, + { 0x28d, 0x03, 0, 0xffff }, +}; + +struct hwm_tab_entry HWM_TAB4[] = { + { 0x005, 0x33, 0, 0xffff }, + { 0x018, 0x2f, 0, 0xffff }, + { 0x019, 0x2f, 0, 0xffff }, + { 0x01a, 0x2f, 0, 0xffff }, + { 0x080, 0x00, 0, 0xffff }, + { 0x081, 0x00, 0, 0xffff }, + { 0x083, 0xbb, 0, 0xffff }, + { 0x085, 0x99, 0, 0x0020 }, + { 0x085, 0xad, 0, 0x0010 }, + { 0x086, 0x1c, 0, 0xffff }, + { 0x08a, 0x39, 0, 0x0020 }, + { 0x08a, 0x41, 0, 0x0010 }, + { 0x08b, 0x76, 0, 0x0020 }, + { 0x08b, 0x8b, 0, 0x0010 }, + { 0x090, 0x5e, 0, 0xffff }, + { 0x091, 0x5e, 0, 0xffff }, + { 0x092, 0x86, 0, 0xffff }, + { 0x096, 0xa4, 0, 0xffff }, + { 0x097, 0xa4, 0, 0xffff }, + { 0x098, 0xa4, 0, 0xffff }, + { 0x09b, 0xa4, 0, 0xffff }, + { 0x0a0, 0x0a, 0, 0xffff }, + { 0x0a1, 0x0a, 0, 0xffff }, + { 0x0ae, 0x7c, 0, 0xffff }, + { 0x0af, 0x7c, 0, 0xffff }, + { 0x0b0, 0x9a, 0, 0xffff }, + { 0x0b3, 0x7c, 0, 0xffff }, + { 0x0b6, 0x08, 0, 0xffff }, + { 0x0b7, 0x08, 0, 0xffff }, + { 0x0ea, 0x64, 0, 0x0020 }, + { 0x0ea, 0x5c, 0, 0x0010 }, + { 0x0ef, 0xff, 0, 0xffff }, + { 0x0f8, 0x15, 0, 0xffff }, + { 0x0f9, 0x00, 0, 0xffff }, + { 0x0f0, 0x30, 0, 0xffff }, + { 0x0fd, 0x01, 0, 0xffff }, + { 0x1a1, 0x00, 0, 0xffff }, + { 0x1a2, 0x00, 0, 0xffff }, + { 0x1b1, 0x08, 0, 0xffff }, + { 0x1be, 0x90, 0, 0xffff }, + { 0x280, 0x94, 0, 0x0020 }, + { 0x281, 0x11, 0, 0x0020 }, + { 0x280, 0x94, 0, 0x0010 }, + { 0x281, 0x11, 0, 0x0010 }, + { 0x282, 0x03, 0, 0xffff }, + { 0x283, 0x0a, 0, 0xffff }, + { 0x284, 0x80, 0, 0xffff }, + { 0x285, 0x03, 0, 0xffff }, + { 0x288, 0x28, 0, 0x0020 }, + { 0x289, 0x0a, 0, 0x0020 }, + { 0x288, 0x28, 0, 0x0010 }, + { 0x289, 0x0a, 0, 0x0010 }, + { 0x28a, 0x03, 0, 0xffff }, + { 0x28b, 0x0a, 0, 0xffff }, + { 0x28c, 0x80, 0, 0xffff }, + { 0x28d, 0x03, 0, 0xffff }, +}; + +struct hwm_tab_entry HWM_TAB5[] = { + { 0x005, 0x33, 0, 0xffff }, + { 0x018, 0x2f, 0, 0xffff }, + { 0x019, 0x2f, 0, 0xffff }, + { 0x01a, 0x2f, 0, 0xffff }, + { 0x080, 0x00, 0, 0xffff }, + { 0x081, 0x00, 0, 0xffff }, + { 0x083, 0xbb, 0, 0xffff }, + { 0x085, 0x66, 0, 0x0020 }, + { 0x085, 0x5d, 0, 0x0010 }, + { 0x086, 0x1c, 0, 0xffff }, + { 0x08a, 0x39, 0, 0x0020 }, + { 0x08a, 0x41, 0, 0x0010 }, + { 0x08b, 0x76, 0, 0x0020 }, + { 0x08b, 0x80, 0, 0x0010 }, + { 0x090, 0x5d, 0, 0x0020 }, + { 0x090, 0x5e, 0, 0x0010 }, + { 0x091, 0x5e, 0, 0xffff }, + { 0x092, 0x86, 0, 0xffff }, + { 0x096, 0xa4, 0, 0xffff }, + { 0x097, 0xa4, 0, 0xffff }, + { 0x098, 0xa3, 0, 0x0020 }, + { 0x098, 0xa4, 0, 0x0010 }, + { 0x09b, 0xa4, 0, 0xffff }, + { 0x0a0, 0x08, 0, 0xffff }, + { 0x0a1, 0x0a, 0, 0xffff }, + { 0x0ae, 0x7c, 0, 0xffff }, + { 0x0af, 0x7c, 0, 0xffff }, + { 0x0b0, 0x9a, 0, 0xffff }, + { 0x0b3, 0x7c, 0, 0xffff }, + { 0x0b6, 0x08, 0, 0xffff }, + { 0x0b7, 0x08, 0, 0xffff }, + { 0x0ea, 0x64, 0, 0x0020 }, + { 0x0ea, 0x5c, 0, 0x0010 }, + { 0x0ef, 0xff, 0, 0xffff }, + { 0x0f8, 0x15, 0, 0xffff }, + { 0x0f9, 0x00, 0, 0xffff }, + { 0x0f0, 0x30, 0, 0xffff }, + { 0x0fd, 0x01, 0, 0xffff }, + { 0x1a1, 0x00, 0, 0xffff }, + { 0x1a2, 0x00, 0, 0xffff }, + { 0x1b1, 0x08, 0, 0xffff }, + { 0x1be, 0x98, 0, 0x0020 }, + { 0x1be, 0x90, 0, 0x0010 }, + { 0x280, 0x94, 0, 0x0020 }, + { 0x281, 0x11, 0, 0x0020 }, + { 0x280, 0x94, 0, 0x0010 }, + { 0x281, 0x11, 0, 0x0010 }, + { 0x282, 0x03, 0, 0xffff }, + { 0x283, 0x0a, 0, 0xffff }, + { 0x284, 0x80, 0, 0xffff }, + { 0x285, 0x03, 0, 0xffff }, + { 0x288, 0x28, 0, 0x0020 }, + { 0x289, 0x0a, 0, 0x0020 }, + { 0x288, 0x28, 0, 0x0010 }, + { 0x289, 0x0a, 0, 0x0010 }, + { 0x28a, 0x03, 0, 0xffff }, + { 0x28b, 0x0a, 0, 0xffff }, + { 0x28c, 0x80, 0, 0xffff }, + { 0x28d, 0x03, 0, 0xffff }, +}; + +struct hwm_tab_entry HWM_TAB6[] = { + { 0x005, 0x33, 0, 0xffff }, + { 0x018, 0x2f, 0, 0xffff }, + { 0x019, 0x2f, 0, 0xffff }, + { 0x01a, 0x2f, 0, 0xffff }, + { 0x080, 0x00, 0, 0xffff }, + { 0x081, 0x00, 0, 0xffff }, + { 0x083, 0xbb, 0, 0xffff }, + { 0x085, 0x98, 0, 0xffff }, + { 0x086, 0x3c, 0, 0xffff }, + { 0x08a, 0x39, 0, 0x0020 }, + { 0x08a, 0x3d, 0, 0x0010 }, + { 0x08b, 0x44, 0, 0x0020 }, + { 0x08b, 0x51, 0, 0x0010 }, + { 0x090, 0x61, 0, 0xffff }, + { 0x091, 0x6d, 0, 0xffff }, + { 0x092, 0x86, 0, 0xffff }, + { 0x096, 0xa4, 0, 0xffff }, + { 0x097, 0xa4, 0, 0xffff }, + { 0x098, 0x9f, 0, 0x0020 }, + { 0x098, 0xa4, 0, 0x0010 }, + { 0x09b, 0xa4, 0, 0xffff }, + { 0x0a0, 0x0e, 0, 0xffff }, + { 0x0a1, 0x0e, 0, 0xffff }, + { 0x0ae, 0x7c, 0, 0xffff }, + { 0x0af, 0x7c, 0, 0xffff }, + { 0x0b0, 0x9b, 0, 0x0020 }, + { 0x0b0, 0x98, 0, 0x0010 }, + { 0x0b3, 0x9a, 0, 0xffff }, + { 0x0b6, 0x08, 0, 0xffff }, + { 0x0b7, 0x08, 0, 0xffff }, + { 0x0ea, 0x64, 0, 0x0020 }, + { 0x0ea, 0x5c, 0, 0x0010 }, + { 0x0ef, 0xff, 0, 0xffff }, + { 0x0f8, 0x15, 0, 0xffff }, + { 0x0f9, 0x00, 0, 0xffff }, + { 0x0f0, 0x30, 0, 0xffff }, + { 0x0fd, 0x01, 0, 0xffff }, + { 0x1a1, 0x00, 0, 0xffff }, + { 0x1a2, 0x00, 0, 0xffff }, + { 0x1b1, 0x08, 0, 0xffff }, + { 0x1be, 0x9a, 0, 0x0020 }, + { 0x1be, 0x96, 0, 0x0010 }, + { 0x280, 0x94, 0, 0x0020 }, + { 0x281, 0x11, 0, 0x0020 }, + { 0x280, 0x94, 0, 0x0010 }, + { 0x281, 0x11, 0, 0x0010 }, + { 0x282, 0x03, 0, 0xffff }, + { 0x283, 0x0a, 0, 0xffff }, + { 0x284, 0x80, 0, 0xffff }, + { 0x285, 0x03, 0, 0xffff }, + { 0x288, 0x94, 0, 0x0020 }, + { 0x289, 0x11, 0, 0x0020 }, + { 0x288, 0x94, 0, 0x0010 }, + { 0x289, 0x11, 0, 0x0010 }, + { 0x28a, 0x03, 0, 0xffff }, + { 0x28b, 0x0a, 0, 0xffff }, + { 0x28c, 0x80, 0, 0xffff }, + { 0x28d, 0x03, 0, 0xffff }, +}; + +static uint8_t get_chassis_type(void) +{ + uint8_t gpio_chassis_type; + + // Read chassis type from GPIO + gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 | + get_gpio(17) << 1 | get_gpio(1); + + printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type); + + // Turn it into internal chassis index + switch (gpio_chassis_type) { + case 0x08: + case 0x0a: + return 4; + case 0x0b: + return 3; + case 0x0c: + return 5; + case 0x0d: // SFF + case 0x0e: + case 0x0f: + return 6; + default: + return CHASSIS_TYPE_UNKNOWN; + } + +} + +static uint8_t get_temp_target(void) +{ + uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; + if (!val) + val = 20; + return 0x95 - val; +} + +static uint16_t get_pkg_power(void) +{ + uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf; + if (rapl_power_unit) + rapl_power_unit = 2 << (rapl_power_unit - 1); + uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff; + if (pkg_power_info / rapl_power_unit > 0x41) + return 32; + else + return 16; +} + +static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size) +{ + uint8_t temp_target = get_temp_target(); + uint16_t pkg_power = get_pkg_power(); + + printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target); + printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power); + + for (size_t i = 0; i < size; ++i) { + // Skip entry if it doesn't apply for this package power + if (arr[i].pkg_power != pkg_power && + arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY) + continue; + + uint8_t val = arr[i].val; + + // Add temp target to value if requested (current tables never do) + if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET) + val += temp_target; + + // Perform write + sch5555_mbox_write(1, arr[i].addr, val); + + } +} + +static void sch5555_ec_hwm_init(void *arg) +{ + uint8_t chassis_type, saved_2fc; + + printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n"); + + saved_2fc = sch5555_mbox_read(1, 0x2fc); + sch5555_mbox_write(1, 0x2fc, 0xa0); + sch5555_mbox_write(1, 0x2fd, 0x32); + + chassis_type = get_chassis_type(); + + if (chassis_type != CHASSIS_TYPE_UNKNOWN) { + printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type); + } else { + printk(BIOS_DEBUG, "WARNING: Unknown chassis type\n"); + } + + // Apply HWM table based on chassis type + switch (chassis_type) { + case 3: + apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3)); + break; + case 4: + apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4)); + break; + case 5: + apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5)); + break; + case 6: + apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6)); + break; + } + + // NOTE: vendor firmware applies these when "max core address" > 2 + // i think this is always the case + sch5555_mbox_write(1, 0x9e, 0x30); + sch5555_mbox_write(1, 0xeb, sch5555_mbox_read(1, 0xea)); + + sch5555_mbox_write(1, 0x2fc, saved_2fc); + + // Apply full speed fan config if requested or if the chassis type is unknown + if (chassis_type == CHASSIS_TYPE_UNKNOWN || get_uint_option("fan_full_speed", 0)) { + printk(BIOS_DEBUG, "Setting full fan speed\n"); + sch5555_mbox_write(1, 0x80, 0x60 | sch5555_mbox_read(1, 0x80)); + sch5555_mbox_write(1, 0x81, 0x60 | sch5555_mbox_read(1, 0x81)); + } + + sch5555_mbox_read(1, 0xb8); + + if ((chassis_type == 4 || chassis_type == 5) && sch5555_mbox_read(1, 0x26) == 0) { + sch5555_mbox_write(1, 0xa0, sch5555_mbox_read(1, 0xa0) & 0xfb); + sch5555_mbox_write(1, 0xa1, sch5555_mbox_read(1, 0xa1) & 0xfb); + sch5555_mbox_write(1, 0xa2, sch5555_mbox_read(1, 0xa2) & 0xfb); + sch5555_mbox_write(1, 0x8a, 0x99); + sch5555_mbox_write(1, 0x8b, 0x47); + sch5555_mbox_write(1, 0x8c, 0x91); + } +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL); diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c new file mode 100644 index 0000000..1df5026 --- /dev/null +++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/io.h> +#include <device/pnp_ops.h> +#include <superio/smsc/sch555x/sch555x.h> +#include "sch5555_ec.h" + +uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2) +{ + // clear ec-to-host mailbox + uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); + outb(tmp, SCH555x_EMI_IOBASE + 1); + + // send address + outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); + outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4); + + outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); + outl(addr2 << 16, SCH555x_EMI_IOBASE + 4); + + // send message to ec + outb(1, SCH555x_EMI_IOBASE); + + // wait for ack + for (size_t retry = 0; retry < 0xfff; ++retry) + if (inb(SCH555x_EMI_IOBASE + 1) & 1) + break; + + // read result + outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2); + return inb(SCH555x_EMI_IOBASE + 4); +} + +void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val) +{ + // clear ec-to-host mailbox + uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1); + outb(tmp, SCH555x_EMI_IOBASE + 1); + + // send address and value + outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2); + outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4); + + outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2); + outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4); + + // send message to ec + outb(1, SCH555x_EMI_IOBASE); + + // wait for ack + for (size_t retry = 0; retry < 0xfff; ++retry) + if (inb(SCH555x_EMI_IOBASE + 1) & 1) + break; +} diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h new file mode 100644 index 0000000..9d262d5 --- /dev/null +++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SCH5555_EC_H__ +#define __SCH5555_EC_H__ + +uint8_t sch5555_mbox_read(uint8_t addr1, uint16_t addr2); + +void sch5555_mbox_write(uint8_t addr1, uint16_t addr2, uint8_t val); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/81529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43 Gerrit-Change-Number: 81529 Gerrit-PatchSet: 11 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: mb/dell/optiplex_9020: Implement late HWM initialization
by Felix Held (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Máté Kukri, Paul Menzel, Varshit Pandya. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81529?usp=email ) Change subject: mb/dell/optiplex_9020: Implement late HWM initialization ...................................................................... Patch Set 10: (1 comment) File src/mainboard/dell/optiplex_9020/mainboard.c: https://review.coreboot.org/c/coreboot/+/81529/comment/a743eaf2_1294e3c6 : PS9, Line 296: static uint8_t get_temp_target(void) : { : uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff; : if (!val) : val = 20; : return 0x95 - val; : } : : static uint16_t get_pkg_power(void) : { : uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf; : if (rapl_power_unit) : rapl_power_unit = 2 << (rapl_power_unit - 1); : uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff; : if (pkg_power_info / rapl_power_unit > 0x41) : return 32; : else : return 16; : } > I'm OK dealing with this in a follow-up sounds like a good plan -- To view, visit https://review.coreboot.org/c/coreboot/+/81529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43 Gerrit-Change-Number: 81529 Gerrit-PatchSet: 10 Gerrit-Owner: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Máté Kukri <kukri.mate(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 24 Apr 2024 17:42:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Máté Kukri <kukri.mate(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: haswell NRI: Post-process selected timings
by Felix Held (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Nico Huber, Patrick Rudolph. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/64185?usp=email ) Change subject: haswell NRI: Post-process selected timings ...................................................................... Patch Set 5: (1 comment) File src/northbridge/intel/haswell/native_raminit/lookup_timings.c: https://review.coreboot.org/c/coreboot/+/64185/comment/5494072f_57bb5317 : PS5, Line 9: uint32_t > While I don't expect Haswell to run at more than 65535 MHz, changing this would require refactoring […] i'd be in favor of keeping this as it is for now and only look into changing this once all other patches have landed. the current code isn't a problem and changing this to uint16_t seems to be a micro-optimization to me that's not worth the trouble it might cause right now -- To view, visit https://review.coreboot.org/c/coreboot/+/64185?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id02caf858f75b9e08016762b3aefda282b274386 Gerrit-Change-Number: 64185 Gerrit-PatchSet: 5 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 24 Apr 2024 17:05:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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