coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/amd/common/amd_pci_util.h: assign 0 to PIN_A in pcie_swizzle_pin
by Matt DeVillier (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82049?usp=email ) Change subject: soc/amd/common/amd_pci_util.h: assign 0 to PIN_A in pcie_swizzle_pin ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82049?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I21850e21f859f2079f804d4344a1a11856b27d90 Gerrit-Change-Number: 82049 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 24 Apr 2024 15:10:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/common/amd_pci_util.h: rename bridge irq in pci_routing_info
by Matt DeVillier (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82048?usp=email ) Change subject: soc/amd/common/amd_pci_util.h: rename bridge irq in pci_routing_info ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82048?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6410be673d15d6f9b5eb4c80b51fb705fec5b155 Gerrit-Change-Number: 82048 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 24 Apr 2024 15:09:48 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Use OCP_VPD drivers
by Shuo Liu (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, David Hendricks, Jincheng Li, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu. Hello Angel Pons, Arthur Heymans, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81317?usp=email to look at the new patch set (#44). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Code-Review+2 by Lean Sheng Tan, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/xeon_sp/gnr: Use OCP_VPD drivers ...................................................................... soc/intel/xeon_sp/gnr: Use OCP_VPD drivers Use OCP_VPD driver provided functions to get VPD value. Change-Id: Ifeca8cf4312ab66ca03188fe25af88a952073130 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/gnr/Kconfig M src/soc/intel/xeon_sp/gnr/chip.h M src/soc/intel/xeon_sp/gnr/romstage.c 3 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/81317/44 -- To view, visit https://review.coreboot.org/c/coreboot/+/81317?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifeca8cf4312ab66ca03188fe25af88a952073130 Gerrit-Change-Number: 81317 Gerrit-PatchSet: 44 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for spi rw
by Ashish Kumar Mishra (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Paul Menzel, Saurabh Mishra, Subrata Banik. Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email ) Change subject: block/fast_spi: Use read32p/write32p for spi rw ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/82079/comment/666eca01_16b23e95 : PS2, Line 15: TEST=Build and boot mtl 64-bit and verified MRC cache working. > MRC verification passed during warmboot and cbmem verified. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 24 Apr 2024 15:04:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 55: (1 comment) Patchset: PS55: Remove the IORESOURCE_SUBTRACTIVE flag for gen1 legacy IO as well. -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 55 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 15:02:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Hello Angel Pons, Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81316?usp=email to look at the new patch set (#55). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... soc/intel/xeon_sp: Add Granite Rapids initial codes coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single IO-APIC Xeon-SP platform. The same set of codes is also used for SRF (Sierra Forest) SoC. This patch initially sets the code set up as a build target with Granite Rapids N-1 FSP (src/vc/intel/fsp/fsp2_0/graniterapids). 1. All register definitions are forked from SPR (Sapphire Rapids) and EBG (Emmitsburg PCH)'s codes are reused. 2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later. Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Co-authored-by: Gang Chen <gang.c.chen(a)intel.com> Co-authored-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/chip_gen1.c A src/soc/intel/xeon_sp/chip_gen6.c A src/soc/intel/xeon_sp/gnr/Kconfig A src/soc/intel/xeon_sp/gnr/Makefile.mk A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl A src/soc/intel/xeon_sp/gnr/chip.c A src/soc/intel/xeon_sp/gnr/chip.h A src/soc/intel/xeon_sp/gnr/chipset.cb A src/soc/intel/xeon_sp/gnr/cpu.c A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h A src/soc/intel/xeon_sp/gnr/ramstage.c A src/soc/intel/xeon_sp/gnr/romstage.c A src/soc/intel/xeon_sp/gnr/soc_acpi.c A src/soc/intel/xeon_sp/gnr/soc_util.c M src/soc/intel/xeon_sp/include/soc/acpi.h M src/soc/intel/xeon_sp/spr/cpu.c M src/soc/intel/xeon_sp/spr/soc_acpi.c 21 files changed, 1,123 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/55 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 55 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Support fast boot
by Shuo Liu (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82080?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Support fast boot ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > SPR-SP hardcodes to enable (twice, in soc code and mb). […] Sometimes it is needed to do full boot to retrain memory, e.g. when temperature has big change, when some DIMM is replaced, hence a VPD is needed to control this. Maybe we need to raise this VPD to OCP level and cover SPR as well? -- To view, visit https://review.coreboot.org/c/coreboot/+/82080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib5dc76176b16ea1be5dd9b05a375c9179411f590 Gerrit-Change-Number: 82080 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 14:58:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for spi rw
by Ashish Kumar Mishra (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Paul Menzel, Saurabh Mishra, Subrata Banik. Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email ) Change subject: block/fast_spi: Use read32p/write32p for spi rw ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82079/comment/7d6d5038_f57dadb4 : PS2, Line 7: spi > SPI Acknowledged https://review.coreboot.org/c/coreboot/+/82079/comment/3de658cd_a203fade : PS2, Line 9: impl. > No need to abbreviate words in the commit message. Acknowledged https://review.coreboot.org/c/coreboot/+/82079/comment/eadc88d1_ac3129a1 : PS2, Line 15: TEST=Build and boot mtl 64-bit and verified MRC cache working. > Any boot time difference? MRC verification passed during warmboot and cbmem verified. -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 24 Apr 2024 14:55:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: block/fast_spi: Use read32p/write32p for spi rw
by Ashish Kumar Mishra (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Saurabh Mishra, Subrata Banik. Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82079?usp=email ) Change subject: block/fast_spi: Use read32p/write32p for spi rw ...................................................................... Patch Set 2: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82079/comment/da7d9c75_c2254825 : PS2, Line 9: The memcpy impl. for : x86_64 changed to 8 byte copy and due to 4 byte limit, spi rw fails. MRC : cache rw regression observed in existing X86_64 platforms. Hence update : rw ops to use read32p/write32p. > Maybe change this to say that the hardware only accepts at most dword transactions at most which won […] Acknowledged File src/soc/intel/common/block/fast_spi/fast_spi_flash.c: https://review.coreboot.org/c/coreboot/+/82079/comment/1d36861f_ecf594c1 : PS2, Line 80: const uint8_t *byte_ptr = (const uint8_t *)data; : size_t bytes_to_copy; : union { : uint32_t full; : uint8_t bytes[4]; : } dword; : : for (size_t i = 0; i < len; i += 4) { : dword.full = 0; : : bytes_to_copy = (len - i < 4) ? len - i : 4; : for (size_t j = 0; j < bytes_to_copy; j++) : dword.bytes[j] = byte_ptr[i + j]; : : write32p(ctx->mmio_base + SPIBAR_FDATA(i >> 2), dword.full); : } > > This is what I suggested in CB:81959 but back then I wasn't sure if the hardware can also accept s […] A similar impl. I had done for memcpy replacement earlier, however I found the current patchset code easier/simpler. Anyways, I'll verify the test with these new suggestions and update the patch. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/82079?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I317c7160bf192dd2aeacebf6029a809bc97f3420 Gerrit-Change-Number: 82079 Gerrit-PatchSet: 2 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Saurabh Mishra <mishra.saurabh(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 24 Apr 2024 14:53:41 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Support fast boot
by Arthur Heymans (Code Review) 24 Apr '24

24 Apr '24

Attention is currently required from: Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82080?usp=email ) Change subject: soc/intel/xeon_sp/gnr: Support fast boot ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: SPR-SP hardcodes to enable (twice, in soc code and mb). Any particular reason to make it configurable via VPD? -- To view, visit https://review.coreboot.org/c/coreboot/+/82080?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib5dc76176b16ea1be5dd9b05a375c9179411f590 Gerrit-Change-Number: 82080 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 24 Apr 2024 14:26:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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