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Change subject: soc/mediatek/mt8188: devapc: set devapc permission for MFG
......................................................................
Patch Set 3:
(3 comments)
File src/soc/mediatek/mt8188/devapc.c:
https://review.coreboot.org/c/coreboot/+/82076/comment/025c95d3_5dc9b70f :
PS2, Line 1788: // infra
> /* infra */
Done
https://review.coreboot.org/c/coreboot/+/82076/comment/6d240e05_c02e9933 :
PS2, Line 1807: { SUB_INFRACFG_AO_BASE + INFRA_AO_SEC_MFG_HYP2, infra_sec_mfg_hyp_init, dump_sec_mfg_hyp },
> Line too long.
Done
File src/soc/mediatek/mt8188/include/soc/devapc.h:
https://review.coreboot.org/c/coreboot/+/82076/comment/7a2595fd_41f3a091 :
PS2, Line 31:
> one space
Done
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Change subject: drivers/mipi: Add support for STA_ER88576 panel
......................................................................
Patch Set 8:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82054/comment/f6e00706_db2058dc :
PS7, Line 11: about
> About
Done
https://review.coreboot.org/c/coreboot/+/82054/comment/74e3382e_e58c47f2 :
PS7, Line 11: about the init code, we communicated with the vendor
: through the datasheet to confirm the writing method
: of each register value.
> 72 characters per line for the commit message.
Done
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Change subject: soc/intel/mtl: use different names per mtlrvp variants
......................................................................
soc/intel/mtl: use different names per mtlrvp variants
This patch sets different names with different mtlrvp
variants so they can be matched properly with frid.
BUG=None
BRANCH=firmware-rex-15709.B
TEST=Verified boot functionality on google/rex.
Change-Id: I5292a0ffcd7524c55cd7aef37c2f59432b2af06a
---
M src/mainboard/intel/mtlrvp/Kconfig
1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/82084/1
diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig
index 36842b5..bbff4aa 100644
--- a/src/mainboard/intel/mtlrvp/Kconfig
+++ b/src/mainboard/intel/mtlrvp/Kconfig
@@ -79,7 +79,9 @@
config MAINBOARD_PART_NUMBER
string
- default "mtlrvp"
+ default "Mtlrvp_P_Ext_Ec" if BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP4ES_P_EXT_EC
+ default "Mtlrvp_P_Mchp" if BOARD_INTEL_MTLRVP_P_MCHP
+ default "Mtlrvp" if BOARD_INTEL_MTLRVP_P
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP
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Change subject: arch/io.h: Add port I/O functions to other architectures
......................................................................
Patch Set 5:
(1 comment)
File src/arch/arm/include/armv7/arch/io.h:
https://review.coreboot.org/c/coreboot/+/80372/comment/e0c6d0bb_8bae1fb3 :
PS3, Line 17: printk(BIOS_ERR, "arch/io.h: %s() not implemented\n", __func__);
> I'm not really convinced of this "translator" approach tbh, I doesn't feel right. […]
edit: Forgot the important part: I think you should go back to patch set v4, that looks good (minus the TODO).
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Change subject: arch/io.h: Add port I/O functions to other architectures
......................................................................
Patch Set 5:
(2 comments)
File src/arch/arm/include/armv7/arch/io.h:
https://review.coreboot.org/c/coreboot/+/80372/comment/8ca1309c_831c536c :
PS3, Line 17: printk(BIOS_ERR, "arch/io.h: %s() not implemented\n", __func__);
> Done for this patch, if I correctly understood the "no implementation" part. […]
I'm not really convinced of this "translator" approach tbh, I doesn't feel right. Arm CPUs do not have an IN or OUT instruction, pretending like there was one anyway feels like a hack. If the same kind of device can be accessed via MMIO or port I/O, then the driver needs to be written to allow for both (e.g. like we do for 8250 UART), not expect one architecture to emulate stuff that only exists for another.
File src/device/Kconfig:
https://review.coreboot.org/c/coreboot/+/80372/comment/2c946820_4a175460 :
PS5, Line 532: CPU communicate with peripheral devices over PCI I/O space.
Sorry but I don't think this makes sense. Port I/O is a concept completely specific to the x86 architecture, it doesn't make sense on Arm. Arm processors do not have a separate "I/O bus" coming out of the chip that they can address independently. If a device can be accessed over both port I/O or MMIO then the driver needs to be able to handle both cases, and the resource API already provides parts of an abstraction for that (looks like the bochs driver is already written for that). If the VGA driver doesn't allow that then it needs to be expanded (at least it looks like it has accessor wrappers for everything it does already so it hopefully shouldn't be too complicated to add).
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Change subject: soc/intel/meteorlake: Fill PCI SSID parameters
......................................................................
Patch Set 8:
(1 comment)
Patchset:
PS8:
HDA must be programmed during FSP-M using `PchHdaSubSystemIds`. Using `SiSsidTablePtr` apparently no longer works.
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Change subject: mainboard/qemu-aarch64: Set CONFIG_PCI_IOBASE to 0x3eff0000
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82059/comment/5012c9d1_facf915b :
PS1, Line 15: [1] https://gitlab.com/qemu-project/qemu/-/blob/v8.2.3/hw/arm/virt.c#L164
Forgot to use archive.org, but it doesn't appear to work at all with GitLab. It doesn't jump to desired line with GitHub but at least shows the archived file, so I might use that next time I push.
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Change subject: drivers/pc80/vga/vga: Move big buffer for vga_write_text out of stack
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82063/comment/441e8934_29700846 :
PS1, Line 28: as static and clear it each time it's called.
Tested on QEMU (x86, ARM64, RISC-V), but I don't have hardware I can test on.
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Change subject: drivers/qemu/bochs: Allow building for non-x86 architectures
......................................................................
Patch Set 2:
(2 comments)
File src/drivers/emulation/qemu/bochs.c:
https://review.coreboot.org/c/coreboot/+/80376/comment/088bfec5_90b9cb81 :
PS1, Line 52: #if CONFIG(CPU_QEMU_X86)
> I saw on your qemu riscv PCI code that you add IO resources to the PCI domain.
To be fair that was mostly verbatim from qemu-aarch64, without me thoroughly understanding it...
> In qemu I see that reading and writing to VIRT_PCIE_PIO should be translated to IO read/writes
This was the key I needed to understand things better and implement those functions, thanks! Now we can use working port I/O instead.
https://review.coreboot.org/c/coreboot/+/80376/comment/3cc9719c_32ae7dcd :
PS1, Line 118: VGA
> When using the legacy BOCHS VGA, which identifies as PCI_CLASS_DISPLAY_VGA, it must use the legacy V […]
I've implemented port I/O functions and removed this config check here. Not exactly sure what you mean with "legacy VGA resources", but I could manage to configure `-device VGA` into text mode. Writing to `0xB8000` doesn't put anything on the display though, so I kept `HAVE_VGA_TEXT_FRAMEBUFFER` still dependent on x86.
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