coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: drivers/crb: Disable device if CRB TPM not present
by Lean Sheng Tan (Code Review) 25 Apr '24

25 Apr '24

Attention is currently required from: Christian Walter, Michał Żygowski, Sergii Dmytruk. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80454?usp=email ) Change subject: drivers/crb: Disable device if CRB TPM not present ...................................................................... Patch Set 3: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/80454?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie0928536d9042b1f680d585e1ca9ad2cadf0c8ef Gerrit-Change-Number: 80454 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Sergii Dmytruk <sergii.dmytruk(a)3mdeb.com> Gerrit-Comment-Date: Thu, 25 Apr 2024 10:11:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: acpi: Modify the order of increment operations
by Dolan Liu (Code Review) 25 Apr '24

25 Apr '24

Attention is currently required from: Cliff Huang, Jianeng Ceng, Lance Zhao, Tim Wawrzynczak. Dolan Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82088?usp=email ) Change subject: acpi: Modify the order of increment operations ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/82088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a3eb89633aaebebc8bd98ac6126c578fda23839 Gerrit-Change-Number: 82088 Gerrit-PatchSet: 2 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 25 Apr 2024 09:49:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: acpi: Modify the order of increment operations
by Jianeng Ceng (Code Review) 25 Apr '24

25 Apr '24

Attention is currently required from: Cliff Huang, Lance Zhao, Tim Wawrzynczak. Hello Cliff Huang, Lance Zhao, Tim Wawrzynczak, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/82088?usp=email to look at the new patch set (#2). Change subject: acpi: Modify the order of increment operations ...................................................................... acpi: Modify the order of increment operations Fix ++ as suffix and * precedence. After modification, the gpio index can be obtained correctly. BUG=None TEST= Can get the correct index. Change-Id: I7a3eb89633aaebebc8bd98ac6126c578fda23839 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> --- M src/acpi/device.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/82088/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/82088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a3eb89633aaebebc8bd98ac6126c578fda23839 Gerrit-Change-Number: 82088 Gerrit-PatchSet: 2 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: acpi: Modify the order of increment operations
by Jianeng Ceng (Code Review) 25 Apr '24

25 Apr '24

Jianeng Ceng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82088?usp=email ) Change subject: acpi: Modify the order of increment operations ...................................................................... acpi: Modify the order of increment operations Currently, an error in index transfer causes confusion in the output/input status when write gpio descriptor. Change this to perform an increment operation at the same time when assigning values to correctly write the gpio output status. BUG=None TEST= Can get the correct index. Change-Id: I7a3eb89633aaebebc8bd98ac6126c578fda23839 Signed-off-by: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> --- M src/acpi/device.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/82088/1 diff --git a/src/acpi/device.c b/src/acpi/device.c index 091a086..7313639 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -51,7 +51,7 @@ return ret; acpi_device_write_gpio(gpio); - ret = *curr_index++; + ret = (*curr_index)++; return ret; } -- To view, visit https://review.coreboot.org/c/coreboot/+/82088?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7a3eb89633aaebebc8bd98ac6126c578fda23839 Gerrit-Change-Number: 82088 Gerrit-PatchSet: 1 Gerrit-Owner: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: util/docker/coreboot-sdk: Remove libcurl4 from the package list
by Michał Żygowski (Code Review) 25 Apr '24

25 Apr '24

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82066?usp=email ) Change subject: util/docker/coreboot-sdk: Remove libcurl4 from the package list ...................................................................... util/docker/coreboot-sdk: Remove libcurl4 from the package list When installing the packages, apt-get returns an error about holding broken packages. It occurs the diffutils depends on libcurl4t64 which breaks the libcurl4. As a solution, remove the libcurl4 from the list, and let the package manager resolve the dependencies. TEST=Build coreboot-sdk Change-Id: Iabc4f74619d4462317d8adb4068e50135d89d80e Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M util/docker/coreboot-sdk/Dockerfile 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/82066/1 diff --git a/util/docker/coreboot-sdk/Dockerfile b/util/docker/coreboot-sdk/Dockerfile index ecada14..e19fc4d 100644 --- a/util/docker/coreboot-sdk/Dockerfile +++ b/util/docker/coreboot-sdk/Dockerfile @@ -42,7 +42,6 @@ less \ libcapture-tiny-perl \ libcrypto++-dev \ - libcurl4 \ libcurl4-openssl-dev \ libdatetime-perl \ libelf-dev \ -- To view, visit https://review.coreboot.org/c/coreboot/+/82066?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabc4f74619d4462317d8adb4068e50135d89d80e Gerrit-Change-Number: 82066 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: arch/arm/eabi_compat.c: fix warnings of macros
by Integral (Code Review) 25 Apr '24

25 Apr '24

Attention is currently required from: Arthur Heymans. Integral has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82072?usp=email ) Change subject: arch/arm/eabi_compat.c: fix warnings of macros ...................................................................... Patch Set 1: (4 comments) File src/arch/arm/eabi_compat.c: https://review.coreboot.org/c/coreboot/+/82072/comment/34cbc4c5_edb7334e : PS1, Line 8: __used > lint-007-checkpatch said https://review.coreboot.org/c/coreboot/+/82072/comment/3a8e78ce_f59a8adf : PS1, Line 8: __used > lint-007-checkpatch said "Prefer \__used over __attribute__((used))" Prefer \__used over \__attribute\__((used)) https://review.coreboot.org/c/coreboot/+/82072/comment/ec1f8235_f02511c0 : PS1, Line 8: __used > lint-007-checkpatch said https://review.coreboot.org/c/coreboot/+/82072/comment/27dcae42_0fb0b589 : PS1, Line 8: __used > lint-007-checkpatch said "Prefer \__used over __attribute__((used))" -- To view, visit https://review.coreboot.org/c/coreboot/+/82072?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232f011ba0567af78c69eb8f73366b03d29c2839 Gerrit-Change-Number: 82072 Gerrit-PatchSet: 1 Gerrit-Owner: Integral <integral(a)member.fsf.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 25 Apr 2024 08:19:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Integral <integral(a)member.fsf.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: arch/arm/eabi_compat.c: fix warnings of macros
by Integral (Code Review) 25 Apr '24

25 Apr '24

Attention is currently required from: Arthur Heymans. Integral has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82072?usp=email ) Change subject: arch/arm/eabi_compat.c: fix warnings of macros ...................................................................... Patch Set 1: (1 comment) File src/arch/arm/eabi_compat.c: https://review.coreboot.org/c/coreboot/+/82072/comment/cf152aa5_0b16cc1a : PS1, Line 8: __used > This does not exist? lint-007-checkpatch said "Prefer \__used over __attribute__((used))" -- To view, visit https://review.coreboot.org/c/coreboot/+/82072?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232f011ba0567af78c69eb8f73366b03d29c2839 Gerrit-Change-Number: 82072 Gerrit-PatchSet: 1 Gerrit-Owner: Integral <integral(a)member.fsf.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Thu, 25 Apr 2024 08:17:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/google/brox/var/greenbayupoc:Add SODIMM settings
by Eren Peng (Code Review) 25 Apr '24

25 Apr '24

Eren Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82085?usp=email ) Change subject: mb/google/brox/var/greenbayupoc:Add SODIMM settings ...................................................................... mb/google/brox/var/greenbayupoc:Add SODIMM settings Add SODIMM settings for greenbayupoc Change-Id: I1552cadfa81c48fe561947ded078bcca2e6bc6ad Signed-off-by: Eren Peng <peng.eren(a)inventec.corp-partner.google.com> --- M src/mainboard/google/brox/Kconfig A src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk A src/mainboard/google/brox/variants/greenbayupoc/gpio.c A src/mainboard/google/brox/variants/greenbayupoc/memory.c D src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk D src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt D src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt M src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb A src/mainboard/google/brox/variants/greenbayupoc/ramstage.c 9 files changed, 400 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/82085/1 diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 0ec5220..9eecf2d 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -69,6 +69,7 @@ config BOARD_GOOGLE_GREENBAYUPOC select BOARD_GOOGLE_BASEBOARD_BROX + select MEMORY_SODIMM if BOARD_GOOGLE_BROX_COMMON diff --git a/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk b/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk new file mode 100644 index 0000000..090dd5b --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c +romstage-y += gpio.c +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brox/variants/greenbayupoc/gpio.c b/src/mainboard/google/brox/variants/greenbayupoc/gpio.c new file mode 100644 index 0000000..d0ff91e --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/gpio.c @@ -0,0 +1,138 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* This header block is used to supply information to arbitrage, a + * google-internal tool. Updating it incorrectly will lead to issues, + * so please don't update it unless a change is specifically required. + * BaseID: E3110FFB1FCDA587 + * Overrides: None + */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <boardid.h> +#include <commonlib/helpers.h> +#include <soc/gpio.h> +#include <vendorcode/google/chromeos/chromeos.h> + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* GPP_A18 : [NF1: DDSP_HPDB NF4: DISP_MISCB NF6: USB_C_GPP_A18] ==> NC */ + PAD_NC(GPP_A18, NONE), + /* GPP_A19 : [NF1: DDSP_HPD1 NF4: DISP_MISC1 NF6: USB_C_GPP_A19] ==> NC */ + PAD_NC(GPP_A19, None), + /* GPP_A20 : [NF1: DDSP_HPD2 NF4: DISP_MISC2 NF6: USB_C_GPP_A20] ==> NC */ + PAD_NC(GPP_A20, NONE), + + /* GPP_C0 : [NF1: SMBCLK NF6: USB_C_GPP_C0] ==> SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* GPP_C1 : [NF1: SMBDATA NF6: USB_C_GPP_C1] ==> SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> NC */ + PAD_NC(GPP_D9, NONE), + /* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> NC */ + PAD_NC(GPP_D10, NONE), + + /* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> NC */ + PAD_NC(GPP_E4, NONE), + + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */ + PAD_NC(GPP_E10, NONE), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */ + PAD_NC(GPP_E13, NONE), + /* GPP_E15 : SRCCLK_OE8_L ==> NC */ + PAD_NC(GPP_E15, NONE), + + /* GPP_H15 : [NF1: DDPB_CTRLCLK NF3: PCIE_LINK_DOWN NF6: USB_C_GPP_H15] ==> NC */ + PAD_NC(GPP_H15, NONE), + /* GPP_H17 : [NF1: DDPB_CTRLDATA NF6: USB_C_GPP_H17] ==> NC */ + PAD_NC(GPP_H17, NONE), + + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* GPP_D11 : [] ==> EN_PP3300_SSD (NC) */ + PAD_NC(GPP_D11, NONE), + /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC_LOCK(GPP_E2, NONE, LEVEL, INVERT, LOCK_CONFIG), + /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */ + PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 0, DEEP), + /* F21 : EXT_PWR_GATE2# ==> NC */ + PAD_NC(GPP_F21, NONE), + /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_S0, NONE, DEEP), + + /* CPU PCIe VGPIO for PEG60 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> NC */ + PAD_NC(GPP_E10, NONE), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> NC */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> NC */ + PAD_NC(GPP_E13, NONE), + /* GPP_E15 : SRCCLK_OE8_L ==> NC */ + PAD_NC(GPP_E15, NONE), + /* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), + /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> NC */ + PAD_NC(GPP_S0, NONE), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory.c b/src/mainboard/google/brox/variants/greenbayupoc/memory.c new file mode 100644 index 0000000..c8a193f --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/memory.c @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/gpio.h> +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg ddr4_mem_config = { + .type = MEM_TYPE_DDR4, + + .rcomp = { + .resistor = 100, + .targets = {50, 20, 25, 25, 25}, + }, + + .LpDdrDqDqsReTraining = 1, + + .ect = 1, + + .UserBd = BOARD_TYPE_MOBILE, + + .ddr_config = { + .dq_pins_interleaved = 0, + }, +}; + +const struct mb_cfg *__weak variant_memory_params(void) +{ + return &ddr4_mem_config; +} + +bool __weak variant_is_half_populated(void) +{ + return false; +} + +void __weak variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_DIMM_MODULE; + spd_info->smbus[0].addr_dimm[0] = 0x50; + spd_info->smbus[0].addr_dimm[1] = 0x51; + spd_info->smbus[1].addr_dimm[0] = 0x52; + spd_info->smbus[1].addr_dimm[1] = 0x53; +} diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk b/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk deleted file mode 100644 index eace2e4..0000000 --- a/src/mainboard/google/brox/variants/greenbayupoc/memory/Makefile.mk +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. - -SPD_SOURCES = placeholder diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt deleted file mode 100644 index 2e0f37a..0000000 --- a/src/mainboard/google/brox/variants/greenbayupoc/memory/dram_id.generated.txt +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-or-later -# This is an auto-generated file. Do not edit!! -# Generated by: -# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brox/variants/brox/memory src/mainboard/google/brox/variants/brox/memory/mem_parts_used.txt - -DRAM Part Name ID to assign diff --git a/src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt deleted file mode 100644 index 2499005..0000000 --- a/src/mainboard/google/brox/variants/greenbayupoc/memory/mem_parts_used.txt +++ /dev/null @@ -1,11 +0,0 @@ -# This is a CSV file containing a list of memory parts used by this variant. -# One part per line with an optional fixed ID in column 2. -# Only include a fixed ID if it is required for legacy reasons! -# Generated IDs are dependent on the order of parts in this file, -# so new parts must always be added at the end of the file! -# -# Generate an updated Makefile.mk and dram_id.generated.txt by running the -# part_id_gen tool from util/spd_tools. -# See util/spd_tools/README.md for more details and instructions. - -# Part Name diff --git a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb index ee65135..fec3776 100644 --- a/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb +++ b/src/mainboard/google/brox/variants/greenbayupoc/overridetree.cb @@ -1,14 +1,204 @@ fw_config - field STORAGE 0 1 + field RETIMER 0 1 + option RETIMER_UNKNOWN 0 + option RETIMER_BYPASS 1 + option RETIMER_JHL8040 2 + end + field STORAGE 2 3 option STORAGE_UNKNOWN 0 option STORAGE_UFS 1 option STORAGE_NVME 2 end + field WIFI_BT 4 4 + option WIFI_BT_CNVI 0 + option WIFI_BT_PCIE 1 + end + field AUDIO 5 7 + option AUDIO_UNKNOWN 0 + option AUDIO_REALTEK_ALC256 1 + end + field UFC 8 9 + option UFC_NONE 0 + option UFC_OV2740 1 + end + field ISH 21 + option ISH_DISABLE 0 + option ISH_ENABLE 1 + end end chip soc/intel/alderlake - + register "usb3_ports[0]" = "USB3_PORT_EMPTY" # Disable UDB3 Port + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A port A0(DCI) device domain 0 on + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 + register "device[3].name" = ""DD03"" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port3 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (DCI)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (DCI)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port3 on end + end + end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 3 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 3, + .clk_src = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + probe STORAGE STORAGE_NVME + end + device ref pcie_rp5 on + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_03" + register "add_acpi_dma_property" = "true" + device pci 00.0 on + probe WIFI_BT WIFI_BT_PCIE + end + end + chip soc/intel/common/block/pcie/rtd3 + # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" + register "srcclk_pin" = "1" + device generic 0 on end + end + probe WIFI_BT WIFI_BT_PCIE + end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + probe WIFI_BT WIFI_BT_CNVI + end + device ref smbus on end end - end diff --git a/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c b/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c new file mode 100644 index 0000000..b468320 --- /dev/null +++ b/src/mainboard/google/brox/variants/greenbayupoc/ramstage.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <device/pci_ids.h> + +const struct cpu_power_limits limits[] = { + /* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, pl4 */ + /* All values are for performance config as per document #686872 */ + { PCI_DID_INTEL_RPL_P_ID_1, 45, 18000, 45000, 115000, 115000, 210000 }, + { PCI_DID_INTEL_RPL_P_ID_2, 28, 10000, 28000, 64000, 64000, 126000 }, + { PCI_DID_INTEL_RPL_P_ID_3, 15, 6000, 15000, 55000, 55000, 114000 }, +}; + +void variant_devtree_update(void) +{ + size_t total_entries = ARRAY_SIZE(limits); + variant_update_power_limits(limits, total_entries); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/82085?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1552cadfa81c48fe561947ded078bcca2e6bc6ad Gerrit-Change-Number: 82085 Gerrit-PatchSet: 1 Gerrit-Owner: Eren Peng <peng.eren(a)inventec.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: arch/arm/eabi_compat.c: fix warnings of macros
by Arthur Heymans (Code Review) 25 Apr '24

25 Apr '24

Attention is currently required from: Integral. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/82072?usp=email ) Change subject: arch/arm/eabi_compat.c: fix warnings of macros ...................................................................... Patch Set 1: (1 comment) File src/arch/arm/eabi_compat.c: https://review.coreboot.org/c/coreboot/+/82072/comment/72f8f573_82a316bd : PS1, Line 8: __used This does not exist? -- To view, visit https://review.coreboot.org/c/coreboot/+/82072?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I232f011ba0567af78c69eb8f73366b03d29c2839 Gerrit-Change-Number: 82072 Gerrit-PatchSet: 1 Gerrit-Owner: Integral <integral(a)member.fsf.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Integral <integral(a)member.fsf.org> Gerrit-Comment-Date: Thu, 25 Apr 2024 05:22:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
by Appukuttan V K (Code Review) 25 Apr '24

25 Apr '24

Attention is currently required from: Arthur Heymans, Subrata Banik, Wonkyu Kim. Hello Andrey Petrov, Ronak Kanabar, Subrata Banik, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81661?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Code-Review+1 by Subrata Banik, Code-Review+1 by Wonkyu Kim, Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned ...................................................................... drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned - Stack alignment: 1. FSP functions must be called with the stack 16-bytes aligned in x86_64 mode.This is already setup properly with the default value of the `mpreferred-stack-boundary' compiler option (4). Similarly for x86_32 it is set to 2 through compiler option. 2. The FSP heap buffer supplied by coreboot through the `StackBase' UPD must be 16-bytes aligned for x86_64 and 4-bytes aligned for x86_32. BUG=b:329034258 TEST=Verified on Meteor Lake board (Rex) Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com> --- M src/drivers/intel/fsp2_0/memory_init.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/81661/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/81661?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c Gerrit-Change-Number: 81661 Gerrit-PatchSet: 13 Gerrit-Owner: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newpatchset

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