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Change subject: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
......................................................................
Patch Set 12:
(1 comment)
File src/drivers/intel/fsp2_0/memory_init.c:
https://review.coreboot.org/c/coreboot/+/81661/comment/0625ec23_05b78953 :
PS10, Line 38: sizeof(uint64_t)
> Yes. Tried x32 with bot 4 and 8 alignment in rex system. […]
Updated to 4 for x86_32 as it is the optimum value.
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Hello Andrey Petrov, Ronak Kanabar, Subrata Banik, Wonkyu Kim, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
......................................................................
drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
- Stack alignment:
1. FSP functions must be called with the stack 16-bytes aligned
in x86_64 mode.This is already setup properly with the default
value of the `mpreferred-stack-boundary' compiler option (4).
Similarly for x86_32 it is set to 2 through compiler option.
2. The FSP heap buffer supplied by coreboot through the `StackBase'
UPD must be 16-bytes aligned for x86_64 and 4-bytes aligned for
x86_32.
BUG=b:329034258
TEST=Verified on Meteor Lake board (Rex)
Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c
Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com>
---
M src/drivers/intel/fsp2_0/memory_init.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/81661/12
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Change subject: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
......................................................................
Patch Set 11: Code-Review+1
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Change subject: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81661/comment/e437b26b_82936a17 :
PS10, Line 15: stack
> It's a heap really...
Done
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to look at the new patch set (#11).
Change subject: drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
......................................................................
drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned
- Stack alignment:
1. FSP functions must be called with the stack 16-bytes aligned.
This is already setup properly with the default value of the
`mpreferred-stack-boundary' compiler option (4).
2. The FSP heap buffer supplied by coreboot through the `StackBase'
UPD must be 16-bytes aligned.
BUG=b:329034258
TEST=Verified on Meteor Lake board (Rex)
Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c
Signed-off-by: Appukuttan V K <appukuttan.vk(a)intel.com>
---
M src/drivers/intel/fsp2_0/memory_init.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/81661/11
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Change subject: soc/mediatek/mt8188: devapc: set devapc permission for MFG
......................................................................
Patch Set 4: Code-Review+1
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Change subject: soc/mediatek/mt8188: devapc: set devapc permission for MFG
......................................................................
Patch Set 4: Code-Review+1
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82076/comment/2706c4e9_6774de19 :
PS2, Line 7: UPSTREAM
> Remove `UPSTREAM:`.
Done
https://review.coreboot.org/c/coreboot/+/82076/comment/84205b63_c82dfe74 :
PS2, Line 9: Set MFG to domain 6.
> No need to start a new line for each sentence.
Done
https://review.coreboot.org/c/coreboot/+/82076/comment/cf0dc02b_7a63b20a :
PS2, Line 14: So that only AP in secure mode can access MFG_S_S-2 and MFG_S_S-5
> Missing `.` at the end.
Done
https://review.coreboot.org/c/coreboot/+/82076/comment/fea6bab4_86c00134 :
PS2, Line 13: .
: So
> , so
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/82076/comment/a2a68f36_6975a458 :
PS3, Line 9: Set MFG to domain 6.
: Set MFG remap in infra and sub infra, so that MFG can switch to protect mode by MFG register.
: Set MFG slave MFG_S_S-2 and MFG_S_S-5 permission from NO_PROTECTION to SEC_RW_ONLY for domain 0,
: so that only AP in secure mode can access MFG_S_S-2 and MFG_S_S-5.
> 72 characters per line for the commit message.
Done
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Change subject: soc/mediatek/mt8188: devapc: set devapc permission for MFG
......................................................................
soc/mediatek/mt8188: devapc: set devapc permission for MFG
Set MFG to domain 6.
Set MFG remap, so that MFG can switch to protect mode by MFG register.
Change MFG slave permission NO_PROTECTION -> SEC_RW_ONLY for domain 0,
so that only AP in secure mode can access MFG_S_S-2 and MFG_S_S-5.
BUG=b:313855815
TEST=emerge-geralt coreboot
Change-Id: Ic6fb7d85bf9d4d92946a045a274b274abc440e1d
Signed-off-by: Fei Yan <fei.yan(a)mediatek.corp-partner.google.com>
---
M src/soc/mediatek/mt8188/devapc.c
M src/soc/mediatek/mt8188/include/soc/addressmap.h
M src/soc/mediatek/mt8188/include/soc/devapc.h
3 files changed, 55 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/82076/4
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