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Change subject: soc/mediatek/mt8188: devapc: set devapc permission for MFG
......................................................................
Patch Set 4:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82076/comment/23b2aaee_937c6984 :
PS4, Line 11: NO_PROTECTION -> SEC_RW_ONLY
from NO_PROTECTION to SEC_RW_ONLY
File src/soc/mediatek/mt8188/devapc.c:
https://review.coreboot.org/c/coreboot/+/82076/comment/e039eb8a_465bc14d :
PS4, Line 1787: protected
protection mode ?
https://review.coreboot.org/c/coreboot/+/82076/comment/01905fe0_2a7fa6ff :
PS4, Line 1789: 0
Please define this offset. For example: MAS_DOM_1, SCP_DOM0.
File src/soc/mediatek/mt8188/include/soc/devapc.h:
https://review.coreboot.org/c/coreboot/+/82076/comment/b61b9ace_711deb7d :
PS4, Line 52: MFG_NS_DOM
Use the lowercase.
Is the naming correct ? It looks like you have both secure and non-secure values.
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Change subject: mb/google/corsola: Add initialization of USB port0 for Wugtrio
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Please invite MTK USB expert to join the review.
(Or we can review the patch on Google Gerrit first.)
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
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Patch Set 56:
(1 comment)
File src/soc/intel/xeon_sp/chip_gen6.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/150ce3b7_0e720a53 :
PS53, Line 57: IORESOURCE_SUBTRACTIVE
> I'm OK with leaving it like this for now, but I'll ask around on what the correct way to deal with t […]
Sure, let us sync this later and decide whether need to move to revise pch/lpc codes as well.
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Change subject: soc/intel/mtl: use different names per mtlrvp variants
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82084/comment/823e408e_e259aeb3 :
PS2, Line 17:
Fix "No Signed-off-by line in commit message"
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
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Patch Set 56:
(1 comment)
File src/soc/intel/xeon_sp/chip_gen6.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/9e7f35a5_a2713396 :
PS53, Line 57: IORESOURCE_SUBTRACTIVE
> At a second think, I think to set subtractive might be reasonable. […]
I'm OK with leaving it like this for now, but I'll ask around on what the correct way to deal with this is.
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Change subject: soc/intel/xeon_sp/gnr: Use OCP_VPD drivers
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Patch Set 44:
(1 comment)
Patchset:
PS44:
I made https://review.coreboot.org/c/coreboot/+/82090 and let us discuss there.
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Change subject: MAINTAINERS: Add Granite Rapids FSP to Xeon-SP
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82082/comment/60830ecc_891ce914 :
PS2, Line 7: into
> add … to?
Done
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
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Patch Set 55:
(3 comments)
File src/soc/intel/xeon_sp/chip_gen6.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/9f38186a_b11deb63 :
PS53, Line 57: IORESOURCE_SUBTRACTIVE
> I agree with you. Updated. This cannot be counted as subtractive decoding. […]
At a second think, I think to set subtractive might be reasonable. The intention is to mark that, the whole legacy IO range (0x0000-0x1000) it is treated in subtractive way and handled behind a subtractive decoding bridge. However, as to whether an address will be responded is decided by whether there is a child device responsible behind that bridge, e.g. 0x60/0x64, 0x62/0x66, 0x3f8, 0x2f8, et al ... However, if we remove the subtractive tag, it means the whole 0x0000-0x1000 will be certainly handled by some devices, we cannot be guaranteed by the SoC itself. Hence I tentatively add the flag back here.
P.S. We might move the 0x0000-0x1000 subtractive range declaration to PCH/IBL codes , which could be handled in a separate patch later.
P.S. For the lpc driver (src/soc/intel/common/block/lpc/lpc.c) IMO it should be also with the subtractive flag for 0x0000-0x1000. However, this could be a separate thread.
File src/soc/intel/xeon_sp/gnr/cpu.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/62b33c08_6c3d7233 :
PS53, Line 87: return num_virts * soc_get_num_cpus();
> Maybe add a comment, because it might be confusing seeing the value in the log message, but then see […]
Done
https://review.coreboot.org/c/coreboot/+/81316/comment/ed834f7d_4755154a :
PS53, Line 114: printk(BIOS_ERR, "microcode not found in CBFS!\n");
> The log level should match then? The other log message could also be extended to say, that no update […]
Done
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