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Change subject: bsd/cbfs_serialized: Check the cbfs_file size also when using clang
......................................................................
Patch Set 3: Code-Review-1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/82009/comment/5ac8f924_ea3896a9 :
PS3, Line 7: clang
clang also defined \_\_GNUC\_\_
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 53:
(1 comment)
File src/soc/intel/xeon_sp/gnr/chipset.cb:
https://review.coreboot.org/c/coreboot/+/81316/comment/0abccc65_947d9416 :
PS53, Line 10: .chipset_lockdown = CHIPSET_LOCKDOWN_FSP,
> I'm OK with temporarily using FSP lockdown, as it simplifies initial bring-up. […]
Sounds good to me. Done.
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 53:
(2 comments)
File src/soc/intel/xeon_sp/chip_gen6.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/fdb37aa0_f450d4e8 :
PS53, Line 38: int
> I think the resource API uses `int` everywhere for some reason. […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/81316/comment/2163f3c7_7776760f :
PS53, Line 52: HOB
> I doubt it'll change. […]
Acknowledged. Let’s discuss this in your comment
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Change subject: arch/io.h: Add stubs for x86 I/O port functions to other arches
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80372/comment/86e4f6ea_8f579022 :
PS3, Line 19: We could cover every port function call with #if CONFIG(ARCH_X86), but
: that gets very cluttery. And it looks like it might be possible to
: somehow access to I/O ports over MMIO, as far as I can tell from U-Boot
: and Linux code.
> The hardware often has a translator. […]
Done (but I'll update the patch later)
File src/arch/arm/include/armv7/arch/io.h:
https://review.coreboot.org/c/coreboot/+/80372/comment/f61d5f23_b305942c :
PS3, Line 17: printk(BIOS_ERR, "arch/io.h: %s() not implemented\n", __func__);
> > But we could replace all the open-coded res->flags & RESOURCE_IO checks with a static inline helpe […]
Done for this patch, if I correctly understood the "no implementation" part. But I've actually managed to get a working implementation and will update this change with that, I simply pushed v4 so the code doesn't get lost in my computer.
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 53:
(3 comments)
File src/soc/intel/xeon_sp/chip_gen6.c:
https://review.coreboot.org/c/coreboot/+/81316/comment/53b59ab8_1dd835ce :
PS53, Line 38: int
> unsigned int?
I think the resource API uses `int` everywhere for some reason. If anything, would be best to be consistent (if we're going to use `unsigned int` for resource index, let's do so everywhere).
https://review.coreboot.org/c/coreboot/+/81316/comment/10a37d7e_0fe2d803 :
PS53, Line 52: HOB
> Could the HOB behavior change? If so, mention the version? […]
I doubt it'll change. It doesn't make sense to rely on FSP for this kind of information anyway (see my comment below; coreboot usually controls what is enabled within this range).
https://review.coreboot.org/c/coreboot/+/81316/comment/84c33483_07c17b86 :
PS53, Line 57: IORESOURCE_SUBTRACTIVE
Is this actually a subtractive resource? I think various platforms in coreboot get this wrong.
AIUI, this is a catch-all resource for the various things the southbridge/PCH can place in this range, e.g. LPC-forwarded fixed I/O ranges (e.g. 0x60/0x64, 0x62/0x66, 0x3f8, 0x2f8... It's the `LPC_EN` register on older platforms), CMOS access registers... I forget, the list is pretty long. But this is not at all subtractive decoding.
It's https://github.com/coreboot/coreboot/blob/main/src/southbridge/intel/lynxpo… except for the generic decode ranges (those are handled separately as they can be anywhere in I/O space). (Note: I think Lynxpoint also does this wrong and reports this resource as subtractive).
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Hello Arthur Heymans, Julius Werner, Nico Huber, Philipp Hug, build bot (Jenkins), ron minnich,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80372?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Code-Review+1 by Arthur Heymans, Verified+1 by build bot (Jenkins)
Change subject: arch/io.h: Add stubs for x86 I/O port functions to other arches
......................................................................
arch/io.h: Add stubs for x86 I/O port functions to other arches
The QEMU Bochs display driver and the QEMU Firmware Configuration
interface code (in the qemu-i440fx mainboard dir) were written for x86.
These devices are available in QEMU VMs of other architectures as well,
so we want to port them to be independent from x86.
The Bochs display driver already has an interesting pattern of using a
resource struct to choose whether to use I/O port instructions or MMIO.
We could simply continue with the MMIO code path on non-x86 arches, but
the x86-specific instructions cause a compile error on the other branch
since the I/O port access functions aren't declared.
We could cover every port function call with #if CONFIG(ARCH_X86), but
that gets very cluttery. And often it is possible to access I/O ports
over MMIO through a translator, so these could be implemented later.
For now, add unimplemented prototypes for these functions for all other
architectures where they are missing, so that we can compile code that
refer to them in unreachable code paths. If the function calls can't be
eliminated at build-time, the build will fail with linker errors.
Change-Id: If7d9177283e8c692088ba8e30d6dfe52623c8cb9
Signed-off-by: Alper Nebi Yasak <alpernebiyasak(a)gmail.com>
---
A src/arch/arm/include/armv4/arch/io.h
A src/arch/arm/include/armv7/arch/io.h
A src/arch/arm64/include/armv8/arch/io.h
A src/arch/riscv/include/arch/io.h
4 files changed, 132 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/80372/4
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 53:
(3 comments)
File src/soc/intel/xeon_sp/gnr/chipset.cb:
https://review.coreboot.org/c/coreboot/+/81316/comment/d04b852b_191ff29f :
PS53, Line 10: .chipset_lockdown = CHIPSET_LOCKDOWN_FSP,
> In a server platform many silicon specific register lock ops are by default in FSP space, hence we s […]
I'm OK with temporarily using FSP lockdown, as it simplifies initial bring-up. But I believe it's best to switch to coreboot lockdown in the long run.
https://review.coreboot.org/c/coreboot/+/81316/comment/d0e87f63_72227097 :
PS53, Line 18: ibl
Out of curiosity, what does "ibl" mean?
https://review.coreboot.org/c/coreboot/+/81316/comment/9f21ff12_cf40ba1c :
PS53, Line 19: HEPT
typo: HPET
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Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email )
Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
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Patch Set 53:
(1 comment)
File src/soc/intel/xeon_sp/gnr/chipset.cb:
https://review.coreboot.org/c/coreboot/+/81316/comment/034683b9_0f4a9824 :
PS53, Line 10: .chipset_lockdown = CHIPSET_LOCKDOWN_FSP,
> Just wondering. Why is that the default? coreboot does the lockdown for all other Intel platforms.
In a server platform many silicon specific register lock ops are by default in FSP space, hence we start from such a solution to make sure the codes could be used out-of-box to build products.
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