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Change subject: lib/device_tree: Add some FDT helper functions
......................................................................
lib/device_tree: Add some FDT helper functions
This adds some helper functions for FDT, since more and more mainboards
seem to need FDT nowadays. For example our QEMU boards need it in order
to know how much RAM is available. Also all RISC-V boards in our tree
need FDT.
This also adds some tests in order to test said functions.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8
---
M src/include/device_tree.h
M src/lib/device_tree.c
M tests/lib/Makefile.mk
A tests/lib/device_tree-test.c
A tests/lib/tegra30-ouya.dtb.xxd
A tests/lib/virt.dtb.xxd
M util/lint/lint-000-license-headers
7 files changed, 14,250 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81081/17
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Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81611?usp=email )
Change subject: Documentation: Add Erying Polestar G613 Pro
......................................................................
Documentation: Add Erying Polestar G613 Pro
Documentation entry has to be submitted with board tree that's currently
being reviewed upstream.
Change-Id: I5d60508dbde10373b0da2fb4ece0992760d3121c
Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com>
---
A Documentation/mainboard/erying/tgl_matx.md
A Documentation/mainboard/erying/tgl_matx_board.jpg
M Documentation/mainboard/index.md
3 files changed, 144 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/81611/1
diff --git a/Documentation/mainboard/erying/tgl_matx.md b/Documentation/mainboard/erying/tgl_matx.md
new file mode 100644
index 0000000..d3d7f82
--- /dev/null
+++ b/Documentation/mainboard/erying/tgl_matx.md
@@ -0,0 +1,136 @@
+# Erying Polestar G613 Pro
+
+This page describes how to run coreboot on the [Erying Polestar G613 Pro].
+
+![](tgl_matx_board.jpg)
+
+## Required proprietary blobs
+
+To build full working image of coreboot, the following blobs are required:
+
+```{eval-rst}
++-----------------+---------------------------------+----------------------+
+| Binary file | Apply | Required / Optional |
++=================+=================================+======================+
+| Microcode | CPU Microcode | Required (see notes) |
++-----------------+---------------------------------+----------------------+
+| FSP-M & FSP-S | Intel Firmware Support Package | Required |
++-----------------+---------------------------------+----------------------+
+| ME | Intel Management Engine | Required (see notes) |
++-----------------+---------------------------------+----------------------+
+| FD | Intel Flash Descriptor | Optional (if SI_BIOS)|
++-----------------+---------------------------------+----------------------+
+```
+
+Microcode for those SoCs cannot be generated from the tree.
+While boards with D1 (production) stepping may work, microcode Intel had
+included in their tree is too old, which causes issues with APIC
+(Advanced Programmable Interrupt Controller), resulting in overal instability.
+
+This is **required** for boards sold with D0 SoC revision (Engineering Sample).
+Maintainer of this port had included publicly-available [microcodes] in
+`3rdparty/blobs` coreboot repository, which are being pulled as submodule.
+
+To choose appropriate microcode for your system, you should choose:
+1. If your motherboard uses Engineering Sample (D0) stepping:
+- cpu806D0_platC2_ver00000054_2021-05-07_PRD_B0F9E245.bin
+2. If your motherboard uses retail (D1) stepping:
+- cpu806D1_platC2_ver00000046_2023-02-27_PRD_08E6188A.bin
+
+Failure to choose an appropriate microcode may result in:
+- Bricked (unbootable) board
+- Issues with APIC, resulting in random freezes
+- MCE (Machine Check Exception) errors
+- Unstable system RAM, leading to bit flips and data corruption
+
+There are no extra steps required for FSP.
+Both SKUs work perfectly with FSP Intel publishes in their public repository.
+Coreboot automatically pulls FSP binary from `3rdparty/fsp` submodule at build
+time, which points to TigerLakeFspBinPkg/Client package in official
+Intel FSP repository.
+
+## Flashing coreboot
+
+### Internally
+
+Vendor of this motherboard hasn't locked any flash regions, resulting in
+[flashrom] having full access to the SPI chip.
+Assuming that user had booted Linux with `iomem=relaxed`, they can:
+- flash coreboot from stock firmware
+- flash stock firmware from coreboot
+- update coreboot build to a newer version
+
+Without opening the case and connecting the SPI flasher.
+Please note that for TigerLake Halo platform you will need to use
+[flashrom] v1.3.0 or newer, as older versions won't detect the chipset.
+
+### Externally
+
+SPI chip on this motherboard is located right underneath the PCH heatsink.
+Due to it's location, it's likely that you will need to move (or remove) the
+PCH (Platform Controller Hub) heatsink in order to clip the chip properly.
+
+Vendor populated this board with Winbond W25Q128FV chip in SOIC-8 package.
+Although the stock chip is 16MiB, it is possible to replace it with 32MiB
+equivalent if user desires to use LinuxBoot payload instead of EDK2.
+
+Please note that SPI voltage on this board is standard 3.3V, despite using mobile SoC and PCH.
+
+## Tested and working
+
+- RS232 serial output from IT8613E for debugging (cbmem, Linux)
+- Fan control from userspace (IT8613E Environment Controller)
+- USB2.0 and 3.0
+- HDMI (iGPU, including audio)
+- Realtek RTL8111 (GbE NIC)
+- Realtek ALC897 (integrated audio)
+- PCI-E x16 4.0 (SoC)
+- M.2 x4 4.0 (SoC)
+- M.2 x3 3.0 (PCH)
+- 4x SATA3 ports
+- IOMMU/VT-x (PCI-E passthrough)
+- PCI-E ReBAR (Resizable BAR)
+
+## Work in progress/broken/issues
+
+- XMP Profiles (memory controller in pre-production silicon causes instability)
+- GPU GOP (most EDK2 branches don't include module to load external OpROMs)
+- Sleep states (also broken on stock, system loses RAM power in S3 state)
+- USB3.2 might take few tries to get detected at full speed
+- iGPU DisplayPort (simple fix, need to re-configure GPIOs)
+- Automatic fan control (fans will always spin at 50%)
+- 2x USB2.0 FP and M.2 NGFF USB2.0 not mapped (yet)
+- PCI-E ASPM (results in AER spam in dmesg)
+- M.2 NGFF (WiFi) - untested, should work
+- Intel PTT (fTPM)
+
+Please ensure to:
+- Disable sleep state in your OS to prevent data loss
+- Configure automatic fan control using pwmconfig (`modprobe it87 force_id=0x8603)
+
+## Notes
+- Intel Management Engine blob is required, as it manages: PMC (Power Management Controller), SA (System Agent), USB Controller and many more.
+System Agent manages critical components, such as memory controller or PCI-E lane bifurfication. Therefore, system will simply not POST without this blob present in the build.
+Blob included in `3rdparty/blobs` have been extracted from stock firmware and has "clean" state.
+
+## Specification
+
+```{eval-rst}
++------------------+------------------------------+
+| SoC | Intel TigerLake Halo |
++------------------+------------------------------+
+| PCH | Intel HM570 |
++------------------+------------------------------+
+| Super I/O | ITE IT8613E |
++------------------+------------------------------+
+| SPI | Winbond W25Q128FV 16MiB 3.3V |
++------------------+------------------------------+
+| NIC | Realtek RTL8111 |
++------------------+------------------------------+
+| Audio | Realtek ALC897 |
++------------------+------------------------------+
+```
+
+[Erying Polestar G613 Pro]: https://www.erying.cc/products-detail/id-97.html
+[microcodes]: https://github.com/platomav/CPUMicrocodes/tree/master/Intel
+[flashrom]: https://flashrom.org/Flashrom
diff --git a/Documentation/mainboard/erying/tgl_matx_board.jpg b/Documentation/mainboard/erying/tgl_matx_board.jpg
new file mode 100644
index 0000000..e0f2eed
--- /dev/null
+++ b/Documentation/mainboard/erying/tgl_matx_board.jpg
Binary files differ
diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md
index 6178738..b016fce 100644
--- a/Documentation/mainboard/index.md
+++ b/Documentation/mainboard/index.md
@@ -94,6 +94,14 @@
QEMU POWER9 <emulation/qemu-power9.md>
```
+## Erying
+
+```{toctree}
+:maxdepth: 1
+
+Polestar G613 Pro <erying/tgl_matx.md>
+```
+
## Facebook
```{toctree}
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Hello Jakub Czapiga, Julius Werner, Martin L Roth, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: lib/device_tree: Add some FDT helper functions
......................................................................
lib/device_tree: Add some FDT helper functions
This adds some helper functions for FDT, since more and more mainboards
seem to need FDT nowadays. For example our QEMU boards need it in order
to know how much RAM is available. Also all RISC-V boards in our tree
need FDT.
This also adds some tests in order to test said functions.
Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com>
Change-Id: I2fb1d93c5b3e1cb2f7d9584db52bbce3767b63d8
---
M src/include/device_tree.h
M src/lib/device_tree.c
M tests/lib/Makefile.mk
A tests/lib/device_tree-test.c
A tests/lib/tegra30-ouya.dtb.xxd
A tests/lib/virt.dtb.xxd
6 files changed, 14,248 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/81081/15
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/screebo: Add FW_CONFIG and device for VPU
......................................................................
mb/google/screebo: Add FW_CONFIG and device for VPU
BUG=b:332488817
TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0)
is enabled when bit20 is set, and disabled when cleared
Change-Id: I6d7b35dbf8ac9b0abb42f64a947b4bb94f3c6b0f
Signed-off-by: Jamie Ryu <jamie.m.ryu(a)intel.com>
---
M src/mainboard/google/rex/variants/screebo/overridetree.cb
1 file changed, 7 insertions(+), 0 deletions(-)
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Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81375?usp=email )
Change subject: acpi: Add acpigen_write_OSC_pci_domain
......................................................................
Patch Set 19:
(2 comments)
Patchset:
PS19:
Please consider moving this back to `soc/intel/`. The code seems to be tailored to
a specific, downstream (? at least, I couldn't find it in upstream Linux) interpre-
tation of a non-public spec (probably outdated, I've seen a patch somewhere that
stated the CXL UUID used here is not to be used).
Also, the design doesn't look like our usual acpigen code which normally isn't coupled
that closely to other code (i.e. no callbacks, more simple building blocks instead of
long procedures with a lot of `if`s).
File src/acpi/acpigen_pci.c:
https://review.coreboot.org/c/coreboot/+/81375/comment/10bbf85b_551d027e :
PS12, Line 348: __weak unsigned long get_granted_pci_features(const struct device *domain)
: {
: return 0;
: }
:
: __weak unsigned long get_granted_cxl_features(const struct device *domain)
: {
: return 0;
: }
> refer to: PCI firmware specification, revision 3.1 […]
This explains what would happen not why it would make sense to generate all the code
in a no-op state (when the functions aren't overridden). I still don't understand why
there are weak implementations.
Thinking about it further, why are there callbacks at all? With the `const` for the
parameter, the API even suggests that the devicetree wouldn't change because of a call.
So further calls should still behave the same and then you could just have passed the
feature mask as an argument to acpigen_write_OSC_pci_domain().
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Change subject: soc/intel/alderlake: Set PL1 Time to Intel default 56s for certain CPUs
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
Patchset:
PS3:
Needs a rebase (an ADL N SKU was added in the meantime)
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Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
Patch Set 30:
(1 comment)
Patchset:
PS30:
> Can you please check this for 1 above ? https://review.coreboot.org/c/coreboot/+/81630
please make sure the code is builable/bootable with 32-bit and 64-bit recipe in MTL
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
Patch Set 35:
(1 comment)
File src/soc/intel/xeon_sp/gnr/acpi/platform.asl:
https://review.coreboot.org/c/coreboot/+/81316/comment/d6c448d9_87017b9f :
PS33, Line 6: Name (_S0, Package () // mandatory system state
: {
: 0x00, 0x00, 0x00, 0x00
: })
:
: Name (_S5, Package () // mandatory system state
: {
: 0x07, 0x00, 0x00, 0x00
: })
> diff --git a/src/southbridge/intel/common/acpi/sleepstates. […]
I removed the platform.asl first from this patch.
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Change subject: drivers/intel/fsp2_0: Support FSP 2.4 64-bits
......................................................................
Patch Set 30:
(1 comment)
Patchset:
PS30:
> can you please try to split this changes to first accommodate […]
Can you please check this for 1 above ? https://review.coreboot.org/c/coreboot/+/81630
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