coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: include/efi: Introduce __efiapi for EFI calling convention flexibility
by Dinesh Gehlot (Code Review) 03 Apr '24

03 Apr '24

Attention is currently required from: Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81620?usp=email ) Change subject: include/efi: Introduce __efiapi for EFI calling convention flexibility ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I21660f8ebeed3b9ef060118928a940a470492bb8 Gerrit-Change-Number: 81620 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Wed, 03 Apr 2024 05:27:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: riscv/opensbi: make the opensbi payload a flat binary
by ron minnich (Code Review) 03 Apr '24

03 Apr '24

Attention is currently required from: Arthur Heymans, Jonathan Neuschäfer, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Jonathan Neuschäfer, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81632?usp=email to look at the new patch set (#4). Change subject: riscv/opensbi: make the opensbi payload a flat binary ...................................................................... riscv/opensbi: make the opensbi payload a flat binary opensbi is now self-relocating and, further, has strict requirements on the alignment of the data segment -- it has to be power of 2. As opposed to trying to play too many games with ELF files and ldscripts, taking them beyond what's possible, it is simplest just to unpack the opensbi elf into a flat binary and specify its location in cbfs. Change-Id: I31525125e87ff5925ca82f4e48fe1191ba6326fd Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/Makefile.mk M src/mainboard/emulation/qemu-riscv/memlayout.ld 2 files changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/81632/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31525125e87ff5925ca82f4e48fe1191ba6326fd Gerrit-Change-Number: 81632 Gerrit-PatchSet: 4 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: riscv/opensbi: make the opensbi payload a flat binary
by ron minnich (Code Review) 03 Apr '24

03 Apr '24

Attention is currently required from: Arthur Heymans, Jonathan Neuschäfer, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Jonathan Neuschäfer, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81632?usp=email to look at the new patch set (#3). Change subject: riscv/opensbi: make the opensbi payload a flat binary ...................................................................... riscv/opensbi: make the opensbi payload a flat binary opensbi is now self-relocating and, further, has strict requirements on the alignment of the data segment -- it has to be power of 2. As opposed to trying to play too many games with ELF files and ldscripts, taking them beyond what's possible, it is simplest just to unpack the opensbi elf into a flat binary and specify its location in cbfs. Change-Id: I31525125e87ff5925ca82f4e48fe1191ba6326fd Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/Makefile.mk M src/mainboard/emulation/qemu-riscv/memlayout.ld 2 files changed, 7 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/81632/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31525125e87ff5925ca82f4e48fe1191ba6326fd Gerrit-Change-Number: 81632 Gerrit-PatchSet: 3 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: lib: Refactor bmp_load_logo() implementation
by Subrata Banik (Code Review) 03 Apr '24

03 Apr '24

Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Julius Werner, Matt DeVillier, Ronak Kanabar, Sean Rhodes. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81618?usp=email ) Change subject: lib: Refactor bmp_load_logo() implementation ...................................................................... Patch Set 4: (2 comments) File src/drivers/intel/fsp1_1/ramstage.c: https://review.coreboot.org/c/coreboot/+/81618/comment/ab83d0db_f8df3050 : PS3, Line 81: uint32_t > Yes, that. The cast to `uint32_t` is optional but the other one is not. Acknowledged File src/drivers/intel/fsp2_0/fsp_gop_blt.c: https://review.coreboot.org/c/coreboot/+/81618/comment/8841bed5_37f9905e : PS3, Line 241: logo_size_t > I think it would be cleaner to change the type for `logo_ptr_size` here already tbh. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/81618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14bc54670a67980ec93bc366b274832d1f959e50 Gerrit-Change-Number: 81618 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 03 Apr 2024 04:11:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t
by Subrata Banik (Code Review) 03 Apr '24

03 Apr '24

Attention is currently required from: Andrey Petrov, Elyes Haouas, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Paul Menzel, Ronak Kanabar, Subrata Banik. Hello Andrey Petrov, Elyes Haouas, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Paul Menzel, Ronak Kanabar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81615?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Code-Review+1 by Elyes Haouas, Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t ...................................................................... drivers/intel/fsp2_0: Enhance portability with uintptr_t/size_t Replace fixed-width integers for pointers and sizes with uintptr_t and size_t, promoting portability across 32-bit and 64-bit architectures. For FSP-API specific UPD assignments, rely on `efi_uintn_t` rather fixed size datatype uint32_t/uint64_t. BUG=b:242829490 TEST=Firmware splash screen visible on google/rex0 w/ both 32-bit and 64-bit compilation. Change-Id: Iab5c612e0640441a2a10e77949416de2afdb8985 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp2_0/fsp_gop_blt.c M src/drivers/intel/fsp2_0/include/fsp/fsp_gop_blt.h 2 files changed, 8 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/81615/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/81615?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab5c612e0640441a2a10e77949416de2afdb8985 Gerrit-Change-Number: 81615 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: lib: Refactor bmp_load_logo() implementation
by Subrata Banik (Code Review) 03 Apr '24

03 Apr '24

Attention is currently required from: Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Ronak Kanabar, Sean Rhodes, Subrata Banik. Hello Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Ronak Kanabar, Sean Rhodes, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81618?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: lib: Refactor bmp_load_logo() implementation ...................................................................... lib: Refactor bmp_load_logo() implementation This refactoring ensures bmp_load_logo() takes logo_size as an argument, returning a valid logo_ptr only if logo_size is non-zero. This prevents potential errors from mismatched size assumption. BUG=b:242829490 TEST=google/rex0 builds successfully. Change-Id: I14bc54670a67980ec93bc366b274832d1f959e50 Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/intel/fsp1_1/ramstage.c M src/drivers/intel/fsp2_0/fsp_gop_blt.c M src/include/bootsplash.h M src/lib/bmp_logo.c M src/soc/amd/mendocino/fsp_s_params.c M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/skylake/chip.c 8 files changed, 29 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/81618/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I14bc54670a67980ec93bc366b274832d1f959e50 Gerrit-Change-Number: 81618 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Use coreboot uint8_t type for consistency
by Subrata Banik (Code Review) 03 Apr '24

03 Apr '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81571?usp=email ) Change subject: drivers/intel/fsp2_0: Use coreboot uint8_t type for consistency ...................................................................... drivers/intel/fsp2_0: Use coreboot uint8_t type for consistency This patch replaces UINT8 with uint8_t to align with coreboot's standard data type conventions. This promotes consistency within the codebase. BUG=b:242829490 TEST=Verified firmware splash screen functionality on google/rex0. Change-Id: I524bf6dc83e4330f155e21691f6b161643f29bd8 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81571 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/intel/fsp2_0/fsp_gop_blt.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified Elyes Haouas: Looks good to me, approved diff --git a/src/drivers/intel/fsp2_0/fsp_gop_blt.c b/src/drivers/intel/fsp2_0/fsp_gop_blt.c index a43364a..8b64502 100644 --- a/src/drivers/intel/fsp2_0/fsp_gop_blt.c +++ b/src/drivers/intel/fsp2_0/fsp_gop_blt.c @@ -151,7 +151,7 @@ die("%s: out of memory. Consider increasing the `CONFIG_HEAP_SIZE`\n", __func__); - bmp_image = ((UINT8 *)logo_ptr) + header->ImageOffset; + bmp_image = ((uint8_t *)logo_ptr) + header->ImageOffset; bmp_image_header = bmp_image; gop_blt_buffer = gop_blt_ptr; bmp_color_map = (efi_bmp_color_map *)(logo_ptr + sizeof(efi_bmp_image_header)); -- To view, visit https://review.coreboot.org/c/coreboot/+/81571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I524bf6dc83e4330f155e21691f6b161643f29bd8 Gerrit-Change-Number: 81571 Gerrit-PatchSet: 7 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: acpi: Add acpigen_write_OSC_pci_domain
by Shuo Liu (Code Review) 03 Apr '24

03 Apr '24

Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81375?usp=email ) Change subject: acpi: Add acpigen_write_OSC_pci_domain ...................................................................... Patch Set 19: (1 comment) Patchset: PS19: > I see. […] https://review.coreboot.org/c/coreboot/+/81652 is raised for discussion. -- To view, visit https://review.coreboot.org/c/coreboot/+/81375?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I711ce5350d718e47feb2912555108801ad7f918d Gerrit-Change-Number: 81375 Gerrit-PatchSet: 19 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 03 Apr 2024 02:14:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP
by Shuo Liu (Code Review) 03 Apr '24

03 Apr '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81652?usp=email ) Change subject: acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP ...................................................................... acpi: Move acpigen_write_OSC_pci_domain to Xeon-SP TEST=Build on intel/archercity CRB Change-Id: Ia297e0a828f25b751032f18de04ec76f10131076 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/acpi/acpigen_pci.c M src/include/acpi/acpigen_pci.h M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/include/soc/acpi.h 4 files changed, 294 insertions(+), 316 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/81652/1 diff --git a/src/acpi/acpigen_pci.c b/src/acpi/acpigen_pci.c index a23b84c..3edf0d0 100644 --- a/src/acpi/acpigen_pci.c +++ b/src/acpi/acpigen_pci.c @@ -55,308 +55,3 @@ acpigen_pop_len(); /* Package */ } - -#define PCI_HOST_BRIDGE_OSC_UUID "33db4d5b-1ff7-401c-9657-7441c03dd766" -#define CXL_HOST_BRIDGE_OSC_UUID "68f2d50b-c469-4d8a-bd3d-941a103fd3fc" - -#define OSC_RET_FAILURE 0x02 -#define OSC_RET_UNRECOGNIZED_UUID 0x04 -#define OSC_RET_UNRECOGNIZED_REV 0x08 -#define OSC_RET_CAPABILITIES_MASKED 0x10 - -#define OSC_QUERY_SUPPORT_SET 0x01 - -#define ASL_UUID_UNHANDLED 0x00 -#define ASL_UUID_HANDLED 0x01 - -static void acpigen_OSC_handle_pcie_request(const struct device *domain); -static void acpigen_OSC_handle_cxl_request(const struct device *domain); - -/* - * acpigen_write_OSC_pci_domain - * - * Reference: - * 6.2.11 in https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/06_Device_Configuration/Devic… - * - * _OSC ASL Arguments: (4) - * Arg0 - A Buffer containing a UUID - * Arg1 - An Integer containing a Revision ID of the buffer format - * Arg2 - An Integer containing a count of entries in Arg3 - * Arg3 - A Buffer containing a list of DWORD capabilities - * - * _OSC ASL Return Value: - * A Buffer containing a list of capabilities - * - * Local Variables Assignment: - * Local0 - Temp assigned - * Local1 - Temp assigned - * Local2 - Not used - * Local3 - Not used - * Local4 - Not used - * Local5 - Not used - * Local6 - Record whether the UUID is handled - * Local7 - Backs up the input value of Arg3 - * - * Field Definitions: - * Name - Width Source Offset Description - * -------------------------------- - * QSUP - DWord Local7 0x00 Query support - * RETE - DWord Arg3 0x00 Returned errors - * SUPP - Dword Arg3 0x04 PCIe Features that OS supported - * CTRL - Dword Arg3 0x08 PCIe Features that firmware grant control to OS - * OTRL - Dword Local7 0x08 PCIe Features that OS requests for control - * SUPC - Dword Arg3 0x0C CXL Features that OS supported - * CTRC - Dword Arg3 0x10 CXL Features that firmware grant control to OS - * OTRC - Dword Local7 0x10 CXL Features that OS requests for control - */ -void acpigen_write_OSC_pci_domain(const struct device *domain, const bool is_cxl_domain) -{ - /* - * Method (_OSC, 4, NotSerialized) - * { - */ - acpigen_write_method("_OSC", 4); - - /* - * // - * // Check revision ID - * // - * If (Arg1 != 1) - * { - * RETE = OSC_RET_UNRECOGNIZED_REV - * Return (Arg3) - * } - */ - acpigen_write_if(); - acpigen_emit_byte(LNOT_OP); - acpigen_emit_byte(LEQUAL_OP); - acpigen_emit_byte(ARG1_OP); - acpigen_write_integer(0x1); - - acpigen_write_store_int_to_namestr(OSC_RET_UNRECOGNIZED_REV, "RETE"); - acpigen_write_return_op(ARG3_OP); - - acpigen_write_if_end(); - - /* - * // - * // Setup up local variables - * // - * Local7 = Arg3 - * CreateDwordField (Local7, 0x00, QSUP) - * CreateDWordField (Arg3, 0x00, RETE) - * RETE = 0x0 - * Local6 = ASL_UUID_UNHANDLED - */ - acpigen_write_store_ops(ARG3_OP, LOCAL7_OP); - acpigen_write_create_dword_field(LOCAL7_OP, 0x00, "QSUP"); - acpigen_write_create_dword_field(ARG3_OP, 0x00, "RETE"); - acpigen_write_store_int_to_namestr(0x0, "RETE"); - acpigen_write_store_int_to_op(ASL_UUID_UNHANDLED, LOCAL6_OP); - - /* - * // - * // Refer to CXL-3.1-Specification, 9.18.2 - * // A CXL Host Bridge also originates a PCIe hierarchy and will have a - * // _CID of EISAID("PNP0A08"). As such, a CXL Host Bridge device may expose - * // both CXL _OSC and PCIe _OSC. - * // - * - * If (Arg0 == ToUUID (PCI_HOST_BRIDGE_OSC_UUID)) - * { - * // - * // Handle PCIe _OSC request - * // Mark UUID handled - * // - * } - */ - acpigen_write_if(); - acpigen_emit_byte(LEQUAL_OP); - acpigen_emit_byte(ARG0_OP); - acpigen_write_uuid(PCI_HOST_BRIDGE_OSC_UUID); - - acpigen_OSC_handle_pcie_request(domain); - acpigen_write_store_int_to_op(ASL_UUID_HANDLED, LOCAL6_OP); - - acpigen_write_if_end(); - - if (is_cxl_domain) { - /* - * If (Arg0 == ToUUID (CXL_HOST_BRIDGE_OSC_UUID)) - * { - * // - * // Handle CXL _OSC request - * // Mark UUID handled - * // - * } - */ - acpigen_write_if(); - acpigen_emit_byte(LEQUAL_OP); - acpigen_emit_byte(ARG0_OP); - acpigen_write_uuid(CXL_HOST_BRIDGE_OSC_UUID); - - acpigen_OSC_handle_cxl_request(domain); - acpigen_write_store_int_to_op(ASL_UUID_HANDLED, LOCAL6_OP); - - acpigen_write_if_end(); - } - - /* - * // - * // Handle unrecognized UUID - * // - * If (Local6 == ASL_UUID_UNHANDLED) - * { - * RETE = OSC_RET_UNRECOGNIZED_UUID - * } - */ - acpigen_write_if_lequal_op_int(LOCAL6_OP, ASL_UUID_UNHANDLED); - acpigen_write_store_int_to_namestr(OSC_RET_UNRECOGNIZED_UUID, "RETE"); - acpigen_write_if_end(); - - /* - * // - * // All done, return - * // - * Return (Arg3) - */ - acpigen_write_return_op(ARG3_OP); - - /* - * } // Method (_OSC, 4, NotSerialized) - */ - acpigen_pop_len(); - -} - -void acpigen_OSC_handle_pcie_request(const struct device *domain) -{ - uint32_t osc_features = soc_get_granted_pci_features(domain); - - /* - * If (Arg2 < 2)) - * { - * RETE = OSC_RET_FAILURE - * Return (Arg3) - * } - */ - acpigen_write_if(); - acpigen_emit_byte(LLESS_OP); - acpigen_emit_byte(ARG2_OP); - acpigen_write_integer(0x2); - - acpigen_write_store_int_to_namestr(OSC_RET_FAILURE, "RETE"); - acpigen_write_return_op(ARG3_OP); - - acpigen_write_if_end(); - - /* - * CreateDWordField (Arg3, 0x04, SUPP) - * CreateDWordField (Arg3, 0x08, CTRL) - * CreateDWordField (Local7, 0x08, OTRL) - */ - acpigen_write_create_dword_field(ARG3_OP, 0x04, "SUPP"); - acpigen_write_create_dword_field(ARG3_OP, 0x08, "CTRL"); - acpigen_write_create_dword_field(LOCAL7_OP, 0x08, "OTRL"); - - /* - * // Grant PCIe feature controls to OS - * CTRL &= osc_features - */ - acpigen_write_to_integer_from_namestring("CTRL", LOCAL0_OP); - acpigen_write_store_int_to_op(osc_features, LOCAL1_OP); - acpigen_write_and(LOCAL0_OP, LOCAL1_OP, LOCAL0_OP); - acpigen_write_store_op_to_namestr(LOCAL0_OP, "CTRL"); - - /* - * If (CTRL != OTRL) - * { - * RETE = OSC_RET_CAPABILITIES_MASKED - * } - */ - acpigen_write_if(); - acpigen_emit_byte(LNOT_OP); - acpigen_emit_byte(LEQUAL_OP); - acpigen_emit_namestring("CTRL"); - acpigen_emit_namestring("OTRL"); - acpigen_write_store_int_to_namestr(OSC_RET_CAPABILITIES_MASKED, "RETE"); - acpigen_write_if_end(); -}; - -void acpigen_OSC_handle_cxl_request(const struct device *domain) -{ - uint32_t osc_features = soc_get_granted_cxl_features(domain); - - /* - * If (Arg2 < 4)) - * { - * RETE = OSC_RET_FAILURE - * Return (Arg3) - * } - */ - acpigen_write_if(); - acpigen_emit_byte(LLESS_OP); - acpigen_emit_byte(ARG2_OP); - acpigen_write_integer(0x4); - - acpigen_write_store_int_to_namestr(OSC_RET_FAILURE, "RETE"); - acpigen_write_return_op(ARG3_OP); - - acpigen_write_if_end(); - - /* - * CreateDWordField (Arg3, 0x0C, SUPC) - * CreateDWordField (Arg3, 0x10, CTRC) - * CreateDWordField (Local7, 0x10, OTRC) - */ - acpigen_write_create_dword_field(ARG3_OP, 0x0C, "SUPC"); - acpigen_write_create_dword_field(ARG3_OP, 0x10, "CTRC"); - acpigen_write_create_dword_field(LOCAL7_OP, 0x10, "OTRC"); - - /* - * // Grant CXL feature controls to OS - * CTRC &= osc_features - */ - acpigen_write_to_integer_from_namestring("CTRC", LOCAL0_OP); - acpigen_write_store_int_to_op(osc_features, LOCAL1_OP); - acpigen_write_and(LOCAL0_OP, LOCAL1_OP, LOCAL0_OP); - acpigen_write_store_op_to_namestr(LOCAL0_OP, "CTRC"); - - /* - * If (CTRC != OTRC) - * { - * RETE = OSC_RET_CAPABILITIES_MASKED - * } - */ - acpigen_write_if(); - acpigen_emit_byte(LNOT_OP); - acpigen_emit_byte(LEQUAL_OP); - acpigen_emit_namestring("CTRC"); - acpigen_emit_namestring("OTRC"); - acpigen_write_store_int_to_namestr(OSC_RET_CAPABILITIES_MASKED, "RETE"); - acpigen_write_if_end(); -}; - -__weak uint32_t soc_get_granted_pci_features(const struct device *domain) -{ - /* - * By default grant no features to OS, which equals to the case where _OSC - * is absent. - * - * Refer to PCI firmware specification, revision 3.1. - * If the _OSC control method is absent from the scope of a host bridge device, then - * the operating system must not enable or attempt to use any features defined in this - * section for the hierarchy originated by the host bridge. Doing so could contend with - * platform firmware operations or produce undesired results. - */ - return 0; -} - -__weak uint32_t soc_get_granted_cxl_features(const struct device *domain) -{ - /* - * By default grant no features to OS, which equals to the case where _OSC - * is absent. - */ - return 0; -} diff --git a/src/include/acpi/acpigen_pci.h b/src/include/acpi/acpigen_pci.h index 7a07423..69216ec 100644 --- a/src/include/acpi/acpigen_pci.h +++ b/src/include/acpi/acpigen_pci.h @@ -7,13 +7,6 @@ #include <device/pci_def.h> #include <device/pci_type.h> -#define PCIE_NATIVE_HOTPLUG_CONTROL 0x01 -#define SHPC_NATIVE_HOTPLUG_CONTROL 0x02 -#define PCIE_PME_CONTROL 0x04 -#define PCIE_AER_CONTROL 0x08 -#define PCIE_CAP_STRUCTURE_CONTROL 0x10 -#define PCIE_LTR_CONTROL 0x20 - void acpigen_write_ADR_pci_devfn(pci_devfn_t devfn); void acpigen_write_ADR_pci_device(const struct device *dev); @@ -23,8 +16,4 @@ void pci_domain_fill_ssdt(const struct device *domain); -void acpigen_write_OSC_pci_domain(const struct device *domain, const bool is_cxl_domain); -uint32_t soc_get_granted_pci_features(const struct device *domain); -uint32_t soc_get_granted_cxl_features(const struct device *domain); - #endif /* ACPIGEN_PCI_H */ diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 9ee8d6a..2d8831a5 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <acpi/acpigen.h> +#include <acpi/acpigen_pci.h> #include <assert.h> #include <intelblocks/acpi.h> #include <soc/chip_common.h> @@ -157,3 +159,285 @@ return NULL; } + +#define PCI_HOST_BRIDGE_OSC_UUID "33db4d5b-1ff7-401c-9657-7441c03dd766" +#define CXL_HOST_BRIDGE_OSC_UUID "68f2d50b-c469-4d8a-bd3d-941a103fd3fc" + +#define OSC_RET_FAILURE 0x02 +#define OSC_RET_UNRECOGNIZED_UUID 0x04 +#define OSC_RET_UNRECOGNIZED_REV 0x08 +#define OSC_RET_CAPABILITIES_MASKED 0x10 + +#define OSC_QUERY_SUPPORT_SET 0x01 + +#define ASL_UUID_UNHANDLED 0x00 +#define ASL_UUID_HANDLED 0x01 + +static void acpigen_OSC_handle_pcie_request(const struct device *domain, + const uint32_t granted_pcie_features); +static void acpigen_OSC_handle_cxl_request(const struct device *domain, + const uint32_t granted_cxl_features); + +/* + * acpigen_write_OSC_pci_domain + * + * Reference: + * 6.2.11 in https://uefi.org/htmlspecs/ACPI_Spec_6_4_html/06_Device_Configuration/Devic… + * + * _OSC ASL Arguments: (4) + * Arg0 - A Buffer containing a UUID + * Arg1 - An Integer containing a Revision ID of the buffer format + * Arg2 - An Integer containing a count of entries in Arg3 + * Arg3 - A Buffer containing a list of DWORD capabilities + * + * _OSC ASL Return Value: + * A Buffer containing a list of capabilities + * + * Local Variables Assignment: + * Local0 - Temp assigned + * Local1 - Temp assigned + * Local2 - Not used + * Local3 - Not used + * Local4 - Not used + * Local5 - Not used + * Local6 - Record whether the UUID is handled + * Local7 - Backs up the input value of Arg3 + * + * Field Definitions: + * Name - Width Source Offset Description + * -------------------------------- + * QSUP - DWord Local7 0x00 Query support + * RETE - DWord Arg3 0x00 Returned errors + * SUPP - Dword Arg3 0x04 PCIe Features that OS supported + * CTRL - Dword Arg3 0x08 PCIe Features that firmware grant control to OS + * OTRL - Dword Local7 0x08 PCIe Features that OS requests for control + * SUPC - Dword Arg3 0x0C CXL Features that OS supported + * CTRC - Dword Arg3 0x10 CXL Features that firmware grant control to OS + * OTRC - Dword Local7 0x10 CXL Features that OS requests for control + */ +void acpigen_write_OSC_pci_domain(const struct device *domain, const uint32_t granted_pcie_features, + const bool is_cxl_domain, const uint32_t granted_cxl_features) +{ + /* + * Method (_OSC, 4, NotSerialized) + * { + */ + acpigen_write_method("_OSC", 4); + + /* + * // + * // Check revision ID + * // + * If (Arg1 != 1) + * { + * RETE = OSC_RET_UNRECOGNIZED_REV + * Return (Arg3) + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LNOT_OP); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(ARG1_OP); + acpigen_write_integer(0x1); + + acpigen_write_store_int_to_namestr(OSC_RET_UNRECOGNIZED_REV, "RETE"); + acpigen_write_return_op(ARG3_OP); + + acpigen_write_if_end(); + + /* + * // + * // Setup up local variables + * // + * Local7 = Arg3 + * CreateDwordField (Local7, 0x00, QSUP) + * CreateDWordField (Arg3, 0x00, RETE) + * RETE = 0x0 + * Local6 = ASL_UUID_UNHANDLED + */ + acpigen_write_store_ops(ARG3_OP, LOCAL7_OP); + acpigen_write_create_dword_field(LOCAL7_OP, 0x00, "QSUP"); + acpigen_write_create_dword_field(ARG3_OP, 0x00, "RETE"); + acpigen_write_store_int_to_namestr(0x0, "RETE"); + acpigen_write_store_int_to_op(ASL_UUID_UNHANDLED, LOCAL6_OP); + + /* + * // + * // Refer to CXL-3.1-Specification, 9.18.2 + * // A CXL Host Bridge also originates a PCIe hierarchy and will have a + * // _CID of EISAID("PNP0A08"). As such, a CXL Host Bridge device may expose + * // both CXL _OSC and PCIe _OSC. + * // + * + * If (Arg0 == ToUUID (PCI_HOST_BRIDGE_OSC_UUID)) + * { + * // + * // Handle PCIe _OSC request + * // Mark UUID handled + * // + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(ARG0_OP); + acpigen_write_uuid(PCI_HOST_BRIDGE_OSC_UUID); + + acpigen_OSC_handle_pcie_request(domain, granted_pcie_features); + acpigen_write_store_int_to_op(ASL_UUID_HANDLED, LOCAL6_OP); + + acpigen_write_if_end(); + + if (is_cxl_domain) { + /* + * If (Arg0 == ToUUID (CXL_HOST_BRIDGE_OSC_UUID)) + * { + * // + * // Handle CXL _OSC request + * // Mark UUID handled + * // + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(ARG0_OP); + acpigen_write_uuid(CXL_HOST_BRIDGE_OSC_UUID); + + acpigen_OSC_handle_cxl_request(domain, granted_cxl_features); + acpigen_write_store_int_to_op(ASL_UUID_HANDLED, LOCAL6_OP); + + acpigen_write_if_end(); + } + + /* + * // + * // Handle unrecognized UUID + * // + * If (Local6 == ASL_UUID_UNHANDLED) + * { + * RETE = OSC_RET_UNRECOGNIZED_UUID + * } + */ + acpigen_write_if_lequal_op_int(LOCAL6_OP, ASL_UUID_UNHANDLED); + acpigen_write_store_int_to_namestr(OSC_RET_UNRECOGNIZED_UUID, "RETE"); + acpigen_write_if_end(); + + /* + * // + * // All done, return + * // + * Return (Arg3) + */ + acpigen_write_return_op(ARG3_OP); + + /* + * } // Method (_OSC, 4, NotSerialized) + */ + acpigen_pop_len(); + +} + +void acpigen_OSC_handle_pcie_request(const struct device *domain, + const uint32_t granted_pcie_features) +{ + /* + * If (Arg2 < 2)) + * { + * RETE = OSC_RET_FAILURE + * Return (Arg3) + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LLESS_OP); + acpigen_emit_byte(ARG2_OP); + acpigen_write_integer(0x2); + + acpigen_write_store_int_to_namestr(OSC_RET_FAILURE, "RETE"); + acpigen_write_return_op(ARG3_OP); + + acpigen_write_if_end(); + + /* + * CreateDWordField (Arg3, 0x04, SUPP) + * CreateDWordField (Arg3, 0x08, CTRL) + * CreateDWordField (Local7, 0x08, OTRL) + */ + acpigen_write_create_dword_field(ARG3_OP, 0x04, "SUPP"); + acpigen_write_create_dword_field(ARG3_OP, 0x08, "CTRL"); + acpigen_write_create_dword_field(LOCAL7_OP, 0x08, "OTRL"); + + /* + * // Grant PCIe feature controls to OS + * CTRL &= osc_features + */ + acpigen_write_to_integer_from_namestring("CTRL", LOCAL0_OP); + acpigen_write_store_int_to_op(granted_pcie_features, LOCAL1_OP); + acpigen_write_and(LOCAL0_OP, LOCAL1_OP, LOCAL0_OP); + acpigen_write_store_op_to_namestr(LOCAL0_OP, "CTRL"); + + /* + * If (CTRL != OTRL) + * { + * RETE = OSC_RET_CAPABILITIES_MASKED + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LNOT_OP); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_namestring("CTRL"); + acpigen_emit_namestring("OTRL"); + acpigen_write_store_int_to_namestr(OSC_RET_CAPABILITIES_MASKED, "RETE"); + acpigen_write_if_end(); +}; + +void acpigen_OSC_handle_cxl_request(const struct device *domain, + uint32_t granted_cxl_features) +{ + /* + * If (Arg2 < 4)) + * { + * RETE = OSC_RET_FAILURE + * Return (Arg3) + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LLESS_OP); + acpigen_emit_byte(ARG2_OP); + acpigen_write_integer(0x4); + + acpigen_write_store_int_to_namestr(OSC_RET_FAILURE, "RETE"); + acpigen_write_return_op(ARG3_OP); + + acpigen_write_if_end(); + + /* + * CreateDWordField (Arg3, 0x0C, SUPC) + * CreateDWordField (Arg3, 0x10, CTRC) + * CreateDWordField (Local7, 0x10, OTRC) + */ + acpigen_write_create_dword_field(ARG3_OP, 0x0C, "SUPC"); + acpigen_write_create_dword_field(ARG3_OP, 0x10, "CTRC"); + acpigen_write_create_dword_field(LOCAL7_OP, 0x10, "OTRC"); + + /* + * // Grant CXL feature controls to OS + * CTRC &= osc_features + */ + acpigen_write_to_integer_from_namestring("CTRC", LOCAL0_OP); + acpigen_write_store_int_to_op(granted_cxl_features, LOCAL1_OP); + acpigen_write_and(LOCAL0_OP, LOCAL1_OP, LOCAL0_OP); + acpigen_write_store_op_to_namestr(LOCAL0_OP, "CTRC"); + + /* + * If (CTRC != OTRC) + * { + * RETE = OSC_RET_CAPABILITIES_MASKED + * } + */ + acpigen_write_if(); + acpigen_emit_byte(LNOT_OP); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_namestring("CTRC"); + acpigen_emit_namestring("OTRC"); + acpigen_write_store_int_to_namestr(OSC_RET_CAPABILITIES_MASKED, "RETE"); + acpigen_write_if_end(); +}; diff --git a/src/soc/intel/xeon_sp/include/soc/acpi.h b/src/soc/intel/xeon_sp/include/soc/acpi.h index e374544..1a2a72d 100644 --- a/src/soc/intel/xeon_sp/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/include/soc/acpi.h @@ -25,4 +25,14 @@ void iio_domain_set_acpi_name(struct device *dev, const char *prefix); +#define PCIE_NATIVE_HOTPLUG_CONTROL 0x01 +#define SHPC_NATIVE_HOTPLUG_CONTROL 0x02 +#define PCIE_PME_CONTROL 0x04 +#define PCIE_AER_CONTROL 0x08 +#define PCIE_CAP_STRUCTURE_CONTROL 0x10 +#define PCIE_LTR_CONTROL 0x20 + +void acpigen_write_OSC_pci_domain(const struct device *domain, const uint32_t granted_pcie_features, + const bool is_cxl_domain, const uint32_t granted_cxl_features); + #endif /* _SOC_ACPI_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81652?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia297e0a828f25b751032f18de04ec76f10131076 Gerrit-Change-Number: 81652 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Use default soc_get_ioapic_info
by Varshit Pandya (Code Review) 03 Apr '24

03 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81628?usp=email ) Change subject: soc/intel/xeon_sp: Use default soc_get_ioapic_info ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ecfba49cd9b4dfbb3f11d58d04d07ea1752a131 Gerrit-Change-Number: 81628 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 03 Apr 2024 02:00:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2024