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Change subject: soc/intel/xeon_sp: Use default soc_get_ioapic_info
......................................................................
Patch Set 2:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81628/comment/b30e72f8_fffe29a4 :
PS1, Line 14: TEST=intel/archercity CRB
> can you please add it to the commit message? […]
Sure, done!
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Hello Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins),
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Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes
......................................................................
soc/intel/xeon_sp: Add Granite Rapids initial codes
coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single
IO-APIC Xeon-SP platform. The same set of codes is also used
for SRF (Sierra Forest) SoC.
This patch initially sets the code set up.
1. All register definitions are forked from SPR (Sapphire Rapids)
and EBG (Emmisburg PCH)'s codes are reused.
2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip
common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later.
TEST=Build and boot on intel/archercity CRB
Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
Signed-off-by: Gang Chen <gang.c.chen(a)intel.com>
Signed-off-by: Jincheng Li <jincheng.li(a)intel.com>
---
M MAINTAINERS
M src/soc/intel/xeon_sp/Makefile.mk
M src/soc/intel/xeon_sp/chip_gen1.c
A src/soc/intel/xeon_sp/chip_gen6.c
A src/soc/intel/xeon_sp/gnr/Kconfig
A src/soc/intel/xeon_sp/gnr/Makefile.inc
A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl
A src/soc/intel/xeon_sp/gnr/chip.c
A src/soc/intel/xeon_sp/gnr/chip.h
A src/soc/intel/xeon_sp/gnr/cpu.c
A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h
A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h
A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h
A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h
A src/soc/intel/xeon_sp/gnr/ramstage.c
A src/soc/intel/xeon_sp/gnr/romstage.c
A src/soc/intel/xeon_sp/gnr/soc_acpi.c
A src/soc/intel/xeon_sp/gnr/soc_util.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/include/soc/fsp_upd.h
M src/soc/intel/xeon_sp/lockdown.c
M src/soc/intel/xeon_sp/uncore.c
23 files changed, 1,311 insertions(+), 62 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/36
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Change subject: soc/intel/xeon_sp: Share unlock_pam_regions()
......................................................................
soc/intel/xeon_sp: Share unlock_pam_regions()
unlock_pam_regions() is needed for SKX and CPX. Put the codes into
chip_gen1.c so that it could be shared among SoC generations.
After shared, unlock_pam_regions() is still called from SKX and
CPX SoC specific codes. SPR will also use chip_gen1.c, but it will
not call unlock_pam_regions().
TEST=Build and boot on intel/archercity CRB
Change-Id: Idbc7dc6dd22a1747a65543666fc714a0872e6b37
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/chip_gen1.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/skx/chip.c
4 files changed, 30 insertions(+), 47 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81619/5
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Change subject: soc/intel/xeon_sp: Use default soc_get_ioapic_info
......................................................................
soc/intel/xeon_sp: Use default soc_get_ioapic_info
intel/common/block/acpi provides default soc_get_ioapic_info for
single IOAPIC model. Use the default soc_get_ioapic_info when
XEON_SP_HAVE_IIO_IOAPIC is not set. This model fits for SPR and
later.
TEST=Build and boot on intel/archercity CRB
Change-Id: I1ecfba49cd9b4dfbb3f11d58d04d07ea1752a131
Signed-off-by: Shuo Liu <shuo.liu(a)intel.com>
---
M src/soc/intel/xeon_sp/acpi.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/81628/2
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The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: soc/intel/xeon_sp: Use default soc_get_ioapic_info
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81628/comment/60bd0ad4_5ccb0506 :
PS1, Line 14: TEST=intel/archercity CRB
> Suppose this open is solved, and let me tentatively close it. […]
can you please add it to the commit message?
"TEST: Build and boot archercity CRB"
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Change subject: lib: Refactor bmp_load_logo() implementation
......................................................................
Patch Set 3:
(2 comments)
File src/drivers/intel/fsp1_1/ramstage.c:
https://review.coreboot.org/c/coreboot/+/81618/comment/1baf3b8f_4fc0c6a9 :
PS3, Line 81: uint32_t
> > I don't think this would compile for 64-bit. Better make this a cast to `uintptr_t`. […]
Yes, that. The cast to `uint32_t` is optional but the other one is not.
File src/drivers/intel/fsp2_0/fsp_gop_blt.c:
https://review.coreboot.org/c/coreboot/+/81618/comment/194168cf_fae16cce :
PS3, Line 241: logo_size_t
> > `_t` is usually a suffix for types, not variable identifiers. […]
I think it would be cleaner to change the type for `logo_ptr_size` here already tbh.
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Change subject: mb/google/nissa/var/gothrax: Add touchscreen driver for ILI2901A-A210
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81610/comment/86d477f5_2ae7a95e :
PS2, Line 13: TEST=emerge-nissa coreboot
> How is the boot time affected?
In the experiment, the impact of this change on boot to kernel time was almost 0ms.
https://review.coreboot.org/c/coreboot/+/81610/comment/528e258f_fa86ea85 :
PS2, Line 13: TEST=emerge-nissa coreboot
> were you able to check whether the touchscreen was working correctly or was it just a build test ?
Done
File src/mainboard/google/brya/variants/gothrax/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/81610/comment/5773b12a_b71f6405 :
PS2, Line 244: "300"
> please check the power sequence in SPEC.
We refer to the parameters of the hid protocol
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Change subject: soc/intel/xeon_sp: Use default soc_get_ioapic_info
......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81628/comment/1aba56cd_3922df46 :
PS1, Line 14: TEST=intel/archercity CRB
> Yes, build and boot. […]
Suppose this open is solved, and let me tentatively close it. Please feel free to reopen it if still some needs to be clarified.
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Attention is currently required from: Eric Lai, Hung-Te Lin, Paul Menzel, Ruihai Zhou, Xuxin Xiong, Yang Wu.
Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81585?usp=email )
Change subject: mb/google/corsola: Add new board variant Wugtrio
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Patch Set 10: Code-Review+1
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