coreboot-gerrit April 2024

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[XS] Change in coreboot[main]: Add variant : Kyogre
by Yidi Lin (Code Review) 02 Apr '24

02 Apr '24

Attention is currently required from: Hung-Te Lin, Kei Hiroyoshi. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80135?usp=email ) Change subject: Add variant : Kyogre ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: CB:81218 is merged. Please abandon this patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/80135?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80c29c59fd233dfa5a2297632457176e9301b371 Gerrit-Change-Number: 80135 Gerrit-PatchSet: 1 Gerrit-Owner: Kei Hiroyoshi <hiroyoshi.kei(a)fujitsu.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Kei Hiroyoshi <hiroyoshi.kei(a)fujitsu.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Apr 2024 12:45:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: drivers/mipi: Fine tune clock for IVO_T109NW41
by Yidi Lin (Code Review) 02 Apr '24

02 Apr '24

Attention is currently required from: Ruihai Zhou. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81625?usp=email ) Change subject: drivers/mipi: Fine tune clock for IVO_T109NW41 ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81625/comment/293fe477_0557f9f1 : PS1, Line 12: panel-boe-tv101wum-nl6 > Not wrong, these two panels use the same driver. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/81625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I128b33fbcda9759330a363ebb6cf66415405c488 Gerrit-Change-Number: 81625 Gerrit-PatchSet: 1 Gerrit-Owner: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: cong yang <yangcong5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Apr 2024 12:43:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/corsola: Add new board variant Wugtrio
by Yidi Lin (Code Review) 02 Apr '24

02 Apr '24

Attention is currently required from: Eric Lai, Hung-Te Lin, Paul Menzel, Ruihai Zhou, Varshit Pandya, Xuxin Xiong, Yang Wu. Yidi Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81585?usp=email ) Change subject: mb/google/corsola: Add new board variant Wugtrio ...................................................................... Patch Set 10: Code-Review+1 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81585/comment/0459abab_5b160cfd : PS10, Line 9: And also enables SD card : support and MIPI panel support. > this seem like a separate logical change, can this patch be split into two patches? Please read https://review.coreboot.org/c/coreboot/+/81584/comments/fa93b717_9a99c165 And I don't think it is necessary to split another patch for SD card. -- To view, visit https://review.coreboot.org/c/coreboot/+/81585?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I586de68da4d0ee2dd5b7baea92ebb06db9fcfe8b Gerrit-Change-Number: 81585 Gerrit-PatchSet: 10 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ruihai Zhou <zhouruihai(a)huaqin.corp-partner.google.com> Gerrit-Attention: Xuxin Xiong <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Tue, 02 Apr 2024 12:40:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brox: Enable PMC pins to work with PD
by Felix Held (Code Review) 02 Apr '24

02 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81207?usp=email ) Change subject: mb/google/brox: Enable PMC pins to work with PD ...................................................................... mb/google/brox: Enable PMC pins to work with PD Enable SMLINK1 interface for PMC-PD communication to configure Type-C muxes. Refer RPL EDS vol 1: 765585. BUG=b:327622474 BRANCH=None TEST=Boot image on SKU2 and check PMC-PD working. Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81207 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Deepti Deshatty <deepti.deshatty(a)intel.com> --- M src/mainboard/google/brox/variants/baseboard/brox/gpio.c 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Deepti Deshatty: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c index 2ee4d08..9bdc197 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/gpio.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/gpio.c @@ -102,8 +102,8 @@ PAD_NC(GPP_B7, NONE), /* GPP_B8 : [NF1: ISH_I2C1_SCL NF2: I2C3_SCL NF6: USB_C_GPP_B8] ==> SOC_I2C3_SCL (NC) */ PAD_NC(GPP_B8, NONE), - /* GPP_B11 : [NF1: PMCALERT# NF6: USB_C_GPP_B11] ==> SOC_I2C_PD_INT_ODL (NC) */ - PAD_NC(GPP_B11, NONE), + /* GPP_B11 : [NF1: PMCALERT# NF6: USB_C_GPP_B11] ==> SOC_I2C_PD_INT_ODL */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* GPP_B12 : [NF1: SLP_S0# NF6: USB_C_GPP_B12] ==> SLP_S0_R_L */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* GPP_B13 : [NF1: PLTRST# NF6: USB_C_GPP_B13] ==> PLT_RST_L */ @@ -134,10 +134,10 @@ PAD_NC(GPP_C4, NONE), /* GPP_C5 : [NF1: SML0ALERT# NF6: USB_C_GPP_C5] ==> SOC_GPP_C5_BOOT_STRAP0 (NC) */ PAD_NC(GPP_C5, NONE), - /* GPP_C6 : SML1CLK ==> SOC_I2C_PD_SCL (NC) */ - PAD_NC(GPP_C6, NONE), - /* GPP_C7 : SML1DATA ==> SOC_I2C_PD_SDA (NC) */ - PAD_NC(GPP_C7, NONE), + /* GPP_C6 : SML1CLK ==> SOC_I2C_PD_SCL */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + /* GPP_C7 : SML1DATA ==> SOC_I2C_PD_SDA */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* GPP_D0 : [NF1: ISH_GP0 NF2: BK0 NF5: SBK0 NF6: USB_C_GPP_D0] ==> PCH_EC_PCH_INT_ODL */ PAD_CFG_GPI_APIC_LOW(GPP_D0, NONE, PLTRST), -- To view, visit https://review.coreboot.org/c/coreboot/+/81207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10 Gerrit-Change-Number: 81207 Gerrit-PatchSet: 5 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brya: Make get_soc_power_limit_config() a public function
by Felix Held (Code Review) 02 Apr '24

02 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81616?usp=email ) Change subject: mb/google/brya: Make get_soc_power_limit_config() a public function ...................................................................... mb/google/brya: Make get_soc_power_limit_config() a public function Make get_soc_power_limit_config() a public function to use on brya variants. Add prefix 'variant_' for it. BUG=None BRANCH=brya TEST=emerge-brya coreboot Change-Id: I31f938938e7c9da49c2aa7b52dd4b5f46f793495 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81616 Reviewed-by: Subrata Banik <subratabanik(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c M src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h 2 files changed, 6 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c index a7e5e8a..9ebe0d7 100644 --- a/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c +++ b/src/mainboard/google/brya/variants/baseboard/brya/ramstage.c @@ -11,7 +11,7 @@ WEAK_DEV_PTR(dptf_policy); -static struct soc_power_limits_config *get_soc_power_limit_config(void) +struct soc_power_limits_config *variant_get_soc_power_limit_config(void) { config_t *config = config_of_soc(); size_t i; @@ -44,7 +44,7 @@ if (!num_entries) return; - struct soc_power_limits_config *soc_config = get_soc_power_limit_config(); + struct soc_power_limits_config *soc_config = variant_get_soc_power_limit_config(); if (!soc_config) return; diff --git a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h index ad8eb05..583af59 100644 --- a/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brya/variants/baseboard/include/baseboard/variants.h @@ -4,6 +4,7 @@ #define __BASEBOARD_VARIANTS_H__ #include <chip.h> +#include <intelblocks/power_limit.h> #include <soc/gpio.h> #include <soc/meminit.h> #include <stdint.h> @@ -70,6 +71,9 @@ unsigned int bj_volts_mv; }; +/* Get soc power limit config struct for current CPU sku */ +struct soc_power_limits_config *variant_get_soc_power_limit_config(void); + /* Modify Power Limit devictree settings during ramstage */ void variant_update_power_limits(const struct cpu_power_limits *limits, size_t num_entries); -- To view, visit https://review.coreboot.org/c/coreboot/+/81616?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31f938938e7c9da49c2aa7b52dd4b5f46f793495 Gerrit-Change-Number: 81616 Gerrit-PatchSet: 3 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/nissa/var/sundance: Generate SPD ID for 4 supported memory ...
by Felix Held (Code Review) 02 Apr '24

02 Apr '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81612?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/nissa/var/sundance: Generate SPD ID for 4 supported memory parts ...................................................................... mb/google/nissa/var/sundance: Generate SPD ID for 4 supported memory parts Add sundance supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT 2. Hynix H58G56AK6BX069, H9JCNNNBK3MLYR-N6EE BUG=b:332201349 TEST=Use part_id_gen to generate related settings Change-Id: Ieece88b0b2b2ea5f0d6192ee8441e50d3f22a972 Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81612 Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/mainboard/google/brya/variants/sundance/memory/Makefile.mk M src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt 3 files changed, 20 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk b/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk index eace2e4..26dc4b0 100644 --- a/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk +++ b/src/mainboard/google/brya/variants/sundance/memory/Makefile.mk @@ -1,5 +1,10 @@ # SPDX-License-Identifier: GPL-2.0-or-later # This is an auto-generated file. Do not edit!! -# Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/sundance/memory/ src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt -SPD_SOURCES = placeholder +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 0(0b0000) Parts = H58G56AK6BX069 +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 1(0b0001) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 2(0b0010) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-7.hex # ID = 3(0b0011) Parts = K3KL8L80CM-MGCT diff --git a/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt index fa24790..fee3476 100644 --- a/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt @@ -1 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen ADL lp5 src/mainboard/google/brya/variants/sundance/memory/ src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt + DRAM Part Name ID to assign +H58G56AK6BX069 0 (0000) +H9JCNNNBK3MLYR-N6E 1 (0001) +K3KL6L60GM-MGCT 2 (0010) +K3KL8L80CM-MGCT 3 (0011) diff --git a/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt index 2499005..83001c1 100644 --- a/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt @@ -9,3 +9,7 @@ # See util/spd_tools/README.md for more details and instructions. # Part Name +H58G56AK6BX069 +H9JCNNNBK3MLYR-N6E +K3KL6L60GM-MGCT +K3KL8L80CM-MGCT -- To view, visit https://review.coreboot.org/c/coreboot/+/81612?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieece88b0b2b2ea5f0d6192ee8441e50d3f22a972 Gerrit-Change-Number: 81612 Gerrit-PatchSet: 3 Gerrit-Owner: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Melo Chuang <melo.chuang(a)lcfc.corp-partner.google.com> Gerrit-MessageType: merged

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 02 Apr '24

02 Apr '24

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Use default soc_get_ioapic_info
by Shuo Liu (Code Review) 02 Apr '24

02 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu, Varshit Pandya. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81628?usp=email ) Change subject: soc/intel/xeon_sp: Use default soc_get_ioapic_info ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81628/comment/c71cb175_2e1cafef : PS1, Line 14: TEST=intel/archercity CRB > you mean "Build and Boot archercity CRB"? […] Yes, build and boot. If only build is tested, i will add a sidenote mentioning it is build only. -- To view, visit https://review.coreboot.org/c/coreboot/+/81628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1ecfba49cd9b4dfbb3f11d58d04d07ea1752a131 Gerrit-Change-Number: 81628 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 02 Apr 2024 12:29:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 02 Apr '24

02 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Singer, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81316?usp=email ) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... Patch Set 33: (15 comments) File src/soc/intel/xeon_sp/Makefile.mk: https://review.coreboot.org/c/coreboot/+/81316/comment/161745fd_9cc4304c : PS33, Line 8: ebg : > This is confusing. […] This is due to SPR fork/reuse. Will extend the comment block to clarify. File src/soc/intel/xeon_sp/chip_gen6.c: https://review.coreboot.org/c/coreboot/+/81316/comment/a83e38ac_e2abb3cc : PS33, Line 44: IOINDEX > Just use index directly? this one should be deprecated as links are not in struct bus anymore. Done File src/soc/intel/xeon_sp/gnr/Makefile.inc: https://review.coreboot.org/c/coreboot/+/81316/comment/c5d0eeda_d97f6220 : PS33, Line 12: romstage-y += romstage.c soc_util.c : romstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c : : ramstage-y += chip.c cpu.c soc_util.c ramstage.c soc_acpi.c : ramstage-y += ../chip_gen6.c : : CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/gnr/include -I$(src)/soc/intel/xeon_sp/gnr : > Use one value per line Done File src/soc/intel/xeon_sp/gnr/acpi/gpe.asl: https://review.coreboot.org/c/coreboot/+/81316/comment/f49a38dd_f87deebf : PS33, Line 27: Method (_L62, 0, NotSerialized) : { : DBGO("\\_GPE\\_L62\n") : SGPC = 0 // clear SWGPE control : SGPS = 1 // clear SWGPE Status : } > What do you need this for? This is to enable the SWGPE to work, SWGPE is a special sort of GPE, but it can be triggered by software, The trigger bits is defined in, https://github.com/coreboot/coreboot/blob/main/src/soc/intel/xeon_sp/includ… A similar usage is at, e.g. https://github.com/tianocore/edk2-platforms/blob/master/Platform/Intel/Kaby… File src/soc/intel/xeon_sp/gnr/acpi/platform.asl: https://review.coreboot.org/c/coreboot/+/81316/comment/9315add1_18e5f8b1 : PS33, Line 6: Name (_S0, Package () // mandatory system state : { : 0x00, 0x00, 0x00, 0x00 : }) : : Name (_S5, Package () // mandatory system state : { : 0x07, 0x00, 0x00, 0x00 : }) > can you sleepstates. […] It is possible, but I need to modify the src/southbridge/intel/common/acpi/sleepstates.asl to set SSFG as 0x0 for CONFIG_XEON_SP_COMMON_BASE (to support S0/S5 only). I will have another patch for it. File src/soc/intel/xeon_sp/gnr/chip.h: https://review.coreboot.org/c/coreboot/+/81316/comment/b98aa853_3a7e0cd9 : PS33, Line 16: u > Use bool where possible. Done https://review.coreboot.org/c/coreboot/+/81316/comment/7ef730b1_841b9be7 : PS33, Line 17: uint8_t x2apic; > unused? Done File src/soc/intel/xeon_sp/gnr/cpu.c: https://review.coreboot.org/c/coreboot/+/81316/comment/f0a70a97_97225a4e : PS33, Line 63: {0, 0}, > CPU_TABLE_END Done File src/soc/intel/xeon_sp/gnr/include/soc/cpu.h: https://review.coreboot.org/c/coreboot/+/81316/comment/2d6cb476_f0c55e1c : PS33, Line 6: #include <device/device.h> : #include <cpu/x86/msr.h> > This should not be in this header. Done File src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h: https://review.coreboot.org/c/coreboot/+/81316/comment/9e411fd3_6e420ac1 : PS33, Line 179: DMIRCBAR > I'm curious. […] In the initial codes, all register definitions are forked from SPR (Sapphire Rapids) and EBG (Emmisburg PCH)'s codes are reused. (added mentioning in the commit message). Will extend the comment block to clarify. https://review.coreboot.org/c/coreboot/+/81316/comment/e19a918b_f720f484 : PS33, Line 184: // IIO DFX Global D7F7 registers : #define IIO_DFX_TSWCTL0 0x30c : #define IIO_DFX_LCK_CTL 0x504 : : // XHCI register : #define SYS_BUS_CFG2 0x44 : : /* > Please be consistent with comment style. Done File src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h: https://review.coreboot.org/c/coreboot/+/81316/comment/0be4a5df_ee9c6416 : PS33, Line 3: // TEMPORARY PLACE HOLDER! DO NOT USE! > Eh? In the initial codes, all register definitions are forked from SPR (Sapphire Rapids) and EBG (Emmisburg PCH)'s codes are reused. (added mentioning in the commit message). Will extend the comment block to clarify. File src/soc/intel/xeon_sp/gnr/soc_util.c: https://review.coreboot.org/c/coreboot/+/81316/comment/85a980ac_9f60e839 : PS33, Line 143: bool is_memtype_reserved(uint16_t mem_type) : { : return FALSE; : } : : bool is_memtype_non_volatile(uint16_t mem_type) : { : return FALSE; : } : : bool is_memtype_processor_attached(uint16_t mem_type) : { : return TRUE; : } : > Please use true/false, the definitions from coreboot. Done File src/soc/intel/xeon_sp/uncore.c: PS33: > The code movements should be separated out into their own commit. There were a discussion to merge the movement into this one, so I keep them together. The history is at: https://review.coreboot.org/c/coreboot/+/81110. https://review.coreboot.org/c/coreboot/+/81316/comment/4f643c8e_46a58161 : PS33, Line 35: enum { : TOHM_REG, : MMIOL_REG, : MMCFG_BASE_REG, : MMCFG_LIMIT_REG, : TOLM_REG, : /* NCMEM and ME ranges are mutually exclusive */ : NCMEM_BASE_REG, : NCMEM_LIMIT_REG, : ME_BASE_REG, : ME_LIMIT_REG, : TSEG_BASE_REG, : TSEG_LIMIT_REG, : VTDBAR_REG, : /* Must be last. */ : NUM_MAP_ENTRIES : }; > Does it make sense to move this to a header? It's used as index for the array below. Sure, it should be already at src/soc/intel/xeon_sp/include/soc/chip_common.h. -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 33 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 02 Apr 2024 12:27:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 02 Apr '24

02 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Shuo Liu, TangYiwei, Tim Chu. Hello Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81316?usp=email to look at the new patch set (#34). The following approvals got outdated and were removed: Code-Review+1 by Arthur Heymans, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... soc/intel/xeon_sp: Add Granite Rapids initial codes coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single IO-APIC Xeon-SP platform. The same set of codes is also used for SRF (Sierra Forest) SoC. This patch initially sets the code set up. 1. All register definitions are forked from SPR (Sapphire Rapids) and EBG (Emmisburg PCH)'s codes are reused. 2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later. TEST=intel/archercity CRB Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M MAINTAINERS M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/chip_gen1.c A src/soc/intel/xeon_sp/chip_gen6.c A src/soc/intel/xeon_sp/gnr/Kconfig A src/soc/intel/xeon_sp/gnr/Makefile.inc A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl A src/soc/intel/xeon_sp/gnr/acpi/platform.asl A src/soc/intel/xeon_sp/gnr/chip.c A src/soc/intel/xeon_sp/gnr/chip.h A src/soc/intel/xeon_sp/gnr/cpu.c A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h A src/soc/intel/xeon_sp/gnr/ramstage.c A src/soc/intel/xeon_sp/gnr/romstage.c A src/soc/intel/xeon_sp/gnr/soc_acpi.c A src/soc/intel/xeon_sp/gnr/soc_util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/fsp_upd.h M src/soc/intel/xeon_sp/lockdown.c M src/soc/intel/xeon_sp/uncore.c 24 files changed, 1,325 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/34 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 34 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit April 2024