coreboot-gerrit April 2024

coreboot-gerrit@coreboot.org

1 participants
3293 discussions

[XS] Change in coreboot[main]: lynxpoint/broadwell: Correct L1 exit latency with ASPM
by Lean Sheng Tan (Code Review) 14 Apr '24

14 Apr '24

Attention is currently required from: Angel Pons. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57501?usp=email ) Change subject: lynxpoint/broadwell: Correct L1 exit latency with ASPM ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57501?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2166bd5b5504ed97adcd2db0a802da02da4c91f3 Gerrit-Change-Number: 57501 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 14 Apr 2024 20:55:01 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: lynxpoint/broadwell: Correct PCH-LP PCIe ASPM check
by Lean Sheng Tan (Code Review) 14 Apr '24

14 Apr '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57500?usp=email ) Change subject: lynxpoint/broadwell: Correct PCH-LP PCIe ASPM check ...................................................................... lynxpoint/broadwell: Correct PCH-LP PCIe ASPM check Lynx Point PCH reference code version 1.9.1 checks bit 29 to detect ASPM on PCH-LP root port #6, not bit 28. Document 535127 (BDW PCH-LP BS) also uses bit 29 for root port #6. Correct the bit used in the check, as well as the surrounding comments. Change-Id: Ie4bd7cbbfc151762f29eab1326567f987b25ab19 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57500 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/broadwell/pch/pcie.c M src/southbridge/intel/lynxpoint/pcie.c 2 files changed, 10 insertions(+), 10 deletions(-) Approvals: Lean Sheng Tan: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/broadwell/pch/pcie.c b/src/soc/intel/broadwell/pch/pcie.c index ef03eee..966a25d 100644 --- a/src/soc/intel/broadwell/pch/pcie.c +++ b/src/soc/intel/broadwell/pch/pcie.c @@ -452,17 +452,17 @@ break; case 5: /* - * Bit 28 of b0d28f4 0x32c register correspond to - * Root Ports 4:1. + * Bit 28 of b0d28f4 0x32c register corresponds to + * Root Port 5. */ do_aspm = !!(rpc.b0d28f4_32c & (1 << 28)); break; case 6: /* - * Bit 28 of b0d28f5 0x32c register correspond to - * Root Ports 4:1. + * Bit 29 of b0d28f5 0x32c register corresponds to + * Root Port 6. */ - do_aspm = !!(rpc.b0d28f5_32c & (1 << 28)); + do_aspm = !!(rpc.b0d28f5_32c & (1 << 29)); break; } diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 7f5e1fa..0c17c9c 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -518,17 +518,17 @@ break; case 5: /* - * Bit 28 of b0d28f4 0x32c register correspond to - * Root Ports 4:1. + * Bit 28 of b0d28f4 0x32c register corresponds to + * Root Port 5. */ do_aspm = !!(rpc.b0d28f4_32c & (1 << 28)); break; case 6: /* - * Bit 28 of b0d28f5 0x32c register correspond to - * Root Ports 4:1. + * Bit 29 of b0d28f5 0x32c register corresponds to + * Root Port 6. */ - do_aspm = !!(rpc.b0d28f5_32c & (1 << 28)); + do_aspm = !!(rpc.b0d28f5_32c & (1 << 29)); break; } } else { -- To view, visit https://review.coreboot.org/c/coreboot/+/57500?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie4bd7cbbfc151762f29eab1326567f987b25ab19 Gerrit-Change-Number: 57500 Gerrit-PatchSet: 8 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp/spr: Use official microcodes
by Lean Sheng Tan (Code Review) 14 Apr '24

14 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81637?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/xeon_sp/spr: Use official microcodes ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > The configs/builder/config.intel.crb.ac still uses local ucode binary. […] maybe this patch should also update the configs/builder/config.intel.crb.ac as well? -- To view, visit https://review.coreboot.org/c/coreboot/+/81637?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I58121cc2ca7699d3d26581d7d5875ec74deeeb93 Gerrit-Change-Number: 81637 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sun, 14 Apr 2024 20:53:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp/spr: Drop microcode constraints
by Lean Sheng Tan (Code Review) 14 Apr '24

14 Apr '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81635?usp=email ) Change subject: soc/intel/xeon_sp/spr: Drop microcode constraints ...................................................................... soc/intel/xeon_sp/spr: Drop microcode constraints For current generation SPR/EMR you need to add at least 3 different microcodes having about 2MiB of size in total. This doesn't work with the hardcoded offset and size in Kconfig. Since it's loaded through FIT there's no need to pass it to FSP-T. Drop the hardcoded locations and place it somewhere in CBFS. Test: Booted on ibm/sbp1 with microcode confirmed loaded in bootblock on BSP. All the APs also have the correct microcode version loaded. TEST= Build and boot on intel/archercity CRB 'cat /proc/cpuinfo | grep microcode' result doesn't change before and after this patch. Change-Id: Iaa7007c2b11a860c9c664a7e753440bad7fe858e Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81635 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Jincheng Li <jincheng.li(a)intel.com> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/spr/Kconfig 1 file changed, 0 insertions(+), 7 deletions(-) Approvals: Jincheng Li: Looks good to me, but someone else must approve Shuo Liu: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve Arthur Heymans: Looks good to me, approved Angel Pons: Looks good to me, but someone else must approve build bot (Jenkins): Verified Sumeet R Pawnikar: Looks good to me, approved Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index b40a534..7887bd0 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -75,13 +75,6 @@ allocated at 0xfe800000 (the CAR base) and consumes about 0x150000 bytes of memory. -config CPU_MICROCODE_CBFS_LOC - hex - default 0xffe0fdc0 - -config CPU_MICROCODE_CBFS_LEN - hex - default 0x8c00 config STACK_SIZE hex -- To view, visit https://review.coreboot.org/c/coreboot/+/81635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa7007c2b11a860c9c664a7e753440bad7fe858e Gerrit-Change-Number: 81635 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp/spr: Drop microcode constraints
by Lean Sheng Tan (Code Review) 14 Apr '24

14 Apr '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Ray Ni, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81635?usp=email ) Change subject: soc/intel/xeon_sp/spr: Drop microcode constraints ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81635?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa7007c2b11a860c9c664a7e753440bad7fe858e Gerrit-Change-Number: 81635 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sun, 14 Apr 2024 20:50:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp: Compress FSP-S
by Lean Sheng Tan (Code Review) 14 Apr '24

14 Apr '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81634?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Compress FSP-S ...................................................................... soc/intel/xeon_sp: Compress FSP-S Compress FSP-S to save some space in CBFS. Reduces the size of debug FSP-S by about 25%. Test: Still boots on ibm/sbp1. TEST= Build and boot on intel/archercity CRB. Change-Id: I6248e7cabbce45f6c2fedfab34f328309f87e868 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81634 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/intel/xeon_sp/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved Arthur Heymans: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 51f407e..45c7d9d 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -15,6 +15,7 @@ select CPU_INTEL_FIRMWARE_INTERFACE_TABLE select FSP_CAR select FSP_M_XIP + select FSP_COMPRESS_FSP_S_LZ4 select FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS select FSP_T_XIP select HAVE_SMI_HANDLER -- To view, visit https://review.coreboot.org/c/coreboot/+/81634?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6248e7cabbce45f6c2fedfab34f328309f87e868 Gerrit-Change-Number: 81634 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp: Compress FSP-S
by Lean Sheng Tan (Code Review) 14 Apr '24

14 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Paul Menzel, Ray Ni, Shuo Liu, Sumeet R Pawnikar, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81634?usp=email ) Change subject: soc/intel/xeon_sp: Compress FSP-S ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81634/comment/b1b6742e_d19dd1d2 : PS1, Line 12: Test: Still boots on ibm/sbp1. > any further concern? if no i will mark as close and get it merged. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81634?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6248e7cabbce45f6c2fedfab34f328309f87e868 Gerrit-Change-Number: 81634 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Sun, 14 Apr 2024 20:48:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: sb/intel/ibexpeak: Sever bd82x6x source dependency
by Angel Pons (Code Review) 14 Apr '24

14 Apr '24

Attention is currently required from: Keith Hui. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81889?usp=email ) Change subject: sb/intel/ibexpeak: Sever bd82x6x source dependency ...................................................................... Patch Set 1: (1 comment) File src/southbridge/intel/ibexpeak/chip.h: https://review.coreboot.org/c/coreboot/+/81889/comment/d87dae12_cad2d284 : PS1, Line 71: /* These USB3 fields, copied from bd82x6x, don't apply here, : * as Ibex Peak doesn't have USB3. */ : uint32_t xhci_switchable_ports; : uint32_t superspeed_capable_ports; : uint32_t xhci_overcurrent_mapping; Do you mind dropping these in a follow-up? Thanks in advance -- To view, visit https://review.coreboot.org/c/coreboot/+/81889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I08229ca658bd9c360b6be6137d882d319041b730 Gerrit-Change-Number: 81889 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sun, 14 Apr 2024 19:29:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[M] Change in coreboot[main]: sb/intel/ibexpeak: Sever bd82x6x source dependency
by Angel Pons (Code Review) 14 Apr '24

14 Apr '24

Attention is currently required from: Keith Hui. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81889?usp=email ) Change subject: sb/intel/ibexpeak: Sever bd82x6x source dependency ...................................................................... Patch Set 1: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81889/comment/94dd15db_54699a18 : PS1, Line 13: TEST=Timeless binary did not change. For which board? Please specify -- To view, visit https://review.coreboot.org/c/coreboot/+/81889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I08229ca658bd9c360b6be6137d882d319041b730 Gerrit-Change-Number: 81889 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sun, 14 Apr 2024 19:28:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: mb/packardbell/ms2290: Correct header included
by Angel Pons (Code Review) 14 Apr '24

14 Apr '24

Attention is currently required from: Keith Hui. Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81888?usp=email ) Change subject: mb/packardbell/ms2290: Correct header included ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iafa83b7f3c1cd2d8ab9af51aa331ca673d9a66df Gerrit-Change-Number: 81888 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Comment-Date: Sun, 14 Apr 2024 19:28:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit April 2024