coreboot-gerrit April 2024

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[S] Change in coreboot[main]: soc/intel/xeon_sp/gnr: Use OCP_VPD drivers
by Shuo Liu (Code Review) 15 Apr '24

15 Apr '24

Attention is currently required from: Arthur Heymans, Christian Walter, David Hendricks, Jincheng Li, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, TangYiwei, Tim Chu. Hello Arthur Heymans, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81317?usp=email to look at the new patch set (#34). The following approvals got outdated and were removed: Code-Review+2 by Arthur Heymans, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/intel/xeon_sp/gnr: Use OCP_VPD drivers ...................................................................... soc/intel/xeon_sp/gnr: Use OCP_VPD drivers Use OCP_VPD driver provided functions to get VPD value. TEST=Build and boot on intel/archercity CRB Change-Id: Ifeca8cf4312ab66ca03188fe25af88a952073130 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/gnr/Kconfig M src/soc/intel/xeon_sp/gnr/chip.h M src/soc/intel/xeon_sp/gnr/romstage.c 3 files changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/81317/34 -- To view, visit https://review.coreboot.org/c/coreboot/+/81317?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifeca8cf4312ab66ca03188fe25af88a952073130 Gerrit-Change-Number: 81317 Gerrit-PatchSet: 34 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: TangYiwei Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XL] Change in coreboot[main]: soc/intel/xeon_sp: Add Granite Rapids initial codes
by Shuo Liu (Code Review) 15 Apr '24

15 Apr '24

Attention is currently required from: Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Felix Held, Jincheng Li, Johnny Lin, Jonathan Zhang, Nico Huber, Patrick Rudolph, Paul Menzel, TangYiwei, Tim Chu. Hello Arthur Heymans, Chen, Gang C, Christian Walter, David Hendricks, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, TangYiwei, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81316?usp=email to look at the new patch set (#45). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Add Granite Rapids initial codes ...................................................................... soc/intel/xeon_sp: Add Granite Rapids initial codes coreboot GNR (Granite Rapids) is a FSP 2.4 based, no-PCH, single IO-APIC Xeon-SP platform. The same set of codes is also used for SRF (Sierra Forest) SoC. This patch initially sets the code set up. 1. All register definitions are forked from previous generation. SPR (Sapphire Rapids) and EBG (Emmisburg PCH)'s codes are reused. 2. src/soc/intel/xeon_sp/chip_gen6.c is newly added as chip common codes for 6th Gen Xeon-SP SoC (Granite Rapids) and later. TEST=Build and boot on intel/archercity CRB Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Signed-off-by: Gang Chen <gang.c.chen(a)intel.com> Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M MAINTAINERS M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/chip_gen1.c A src/soc/intel/xeon_sp/chip_gen6.c A src/soc/intel/xeon_sp/gnr/Kconfig A src/soc/intel/xeon_sp/gnr/Makefile.inc A src/soc/intel/xeon_sp/gnr/acpi/gpe.asl A src/soc/intel/xeon_sp/gnr/chip.c A src/soc/intel/xeon_sp/gnr/chip.h A src/soc/intel/xeon_sp/gnr/chipset.cb A src/soc/intel/xeon_sp/gnr/cpu.c A src/soc/intel/xeon_sp/gnr/include/soc/cpu.h A src/soc/intel/xeon_sp/gnr/include/soc/pci_devs.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_msr.h A src/soc/intel/xeon_sp/gnr/include/soc/soc_util.h A src/soc/intel/xeon_sp/gnr/include/soc/vpd.h A src/soc/intel/xeon_sp/gnr/ramstage.c A src/soc/intel/xeon_sp/gnr/romstage.c A src/soc/intel/xeon_sp/gnr/soc_acpi.c A src/soc/intel/xeon_sp/gnr/soc_util.c M src/soc/intel/xeon_sp/include/soc/chip_common.h M src/soc/intel/xeon_sp/include/soc/fsp_upd.h M src/soc/intel/xeon_sp/lockdown.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/uncore.c 25 files changed, 1,274 insertions(+), 81 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81316/45 -- To view, visit https://review.coreboot.org/c/coreboot/+/81316?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3084e1b5abf25d8d9504bebeaed2a15b916ed56b Gerrit-Change-Number: 81316 Gerrit-PatchSet: 45 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: TangYiwei Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: TangYiwei Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: nb/intel/haswell: Fix building BDW MRC.bin path with clang
by Felix Singer (Code Review) 15 Apr '24

15 Apr '24

Attention is currently required from: Angel Pons, Arthur Heymans, Maximilian Brune, Nico Huber. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81862?usp=email ) Change subject: nb/intel/haswell: Fix building BDW MRC.bin path with clang ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81862?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7b5e22e893e9f3f17a15197c65448fb782590f6 Gerrit-Change-Number: 81862 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 14 Apr 2024 23:53:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: acpi/acpi: mark CTBL coreboot table device as hidden
by CoolStar (Code Review) 14 Apr '24

14 Apr '24

Attention is currently required from: Cliff Huang, Felix Held, Lance Zhao, Matt DeVillier, Matt DeVillier, Paul Menzel, Tim Wawrzynczak. CoolStar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81264?usp=email ) Change subject: acpi/acpi: mark CTBL coreboot table device as hidden ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > this has nothing to do with AMD (or Intel), it's an ACPI device for the coreboot/cbmem table. @paul my driver is open source https://github.com/coolstar/cbtable Just a matter of someone with Microsoft hardware portal access to submit it to Windows Update -- To view, visit https://review.coreboot.org/c/coreboot/+/81264?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifaefeb662da33323460333d9ca9c0e8340720fd1 Gerrit-Change-Number: 81264 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: CoolStar <coolstarorganization(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Sun, 14 Apr 2024 21:21:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: CoolStar <coolstarorganization(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: sb/intel/ibexpeak: Sever bd82x6x source dependency
by Keith Hui (Code Review) 14 Apr '24

14 Apr '24

Hello Angel Pons, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81889?usp=email to look at the new patch set (#2). Change subject: sb/intel/ibexpeak: Sever bd82x6x source dependency ...................................................................... sb/intel/ibexpeak: Sever bd82x6x source dependency It shares southbridge devicetree definition with bd82x6x, causing changes made there to break builds for boards with this PCH. Give ibexpeak its own copy. TEST=abuild tested with lenovo/t410, lenovo/x201, packardbell/ms2290. Timeless binary did not change for all. Change-Id: I08229ca658bd9c360b6be6137d882d319041b730 Signed-off-by: Keith Hui <buurin(a)gmail.com> --- M src/southbridge/intel/ibexpeak/chip.h M src/southbridge/intel/ibexpeak/pch.h 2 files changed, 77 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/81889/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I08229ca658bd9c360b6be6137d882d319041b730 Gerrit-Change-Number: 81889 Gerrit-PatchSet: 2 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: sb/intel/ibexpeak: Sever bd82x6x source dependency
by Keith Hui (Code Review) 14 Apr '24

14 Apr '24

Keith Hui has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81889?usp=email ) Change subject: sb/intel/ibexpeak: Sever bd82x6x source dependency ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81889/comment/2cdfcffd_aaf9da2b : PS1, Line 13: TEST=Timeless binary did not change. > For which board? Please specify This was done via abuild so all 3 boards with ibexpeak are covered: lenovo/t410, lenovo/x201 (two abuild configs), packardbell/ms2290. File src/southbridge/intel/ibexpeak/chip.h: https://review.coreboot.org/c/coreboot/+/81889/comment/747b5e0a_9ac8bd56 : PS1, Line 71: /* These USB3 fields, copied from bd82x6x, don't apply here, : * as Ibex Peak doesn't have USB3. */ : uint32_t xhci_switchable_ports; : uint32_t superspeed_capable_ports; : uint32_t xhci_overcurrent_mapping; > Do you mind dropping these in a follow-up? Thanks in advance Will do. I left them behind for now so I can prove I didn't upset the compiled binary during the copy. -- To view, visit https://review.coreboot.org/c/coreboot/+/81889?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I08229ca658bd9c360b6be6137d882d319041b730 Gerrit-Change-Number: 81889 Gerrit-PatchSet: 1 Gerrit-Owner: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 14 Apr 2024 21:15:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/broadwell: Add ACPI CIDs for SerialIO devices
by Angel Pons (Code Review) 14 Apr '24

14 Apr '24

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46973 ) Change subject: soc/intel/broadwell: Add ACPI CIDs for SerialIO devices ...................................................................... soc/intel/broadwell: Add ACPI CIDs for SerialIO devices Lynxpoint has them, so add them on Broadwell as well. Change-Id: Iaa3e8044090262a64e58062ec4b116976978ce55 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pch/acpi/serialio.asl 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/46973/1 diff --git a/src/soc/intel/broadwell/pch/acpi/serialio.asl b/src/soc/intel/broadwell/pch/acpi/serialio.asl index 2bacd2b..1e6dbac 100644 --- a/src/soc/intel/broadwell/pch/acpi/serialio.asl +++ b/src/soc/intel/broadwell/pch/acpi/serialio.asl @@ -166,6 +166,7 @@ // LynxPoint-LP Return ("INT33C2") } + Name (_CID, "INT33C2") Name (_UID, 1) Name (SSCN, Package () { 432, 507, 30 }) @@ -242,6 +243,7 @@ // LynxPoint-LP Return ("INT33C3") } + Name (_CID, "INT33C3") Name (_UID, 1) Name (SSCN, Package () { 432, 507, 30 }) @@ -318,6 +320,7 @@ // LynxPoint-LP Return ("INT33C0") } + Name (_CID, "INT33C0") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -379,6 +382,7 @@ // LynxPoint-LP Return ("INT33C1") } + Name (_CID, "INT33C1") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -452,6 +456,7 @@ // LynxPoint-LP Return ("INT33C4") } + Name (_CID, "INT33C4") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS @@ -525,6 +530,7 @@ // LynxPoint-LP Return ("INT33C5") } + Name (_CID, "INT33C5") Name (_UID, 1) // BAR0 is assigned during PCI enumeration and saved into NVS -- To view, visit https://review.coreboot.org/c/coreboot/+/46973 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa3e8044090262a64e58062ec4b116976978ce55 Gerrit-Change-Number: 46973 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: sb/intel/lynxpoint: Enable PCIe Relaxed Order
by Lean Sheng Tan (Code Review) 14 Apr '24

14 Apr '24

Attention is currently required from: Angel Pons, Maximilian Brune. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57504?usp=email ) Change subject: sb/intel/lynxpoint: Enable PCIe Relaxed Order ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/57504?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If7ba4e826adfc8c220ecc68c4a456fbe3cb99667 Gerrit-Change-Number: 57504 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Sun, 14 Apr 2024 20:57:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: sb/intel/lynxpoint: Fix AER and L1 sub-state reporting
by Lean Sheng Tan (Code Review) 14 Apr '24

14 Apr '24

Attention is currently required from: Angel Pons, Maximilian Brune. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57503?usp=email ) Change subject: sb/intel/lynxpoint: Fix AER and L1 sub-state reporting ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57503?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I08bd107eec7a3b2f1701c4657ae104e0818ae035 Gerrit-Change-Number: 57503 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Sun, 14 Apr 2024 20:57:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: sb/intel/lynxpoint/pcie.c: Fix 0xf5 register mask
by Lean Sheng Tan (Code Review) 14 Apr '24

14 Apr '24

Attention is currently required from: Angel Pons. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/57502?usp=email ) Change subject: sb/intel/lynxpoint/pcie.c: Fix 0xf5 register mask ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/57502?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9529ad88d34a5cb4a09843e3165f3a70c5ea22e8 Gerrit-Change-Number: 57502 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <rudolphpatrick05(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Sun, 14 Apr 2024 20:55:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit April 2024