coreboot-gerrit March 2024

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[S] Change in coreboot[main]: util/xcompile: Add target architecture to CPPFLAGS
by Martin L Roth (Code Review) 26 Mar '24

26 Mar '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/75031?usp=email ) Change subject: util/xcompile: Add target architecture to CPPFLAGS ...................................................................... util/xcompile: Add target architecture to CPPFLAGS In order to preprocess linker scripts the target architecture needs to be specified. With clang this needs to be set via a cli argument. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I4340681e30059d6f18a49a49937668cd3dd39ce1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75031 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- M src/arch/arm/armv7/Makefile.mk M src/arch/arm64/armv8/Makefile.mk M util/xcompile/xcompile 3 files changed, 7 insertions(+), 23 deletions(-) Approvals: build bot (Jenkins): Verified Julius Werner: Looks good to me, approved diff --git a/src/arch/arm/armv7/Makefile.mk b/src/arch/arm/armv7/Makefile.mk index 53261ee..56309d7b 100644 --- a/src/arch/arm/armv7/Makefile.mk +++ b/src/arch/arm/armv7/Makefile.mk @@ -10,11 +10,6 @@ armv7_asm_flags += -Wa,-mno-warn-deprecated else # CLANG armv7_flags += -mfpu=none -bootblock-ld-ccopts += -target arm-eabi -verstage-ld-ccopts += -target arm-eabi -romstage-ld-ccopts += -target arm-eabi -ramstage-ld-ccopts += -target arm-eabi -rmodule_arm-ld-ccopts += -target arm-eabi endif armv7-r_asm_flags = $(armv7-r_flags) $(armv7_asm_flags) diff --git a/src/arch/arm64/armv8/Makefile.mk b/src/arch/arm64/armv8/Makefile.mk index 61961ff..15d80e6 100644 --- a/src/arch/arm64/armv8/Makefile.mk +++ b/src/arch/arm64/armv8/Makefile.mk @@ -13,11 +13,6 @@ ################################################################################ ifeq ($(CONFIG_ARCH_BOOTBLOCK_ARMV8_64),y) -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) -decompressor-ld-ccopts += -target arm64-elf -bootblock-ld-ccopts += -target arm64-elf -endif - ifneq ($(CONFIG_BOOTBLOCK_CUSTOM),y) decompressor-y += bootblock.S ifneq ($(CONFIG_COMPRESS_BOOTBLOCK),y) @@ -49,10 +44,6 @@ ################################################################################ ifeq ($(CONFIG_ARCH_VERSTAGE_ARMV8_64),y) -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) -verstage-ld-ccopts += -target arm64-elf -endif - verstage-y += cache.c verstage-y += cpu.S verstage-y += exception.c @@ -66,10 +57,6 @@ ################################################################################ ifeq ($(CONFIG_ARCH_ROMSTAGE_ARMV8_64),y) -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) -romstage-ld-ccopts += -target arm64-elf -endif - romstage-y += cache.c romstage-y += cpu.S romstage-y += exception.c @@ -86,10 +73,6 @@ ################################################################################ ifeq ($(CONFIG_ARCH_RAMSTAGE_ARMV8_64),y) -ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) -ramstage-ld-ccopts += -target arm64-elf -endif - ramstage-y += cache.c ramstage-y += cpu.S ramstage-y += exception.c diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 1eecc7e..68b3705 100755 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -262,6 +262,9 @@ CLANG_CFLAGS_${TARCH}+=-fbracket-depth=2048 -mllvm -asm-macro-max-nesting-depth=1000 CLANG_COMPILER_RT_${TARCH}:=${CC_RT_CLANG} CLANG_COMPILER_RT_FLAGS_${TARCH}:=${CC_RT_EXTRA_CLANG} +# Leak the target arch into the preprocessor flags with clang. +# This is needed to preprocess linker scripts +CLANG_CPPFLAGS_${TARCH}:=${CPPFLAGS_CLANG} # GCC/Clang Common ifeq (\$(CONFIG_COMPILER_GCC)\$(CONFIG_LP_COMPILER_GCC),y) @@ -272,6 +275,7 @@ else CC_${TARCH}:=\$(CLANG_CC_${TARCH}) CFLAGS_${TARCH}:=\$(CLANG_CFLAGS_${TARCH}) + CPPFLAGS_${TARCH}:=\$(CLANG_CPPFLAGS_${TARCH}) COMPILER_RT_${TARCH}:=\$(CLANG_COMPILER_RT_${TARCH}) COMPILER_RT_FLAGS_${TARCH}:=\$(CLANG_COMPILER_RT_FLAGS_${TARCH}) endif @@ -471,7 +475,9 @@ # but that's more of a clang limitation. Let's be optimistic # that this will change in the future. CLANG="${clang_prefix}clang" - CFLAGS_CLANG="-target ${clang_arch}-${TABI} $CFLAGS_CLANG" + CLANG_TARGET="-target ${clang_arch}-${TABI}" + CFLAGS_CLANG="$CLANG_TARGET $CFLAGS_CLANG" + CPPFLAGS_CLANG="$CLANG_TARGET $CPPFLAGS_CLANG" fi } -- To view, visit https://review.coreboot.org/c/coreboot/+/75031?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4340681e30059d6f18a49a49937668cd3dd39ce1 Gerrit-Change-Number: 75031 Gerrit-PatchSet: 13 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
by Jérémy Compostella (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun. Hello Andrey Petrov, Arthur Heymans, Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81212?usp=email to look at the new patch set (#6). Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache ...................................................................... drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache If SPINOR space is limited and Cache-As-RAM (CAR) is large enough, FSP can be stored compressed, loaded in CBFS cache and executed from there. It allows to reduce the FSP-M SPINOR footprint with a limited boot time penalty. `FSP_M_EXECUTE_FROM_CBFS_CACHE' Kconfig can be set to turn on this feature. We performed some measurements on a Meteor Lake Rex board with a 2 MB Cache-As-RAM (`DCACHE_RAM_SIZE' at 0x200000 and `DCACHE_RAM_BASE' 0xea000000) and a few adjustments in the FSP to enable CAR to RAM PEIM (Pre-EFI Initialization Module) drivers migration. 1. Time impact | Compression algorithm | LZ4 | LZMA | |--------------------------+----------+----------| | Decompress duration | 1.9 ms | 75.6 ms | | Overall boot time impact | +15.9 ms | +77.4 ms | The overall boot time impact increase is explained by FSP-M loading being a bit faster (-18 ms) undermined by a longer Cache-As-RAM setup (32 ms). 2. SPINOR impact | CBFS file / Compression | LZ4 | LZMA | |----------------------------+----------------+-----------------| | romstage size | +4 KB (+3%) | +10 KB (+8%) | | fspm.bin size | -313 KB (-37%) | -456 KB (-54%) | |----------------------------+----------------+-----------------| | Total Per slot | -309 KB | -446 KB | | Total for SPINOR (3 slots) | -926 KB | -1339 KB | BUG=b:329237541 TEST=Verified on rex with Cache-AS-RAM size of 2 MB Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.mk M src/drivers/intel/fsp2_0/memory_init.c M src/soc/intel/meteorlake/Kconfig 4 files changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81212/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/81212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Gerrit-Change-Number: 81212 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/brox: Fix GPE_EC_WAKE configuration
by Keith Short (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Karthik Ramasubramanian, Keith Short, Nick Vaccaro, Shelley Chen, Shyam Sundar Radjacoumar. Keith Short has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81526?usp=email ) Change subject: mb/google/brox: Fix GPE_EC_WAKE configuration ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS3: I ran `suspend_stress_test -c 10` with sensors enabled. This passed in clamshell and tablet mode. -- To view, visit https://review.coreboot.org/c/coreboot/+/81526?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifb89bd0de7b7fc316792e801ed5a1d3f25ca5b1c Gerrit-Change-Number: 81526 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)chromium.org> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 22:30:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
by Jérémy Compostella (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun. Hello Andrey Petrov, Arthur Heymans, Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81212?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache ...................................................................... drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache If SPINOR space is limited and Cache-As-RAM (CAR) is large enough, FSP can be stored compressed, loaded in CBFS cache and executed from there. It allows to reduce the FSP-M SPINOR footprint with a limited boot time penalty. `FSP_EXECUTE_FROM_CBFS_CACHE' Kconfig can be set to turn on this feature. We performed some measurements on a Meteor Lake Rex board with a 2 MB Cache-As-RAM (`DCACHE_RAM_SIZE' at 0x200000 and `DCACHE_RAM_BASE' 0xea000000) and a few adjustments in the FSP to enable CAR to RAM PEIM (Pre-EFI Initialization Module) drivers migration. 1. Time impact | Compression algorithm | LZ4 | LZMA | |--------------------------+----------+----------| | Decompress duration | 1.9 ms | 75.6 ms | | Overall boot time impact | +15.9 ms | +77.4 ms | The overall boot time impact increase is explained by FSP-M loading being a bit faster (-18 ms) undermined by a longer Cache-As-RAM setup (32 ms). 2. SPINOR impact | CBFS file / Compression | LZ4 | LZMA | |----------------------------+----------------+-----------------| | romstage size | +4 KB (+3%) | +10 KB (+8%) | | fspm.bin size | -313 KB (-37%) | -456 KB (-54%) | |----------------------------+----------------+-----------------| | Total Per slot | -309 KB | -446 KB | | Total for SPINOR (3 slots) | -926 KB | -1339 KB | BUG=b:329237541 TEST=Verified on rex with Cache-AS-RAM size of 2 MB Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.mk M src/drivers/intel/fsp2_0/memory_init.c M src/soc/intel/meteorlake/Kconfig 4 files changed, 24 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81212/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/81212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Gerrit-Change-Number: 81212 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: superio/ite: Fix incorrect warnings
by Nico Huber (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Joel Linn. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81516?usp=email ) Change subject: superio/ite: Fix incorrect warnings ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81516?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibabe1b1ef55f2acb2074eceb535ec684bffc8155 Gerrit-Change-Number: 81516 Gerrit-PatchSet: 2 Gerrit-Owner: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Joel Linn <jl_coreboot(a)conductive.de> Gerrit-Comment-Date: Tue, 26 Mar 2024 22:12:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brox: Fix GPE_EC_WAKE configuration
by Karthik Ramasubramanian (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Keith Short, Shelley Chen, Shyam Sundar Radjacoumar. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81526?usp=email ) Change subject: mb/google/brox: Fix GPE_EC_WAKE configuration ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > unresolving Yes, they are all working fine with this change. -- To view, visit https://review.coreboot.org/c/coreboot/+/81526?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifb89bd0de7b7fc316792e801ed5a1d3f25ca5b1c Gerrit-Change-Number: 81526 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Shyam Sundar Radjacoumar <ssradjacoumar(a)google.com> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 22:07:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brox: Fix GPE_EC_WAKE configuration
by Karthik Ramasubramanian (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Karthik Ramasubramanian, Keith Short. Hello Keith Short, Shelley Chen, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81526?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/brox: Fix GPE_EC_WAKE configuration ...................................................................... mb/google/brox: Fix GPE_EC_WAKE configuration Wake signal from EC is routed to GPP_D1 and hence GPE_EC_WAKE corresponds to GPE0_DW1_01. Fix GPE_EC_WAKE configuration. BUG=b:329026602 TEST=Build Brox BIOS image and boot to OS. Trigger suspend and wake up using EC generated events like AC connect/disconnect. Change-Id: Ifb89bd0de7b7fc316792e801ed5a1d3f25ca5b1c Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/ec.h M src/mainboard/google/brox/variants/baseboard/brox/include/baseboard/gpio.h 2 files changed, 4 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/81526/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81526?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifb89bd0de7b7fc316792e801ed5a1d3f25ca5b1c Gerrit-Change-Number: 81526 Gerrit-PatchSet: 3 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/google/brox: Fix GPE_EC_WAKE configuration
by Shelley Chen (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Karthik Ramasubramanian, Keith Short. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81526?usp=email ) Change subject: mb/google/brox: Fix GPE_EC_WAKE configuration ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: > Does suspend_stress_test and powerd_dbus_suspend still work with this change? unresolving -- To view, visit https://review.coreboot.org/c/coreboot/+/81526?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifb89bd0de7b7fc316792e801ed5a1d3f25ca5b1c Gerrit-Change-Number: 81526 Gerrit-PatchSet: 2 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 21:36:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
by Jérémy Compostella (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81212?usp=email ) Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache ...................................................................... Patch Set 3: (2 comments) Patchset: PS3: > I'm a bit confused how this works. FSP-M needs to be relocated at runtime for this to work. I was not aware that this code exist in romstage or did I miss something? The FSP relocation code exists in romstage if `FSP_M_XIP` is not set (cf. src/commonlib/Makefile.mk) and quick (about 1 ms on my Meteor Lake rex board). > Executing FSP-M in CAR is not a new thing. Intel APL/GLK does that, but in that case the FSP-M add is fixed at buildtime CONFIG_FSP_M_ADDR. Relocation is handled at buildtime. I'm wondering if that would not be a better idea than using the cbfs cache.? The point is to leverage the simplicity of the CBFS cache infrastructure for decompression and execution. That way the execution address does not need to be known at compilation time. The idea is to offer a flexible and simple alternative levering CBFS cache. File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/81212/comment/f0436d91_15edc019 : PS3, Line 221: FSP_EXECUTE_FROM_CBFS_CACHE > Can you add an assert (I think makefile is easiest) that FSP-M is at least smaller than the cache? This is a good suggestion and I implemented it. However, I am not really proud of the target I bound it to. I could not find another one "within the right scope" so far. Any better suggestion ? -- To view, visit https://review.coreboot.org/c/coreboot/+/81212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Gerrit-Change-Number: 81212 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 26 Mar 2024 21:26:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
by Jérémy Compostella (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Andrey Petrov, Bora Guvendik, Jérémy Compostella, Paul Menzel, Ronak Kanabar, Shuo Liu. Hello Andrey Petrov, Arthur Heymans, Bora Guvendik, Paul Menzel, Ronak Kanabar, Shuo Liu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81212?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache ...................................................................... drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache If SPINOR space is limited and Cache-As-RAM (CAR) is large enough, FSP can be stored compressed, loaded in CBFS cache and executed from there. It allows to reduce the FSP-M SPINOR footprint with a limited boot time penalty. `FSP_EXECUTE_FROM_CBFS_CACHE' Kconfig can be set to turn on this feature. We performed some measurements on a Meteor Lake Rex board with a 2 MB Cache-As-RAM (`DCACHE_RAM_SIZE' at 0x200000 and `DCACHE_RAM_BASE' 0xea000000) and a few adjustments in the FSP to enable CAR to RAM PEIM (Pre-EFI Initialization Module) drivers migration. 1. Time impact | Compression algorithm | LZ4 | LZMA | |--------------------------+----------+----------| | Decompress duration | 1.9 ms | 75.6 ms | | Overall boot time impact | +15.9 ms | +77.4 ms | The overall boot time impact increase is explained by FSP-M loading being a bit faster (-18 ms) undermined by a longer Cache-As-RAM setup (32 ms). 2. SPINOR impact | CBFS file / Compression | LZ4 | LZMA | |----------------------------+----------------+-----------------| | romstage size | +4 KB (+3%) | +10 KB (+8%) | | fspm.bin size | -313 KB (-37%) | -456 KB (-54%) | |----------------------------+----------------+-----------------| | Total Per slot | -309 KB | -446 KB | | Total for SPINOR (3 slots) | -926 KB | -1339 KB | BUG=b:329237541 TEST=Verified on rex with Cache-AS-RAM size of 2 MB Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.mk M src/drivers/intel/fsp2_0/memory_init.c M src/soc/intel/meteorlake/Kconfig 4 files changed, 23 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81212/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Gerrit-Change-Number: 81212 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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