coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/cavium: Remove blank lines before '}' and after '{'
by Elyes Haouas (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Felix Singer. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81470?usp=email ) Change subject: soc/cavium: Remove blank lines before '}' and after '{' ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Squash into CB:81457 why? -- To view, visit https://review.coreboot.org/c/coreboot/+/81470?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id604dc981d6ca0a8163b7477b7916210faa56a77 Gerrit-Change-Number: 81470 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Wed, 27 Mar 2024 06:07:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/emulation: Remove blank lines before '}' and after '{'
by Elyes Haouas (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Felix Singer, ron minnich. Elyes Haouas has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81465?usp=email ) Change subject: mb/emulation: Remove blank lines before '}' and after '{' ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: > Squash into CB:81461 why? -- To view, visit https://review.coreboot.org/c/coreboot/+/81465?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7071cbcc26e2080020e83b894cf4ac4ef46913c3 Gerrit-Change-Number: 81465 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 06:06:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/purism: Remove blank lines before '}' and after '{'
by Elyes Haouas (Code Review) 27 Mar '24

27 Mar '24

Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81488?usp=email ) Change subject: mb/purism: Remove blank lines before '}' and after '{' ...................................................................... mb/purism: Remove blank lines before '}' and after '{' Change-Id: I2285d1bdaa2734658ca1a0cc58ef2294d90d333e Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81488 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Jonathon Hall <jonathon.hall(a)puri.sm> --- M src/mainboard/purism/librem_cnl/romstage.c M src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c M src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c M src/mainboard/purism/librem_jsl/gpio.h M src/mainboard/purism/librem_l1um_v2/gpio.h 5 files changed, 0 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Jonathon Hall: Looks good to me, approved diff --git a/src/mainboard/purism/librem_cnl/romstage.c b/src/mainboard/purism/librem_cnl/romstage.c index 5d92316..e007fd3 100644 --- a/src/mainboard/purism/librem_cnl/romstage.c +++ b/src/mainboard/purism/librem_cnl/romstage.c @@ -12,7 +12,6 @@ FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; struct cnl_mb_cfg memcfg = { - /* * Rcomp resistor values. These values represent the resistance in * ohms of the three rcomp resistors attached to the DDR_COMP_0, diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c index e5c1a6f..0ec3947 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_14/gpio.c @@ -4,7 +4,6 @@ /* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { - /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - RCIN# */ diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c index 24ed2be..b894bcb 100644 --- a/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c +++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/gpio.c @@ -4,7 +4,6 @@ /* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { - /* ------- GPIO Group GPP_A ------- */ /* GPP_A0 - RCIN# */ diff --git a/src/mainboard/purism/librem_jsl/gpio.h b/src/mainboard/purism/librem_jsl/gpio.h index 79148ea..5c00f6d 100644 --- a/src/mainboard/purism/librem_jsl/gpio.h +++ b/src/mainboard/purism/librem_jsl/gpio.h @@ -6,7 +6,6 @@ #include <gpio.h> static const struct pad_config gpio_table[] = { - /* ------- GPIO Community 1 ------- */ /* ------- GPIO Group GPP_G ------- */ diff --git a/src/mainboard/purism/librem_l1um_v2/gpio.h b/src/mainboard/purism/librem_l1um_v2/gpio.h index 8325b69..f6a4d0d 100644 --- a/src/mainboard/purism/librem_l1um_v2/gpio.h +++ b/src/mainboard/purism/librem_l1um_v2/gpio.h @@ -25,7 +25,6 @@ /* Pad configuration was generated automatically using intelp2m utility */ static const struct pad_config gpio_table[] = { - /* ------- GPIO Community 0 ------- */ /* ------- GPIO Group GPP_A ------- */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81488?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2285d1bdaa2734658ca1a0cc58ef2294d90d333e Gerrit-Change-Number: 81488 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC
by SH Kim (Code Review) 27 Mar '24

27 Mar '24

SH Kim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81444?usp=email ) Change subject: mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC ...................................................................... mb/google/brya/var/xol: Update GPIO settings for speaker and DMIC Update GPIO configuration according to the schematic changes: - Speaker: I2S2 -> I2S1 - DMIC: GPP_S2/GPP_S3 -> GPP_R4/GPP_R5 BUG=b:318584606 TEST=FW_NAME=xol emerge-brya coreboot chromeos-bootimage Change-Id: I3468d79f33d9d9ef8377ccf0f8f628956b02d3c3 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> --- M src/mainboard/google/brya/variants/xol/gpio.c 1 file changed, 14 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/44/81444/1 diff --git a/src/mainboard/google/brya/variants/xol/gpio.c b/src/mainboard/google/brya/variants/xol/gpio.c index 3a92b8e..3192883 100644 --- a/src/mainboard/google/brya/variants/xol/gpio.c +++ b/src/mainboard/google/brya/variants/xol/gpio.c @@ -151,13 +151,23 @@ /* H23 : SRCCLKREQ5# ==> PU 100K 3.3V */ PAD_CFG_GPI(GPP_H23, NONE, DEEP), + /* R4 : HDA_RST# ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), + /* R5 : HDA_SDI1 ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), + /* R6 : I2S2_TXD ==> NC */ + PAD_NC(GPP_R6, NONE), /* R7 : I2S2_RXD ==> NC */ PAD_NC(GPP_R7, NONE), - /* S0 : SNDW0_CLK ==> NC */ - PAD_NC(GPP_S0, NONE), - /* S1 : SNDW0_DATA ==> NC */ - PAD_NC(GPP_S1, NONE), + /* S0 : SNDW0_CLK ==> SDW_HP_CLK_R */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), + /* S1 : SNDW0_DATA ==> SDW_HP_DATA_R */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), + /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), + /* S3 : SNDW1_DATA ==> NC */ + PAD_NC(GPP_S3, NONE), /* S4 : SNDW2_CLK ==> NC */ PAD_NC(GPP_S4, NONE), /* S5 : SNDW2_DATA ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81444?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3468d79f33d9d9ef8377ccf0f8f628956b02d3c3 Gerrit-Change-Number: 81444 Gerrit-PatchSet: 1 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params
by Ashish Kumar Mishra (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Paul Menzel. Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81437?usp=email ) Change subject: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81437/comment/c5a9fad9_055fa8df : PS3, Line 15: [NOTE ] Defaulting to using DDR4 params. Please add dram_type check for : 21 to use_ddr4_params > Please use one line and indent it by four spaces. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Gerrit-Change-Number: 81437 Gerrit-PatchSet: 4 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 27 Mar 2024 05:41:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params
by Ashish Kumar Mishra (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Ashish Kumar Mishra. Hello Karthik Ramasubramanian, Shelley Chen, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81437?usp=email to look at the new patch set (#4). Change subject: lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params ...................................................................... lib/spd_bin: Add LPDDR5X dram_type in use_ddr4_params For dram_type 21 the switch case in use_ddr4_params function falls to default. This adds SPD_DRAM_LPDDR5X dram_type case to switch case block for dram_type 21 in the function. With this patch below NOTE will not be observed in the log: [NOTE ] Defaulting to using DDR4 params. Please add dram_type check for 21 to use_ddr4_params Bug=None BRANCH=None TEST=Boot brox SKU1/SKU2 and verify logs for default case Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> --- M src/lib/spd_bin.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/81437/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/81437?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id78ef90c0dc2e869c1f0424674b982ba64ba3939 Gerrit-Change-Number: 81437 Gerrit-PatchSet: 4 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
by Subrata Banik (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Paul Menzel, Ronak Kanabar, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81212?usp=email ) Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81212/comment/47b28e8e_8d2c405b : PS6, Line 42: 2 MB i have worked on an Intel project where the CAR size is 1.25MB even. How do we expect the SoC user to test if this code is working on all different batches of the SOC generation. -- To view, visit https://review.coreboot.org/c/coreboot/+/81212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Gerrit-Change-Number: 81212 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 05:33:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
by Subrata Banik (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Paul Menzel, Ronak Kanabar, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81212?usp=email ) Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache ...................................................................... Patch Set 6: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/81212/comment/5d563061_096e79ee : PS6, Line 225: Select this value when FSP-M executes from CBFS cache. i guess the assumptions are not drafted properly about how much temp memory is required to support this feature. For example: FSP-M size is growing and what if the underlying SOC CAR doesn't have ample memory (like celeron skus) then we might see abrupt failure during boot. Early decompression only makes sense when we have fallback memory to support with like SRAM. relying on CAR memory may not be scalable because we can't read the max CAR size and availability to choose if we wish to do XIP or copy FSP-M into temp memory and run. Based on my understanding, this feature is better not to enable on Intel SoC unless there are some SRAM or fixed memory available. -- To view, visit https://review.coreboot.org/c/coreboot/+/81212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Gerrit-Change-Number: 81212 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 05:32:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Paul Menzel, Ronak Kanabar, Subrata Banik, Tarun. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81212?usp=email ) Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache ...................................................................... Patch Set 6: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/81212/comment/391f147f_4e151db5 : PS6, Line 225: Select this value when FSP-M executes from CBFS cache. Maybe we can comment here, if FSP-M is compressed, it will be decompressed into PRERAM_CBFS_CACHE, otherwise, will be XIP. -- To view, visit https://review.coreboot.org/c/coreboot/+/81212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Gerrit-Change-Number: 81212 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 02:38:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
by Shuo Liu (Code Review) 26 Mar '24

26 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Paul Menzel, Ronak Kanabar, Subrata Banik, Tarun. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81212?usp=email ) Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache ...................................................................... Patch Set 6: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/81212/comment/f02af2f7_3595634f : PS6, Line 221: config FSP_M_EXECUTE_FROM_CBFS_CACHE I realized that PRERAM_CBFS_CACHE is a must item in car now, if there is an Kconfig like USE_PRERAM_CBFS_CACHE and we depend this new Kconfig on USE_PRERAM_CBFS_CACHE, it would be more clear to users. -- To view, visit https://review.coreboot.org/c/coreboot/+/81212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Gerrit-Change-Number: 81212 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 02:33:40 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit March 2024