coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: cpu/x86/topology: Add node ID parser
by Shuo Liu (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81515?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: cpu/x86/topology: Add node ID parser ...................................................................... Patch Set 5: Code-Review+2 (1 comment) File src/cpu/x86/topology.c: https://review.coreboot.org/c/coreboot/+/81515/comment/2fb30cfa_ffd2f2a0 : PS5, Line 64: void set_cpu_node_id_leaf_1f_b(struct device *cpu) maybe it would be helpful to add a parameter to indicate the level type to query, and return error when the level type doesn't exist. -- To view, visit https://review.coreboot.org/c/coreboot/+/81515?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia3ed1e5923aa18ca7619b32cde491fdb4da0fa0d Gerrit-Change-Number: 81515 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 10:56:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
by Paul Menzel (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, SH Kim, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81436?usp=email ) Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits() ...................................................................... Patch Set 5: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81436/comment/56de6b2c_bd1c77c9 : PS5, Line 14: ramstage.c : Please remove the space before the colon. https://review.coreboot.org/c/coreboot/+/81436/comment/b0dd91c9_bca02a87 : PS5, Line 15: const struct cpu_power_limits limits[] = { : {PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000}, : } Please follow Markdown mark-up language and indent with four spaces. -- To view, visit https://review.coreboot.org/c/coreboot/+/81436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Gerrit-Change-Number: 81436 Gerrit-PatchSet: 5 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 27 Mar 2024 10:43:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL
by Paul Menzel (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Kilari Raasi, Nick Vaccaro, Ronak Kanabar, Subrata Banik. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81446?usp=email ) Change subject: intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL ...................................................................... Patch Set 1: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81446/comment/87a6979c_61c32f8f : PS1, Line 10: And it prevents the boot time increase. Please document the measurements in the commit message. https://review.coreboot.org/c/coreboot/+/81446/comment/8ba706c6_59187977 : PS1, Line 11: Why was it added in the first place, and why can it be removed now? -- To view, visit https://review.coreboot.org/c/coreboot/+/81446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 Gerrit-Change-Number: 81446 Gerrit-PatchSet: 1 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilari Raasi <kilari.raasi(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 10:39:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
by Sumeet R Pawnikar (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, SH Kim, Subrata Banik. Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81436?usp=email ) Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits() ...................................................................... Patch Set 5: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81436/comment/785acea0_7a097c28 : PS5, Line 13: override the PL4 value Please share more details on the reason for overriding the PL4 value. AFAIK user space overrides only PL1/PL2. There is no specific requirement/need for overriding PL4 value from user space. File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c: https://review.coreboot.org/c/coreboot/+/81436/comment/7f5c5902_d407d8f5 : PS5, Line 39: Any reason to removal of these? It was aligned based on the previous argument. https://review.coreboot.org/c/coreboot/+/81436/comment/55c0a9ba_d0e95a73 : PS5, Line 41: same comment as above. https://review.coreboot.org/c/coreboot/+/81436/comment/3747a278_e79e4bcb : PS5, Line 68: soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power, > > The override table has PL1/PL2 min/max values. […] DPTF (user space service) overrides PL1/PL2 for MMIO registers only. -- To view, visit https://review.coreboot.org/c/coreboot/+/81436?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53 Gerrit-Change-Number: 81436 Gerrit-PatchSet: 5 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 27 Mar 2024 10:25:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL
by Kilari Raasi (Code Review) 27 Mar '24

27 Mar '24

Kilari Raasi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81446?usp=email ) Change subject: intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL ...................................................................... intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL By removing FSP_PUBLISH_MBP_HOB for RPL SkipMbpHob is set to 0. And it prevents the boot time increase. BUG=b:328430167 TEST= Able to build and boot brya Signed-off-by: Kilari Raasi <kilari.raasi(a)intel.com> Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/81446/1 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 01d5f89..b8ccd5d 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -517,7 +517,7 @@ config FSP_PUBLISH_MBP_HOB bool - default n if CHROMEOS && (SOC_INTEL_RAPTORLAKE || SOC_INTEL_ALDERLAKE_PCH_N) + default n if CHROMEOS && (SOC_INTEL_ALDERLAKE_PCH_N) default y help This is to control creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. -- To view, visit https://review.coreboot.org/c/coreboot/+/81446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 Gerrit-Change-Number: 81446 Gerrit-PatchSet: 1 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr: Enable x86_64 support
by Lean Sheng Tan (Code Review) 27 Mar '24

27 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81280?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp/spr: Enable x86_64 support ...................................................................... soc/intel/xeon_sp/spr: Enable x86_64 support Fix compilation errors when compiled for x86_64. Test: Booted on ibm/sbp1 to linux payload. Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Signed-off-by: Arthur Heymans <arthur.heymans(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81280 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Nico Huber <nico.h(a)gmx.de> --- M src/soc/intel/xeon_sp/spr/Kconfig M src/soc/intel/xeon_sp/spr/romstage.c M src/soc/intel/xeon_sp/spr/upd_display.c 3 files changed, 6 insertions(+), 5 deletions(-) Approvals: Nico Huber: Looks good to me, but someone else must approve build bot (Jenkins): Verified Jérémy Compostella: Looks good to me, approved Shuo Liu: Looks good to me, but someone else must approve diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig index 3c3c45a..23d2f8b6 100644 --- a/src/soc/intel/xeon_sp/spr/Kconfig +++ b/src/soc/intel/xeon_sp/spr/Kconfig @@ -16,6 +16,7 @@ select FSP_SPEC_VIOLATION_XEON_SP_HEAP_WORKAROUND select UDK_202005_BINDING select SOC_INTEL_HAS_CXL + select HAVE_EXP_X86_64_SUPPORT help Intel Sapphire Rapids-SP support diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 3b38828..91d2099 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -114,7 +114,7 @@ { unsigned int port, socket; - mupd->FspmConfig.IioPcieConfigTablePtr = (UINT32)spr_iio_bifur_table; + mupd->FspmConfig.IioPcieConfigTablePtr = (uintptr_t)spr_iio_bifur_table; /* MAX_SOCKET is the maximal number defined by FSP, currently is 4. */ mupd->FspmConfig.IioPcieConfigTableNumber = MAX_SOCKET; UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = @@ -130,7 +130,7 @@ PciePortConfig[socket].PcieMaxReadRequestSize = 0x5; } - mupd->FspmConfig.DeEmphasisPtr = (UINT32)deemphasis_list; + mupd->FspmConfig.DeEmphasisPtr = (uintptr_t)deemphasis_list; mupd->FspmConfig.DeEmphasisNumber = MAX_SOCKET * MAX_IIO_PORTS_PER_SOCKET; UINT8 *DeEmphasisConfig = (UINT8 *)deemphasis_list; @@ -287,7 +287,7 @@ UPD_IIO_PCIE_PORT_CONFIG *iio_pcie_cfg; int socket; - iio_pcie_cfg = (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr; + iio_pcie_cfg = (UPD_IIO_PCIE_PORT_CONFIG *)(uintptr_t)mupd->FspmConfig.IioPcieConfigTablePtr; for (socket = 0; socket < MAX_SOCKET; socket++) iio_pcie_cfg[socket].PcieGlobalAspm = 0; diff --git a/src/soc/intel/xeon_sp/spr/upd_display.c b/src/soc/intel/xeon_sp/spr/upd_display.c index c69a9a0..b3c0c7c 100644 --- a/src/soc/intel/xeon_sp/spr/upd_display.c +++ b/src/soc/intel/xeon_sp/spr/upd_display.c @@ -12,7 +12,7 @@ int port, socket; UPD_IIO_PCIE_PORT_CONFIG *PciePortConfig = - (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr; + (UPD_IIO_PCIE_PORT_CONFIG *)(uintptr_t)mupd->FspmConfig.IioPcieConfigTablePtr; printk(BIOS_SPEW, "UPD values for IIO:\n"); for (socket = 0; socket < mupd->FspmConfig.IioPcieConfigTableNumber; socket++) { @@ -94,7 +94,7 @@ PciePortConfig[socket].PcieMaxReadRequestSize); } - UINT8 *DeEmphasisConfig = (UINT8 *)mupd->FspmConfig.DeEmphasisPtr; + UINT8 *DeEmphasisConfig = (UINT8 *)(uintptr_t)mupd->FspmConfig.DeEmphasisPtr; for (port = 0; port < mupd->FspmConfig.DeEmphasisNumber; port++) { printk(BIOS_SPEW, "port: %d, DeEmphasisConfig: 0x%x\n", port, DeEmphasisConfig[port]); -- To view, visit https://review.coreboot.org/c/coreboot/+/81280?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2c5ed0339a9c2e9b088b16dbb4c19df98e796d65 Gerrit-Change-Number: 81280 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/google/brox: Enable PMC pins to work with PD
by Ashish Kumar Mishra (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Deepti Deshatty, Shelley Chen. Ashish Kumar Mishra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81207?usp=email ) Change subject: mb/google/brox: Enable PMC pins to work with PD ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/81207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10 Gerrit-Change-Number: 81207 Gerrit-PatchSet: 1 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 08:55:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/glassway: Update the VccIn Aux Imon IccMax
by Shawn Ku (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Frank Chu, Kapil Porwal, Nick Vaccaro, Subrata Banik. Shawn Ku has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81445?usp=email ) Change subject: mb/google/nissa/var/glassway: Update the VccIn Aux Imon IccMax ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I105dc9df53c624fd7fc697408a1097e023a3cd68 Gerrit-Change-Number: 81445 Gerrit-PatchSet: 6 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 27 Mar 2024 08:18:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/glassway: Update the VccIn Aux Imon IccMax
by Frank Chu (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Shawn Ku, Subrata Banik. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81445?usp=email ) Change subject: mb/google/nissa/var/glassway: Update the VccIn Aux Imon IccMax ...................................................................... Patch Set 6: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I105dc9df53c624fd7fc697408a1097e023a3cd68 Gerrit-Change-Number: 81445 Gerrit-PatchSet: 6 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Shawn Ku <shawnku(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 27 Mar 2024 07:37:07 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/nissa/var/glassway: Update the VccIn Aux Imon IccMax
by Frank Chu (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, Shawn Ku, Subrata Banik. Frank Chu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81445?usp=email ) Change subject: mb/google/nissa/var/glassway: Update the VccIn Aux Imon IccMax ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81445?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I105dc9df53c624fd7fc697408a1097e023a3cd68 Gerrit-Change-Number: 81445 Gerrit-PatchSet: 5 Gerrit-Owner: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shawn Ku <shawnku(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Shawn Ku <shawnku(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Wed, 27 Mar 2024 07:35:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit March 2024