coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: volteer: Return MCACHE_SIZE to its old value if using vboot
by Varshit Pandya (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Nick Vaccaro, Vladimir Serbinenko. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81512?usp=email ) Change subject: volteer: Return MCACHE_SIZE to its old value if using vboot ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81512/comment/d1938600_f378460d : PS6, Line 7: volteer "mb/google/volteer" instead of just "volteer" -- To view, visit https://review.coreboot.org/c/coreboot/+/81512?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I52d91fffd34e8f62dcb23cea588bf465291a1f45 Gerrit-Change-Number: 81512 Gerrit-PatchSet: 6 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 12:08:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL
by Subrata Banik (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Kilari Raasi, Nick Vaccaro, Paul Menzel, Ronak Kanabar. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81446?usp=email ) Change subject: intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81446/comment/c036dcea_576cff84 : PS2, Line 8: : By removing FSP_PUBLISH_MBP_HOB for RPL SkipMbpHob is set to 0. : And it prevents the boot time increase of ~158ms. i guess you are presenting the twisted fact here, ideally we wish to avoid sending MBP cmd and create HOB to save boot time. Based on our experience it saves 10-20ms of boot time. CB:71873 Now, Intel CSE has been experiencing some boot delay without sending MBP cmd due to some other issue (which is yet to debug) and setting SkipMbpHob=0 is helping Intel CSE/FSP to avoid additional boot penalty. Ideally, we should be root causing why SkipMbpHob=1 is causing the issue all of a sudden. Until then please specify this is a W/A and not final fix. https://review.coreboot.org/c/coreboot/+/81446/comment/3b15750c_aa3b6872 : PS2, Line 18: With without File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/81446/comment/5a6466b7_af503f71 : PS2, Line 529: RPL consider changing this now? -- To view, visit https://review.coreboot.org/c/coreboot/+/81446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 Gerrit-Change-Number: 81446 Gerrit-PatchSet: 2 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilari Raasi <kilari.raasi(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 12:06:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/brox: Enable PMC pins to work with PD
by Varshit Pandya (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Ashish Kumar Mishra, Deepti Deshatty, Shelley Chen. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81207?usp=email ) Change subject: mb/google/brox: Enable PMC pins to work with PD ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81207/comment/fd57fb6a_c3e46adc : PS1, Line 9: For PMC-PD communication we need to enable 3 pins. since you are configuring pins to native function, it would be good to mention what is that native function and according to which document have you updated it ? (doc number, rev and table name) -- To view, visit https://review.coreboot.org/c/coreboot/+/81207?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia678d291e7a14aefe09026e70478fea3f68c8e10 Gerrit-Change-Number: 81207 Gerrit-PatchSet: 1 Gerrit-Owner: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-Attention: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 12:03:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL
by Kilari Raasi (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Kilari Raasi, Nick Vaccaro, Paul Menzel, Ronak Kanabar, Subrata Banik. Kilari Raasi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81446?usp=email ) Change subject: intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81446/comment/82436501_6fe92153 : PS1, Line 10: And it prevents the boot time increase. > Please document the measurements in the commit message. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 Gerrit-Change-Number: 81446 Gerrit-PatchSet: 2 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilari Raasi <kilari.raasi(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 11:46:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL
by Kilari Raasi (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Kilari Raasi, Nick Vaccaro, Ronak Kanabar, Subrata Banik. Hello Dinesh Gehlot, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81446?usp=email to look at the new patch set (#2). Change subject: intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL ...................................................................... intel/alderlake: Remove FSP_PUBLISH_MBP_HOB config for RPL By removing FSP_PUBLISH_MBP_HOB for RPL SkipMbpHob is set to 0. And it prevents the boot time increase of ~158ms. BUG=b:328430167 TEST= Able to build,boot and collect boot time data of brya. With SkipMpbpHob = 0: 963:returning from FspMultiPhaseSiInit 1,337,481 (249,046) With SkipMbpHob = 1: 963:returning from FspMultiPhaseSiInit 1,496,268 (408,194) Signed-off-by: Kilari Raasi <kilari.raasi(a)intel.com> Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 --- M src/soc/intel/alderlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/81446/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81446?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8a99a57b644732074e41051d99e63576f1edd229 Gerrit-Change-Number: 81446 Gerrit-PatchSet: 2 Gerrit-Owner: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kilari Raasi <kilari.raasi(a)intel.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kilari Raasi <kilari.raasi(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: cpu/x86/topology: Add node ID parser
by Shuo Liu (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81515?usp=email ) Change subject: cpu/x86/topology: Add node ID parser ...................................................................... Patch Set 5: (2 comments) File src/cpu/x86/topology.c: https://review.coreboot.org/c/coreboot/+/81515/comment/40715567_a57aa2b3 : PS5, Line 64: void set_cpu_node_id_leaf_1f_b(struct device *cpu) > Why? get_cpu_package_bits returns the higest level type, no matter how many level's there are, and t […] Acknowledged https://review.coreboot.org/c/coreboot/+/81515/comment/047b1ff0_2d5cffbf : PS5, Line 158: package_id = apicid >> (thread_bits + core_bits); will the package bits be obtained by get_cpu_package_bits as well? -- To view, visit https://review.coreboot.org/c/coreboot/+/81515?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia3ed1e5923aa18ca7619b32cde491fdb4da0fa0d Gerrit-Change-Number: 81515 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 11:39:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/google/brya/var/bujia: Update devicetree setting
by Shon Wang (Code Review) 27 Mar '24

27 Mar '24

Shon Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81447?usp=email ) Change subject: mb/google/brya/var/bujia: Update devicetree setting ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/81447?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia010e99c21e8d6088f6bb873f79dc19cadc9e455 Gerrit-Change-Number: 81447 Gerrit-PatchSet: 2 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Kevin Chiu <kevin.chiu.17802(a)gmail.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 11:30:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: mb/google/brya/var/bujia: Update devicetree setting
by Shon Wang (Code Review) 27 Mar '24

27 Mar '24

Shon Wang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81447?usp=email ) Change subject: mb/google/brya/var/bujia: Update devicetree setting ...................................................................... mb/google/brya/var/bujia: Update devicetree setting Update devicetree setting per the schematic. it compare with gladios. 1.remove SD reader 2.remove EMMC setting 3.modify USB port distribution BUG=b:327549688 TEST= USE="-project_all project_bujia" emerge-brask coreboot Change-Id: Ia010e99c21e8d6088f6bb873f79dc19cadc9e455 --- M src/mainboard/google/brya/variants/bujia/overridetree.cb 1 file changed, 302 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/81447/1 diff --git a/src/mainboard/google/brya/variants/bujia/overridetree.cb b/src/mainboard/google/brya/variants/bujia/overridetree.cb index 4f2c04a..17f74a39 100644 --- a/src/mainboard/google/brya/variants/bujia/overridetree.cb +++ b/src/mainboard/google/brya/variants/bujia/overridetree.cb @@ -1,6 +1,307 @@ chip soc/intel/alderlake + register "sagv" = "SaGv_Enabled" + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI1 | NC | + #| I2C0 | Audio | + #| I2C1 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| I2C3 | NC | + #| I2C5 | NC | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + .i2c[1] = { + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 600, + .fall_time_ns = 400, + .data_hold_time_ns = 50, + }, + }" + + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # USB2 Port 3 - Port 5 for OPS interface + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable Port 6 + + register "usb3_ports[2]" = "USB3_PORT_EMPTY " # Disable Port 2 + # USB3 Port 3 for OPS interface + + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" # Disable Port1 + register "tcss_ports[2]" = "TCSS_PORT_EMPTY" # Disable Port2 + + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + }" + + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" device domain 0 on - end + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM"" + register "options.tsr[1].desc" = ""Charger"" + # TODO: below values are initial reference values only + ## Active Policy + register "policies.active" = "{ + [0] = { + .target = DPTF_CPU, + .thresholds = { + TEMP_PCT(85, 90), + TEMP_PCT(80, 80), + TEMP_PCT(75, 70), + } + } + }" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 95, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 75, 5000), + [2] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_1, 75, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 85, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 85, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 3000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + ## Fan Performance Control (Percent, Speed, Noise, Power) + register "controls.fan_perf" = "{ + [0] = { 90, 6700, 220, 2200, }, + [1] = { 80, 5800, 180, 1800, }, + [2] = { 70, 5000, 145, 1450, }, + [3] = { 60, 4900, 115, 1150, }, + [4] = { 50, 3838, 90, 900, }, + [5] = { 40, 2904, 55, 550, }, + [6] = { 30, 2337, 30, 300, }, + [7] = { 20, 1608, 15, 150, }, + [8] = { 10, 800, 10, 100, }, + [9] = { 0, 0, 0, 50, } + }" + + ## Fan options + register "options.fan.fine_grained_control" = "1" + register "options.fan.step_size" = "2" + + device generic 0 alias dptf_policy on end + end + end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 0 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end #NVME + device ref tbt_pcie_rp0 off end + device ref tbt_pcie_rp1 off end + device ref tbt_pcie_rp2 off end + + device ref tcss_dma0 off end + device ref tcss_dma1 off end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5650"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5650"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_A23)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-mode"" + register "property_list[0].integer" = "2" + device i2c 1a on end + end + end # I2C0 + device ref i2c1 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_A13_IRQ)" + device i2c 50 on end + end + end # I2C1 + device ref pcie_rp7 on + chip drivers/net + register "wake" = "GPE0_DW0_07" + register "customized_leds" = "0x060f" + register "enable_aspm_l1_2" = "1" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end # RTL8111 Ethernet NIC + device ref pcie_rp8 off end # disable SD reader + device ref gspi1 off end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port1 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A3 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 OPS interface TX25A"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 OPS interface TX25A"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(5, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 OPS interface TX25A"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(6, 1))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 1))" + device ref usb2_port8 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(8, 1))" + device ref usb2_port9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = + "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(8, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, CENTER, ACPI_PLD_GROUP(7, 1))" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 OPS interface TX25A"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(BACK, CENTER, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port4 on end + end + end + end + end + end end -- To view, visit https://review.coreboot.org/c/coreboot/+/81447?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia010e99c21e8d6088f6bb873f79dc19cadc9e455 Gerrit-Change-Number: 81447 Gerrit-PatchSet: 1 Gerrit-Owner: Shon Wang <shon.wang(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: cpu/x86/topology: Add node ID parser
by Patrick Rudolph (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Chen, Gang C, Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81515?usp=email ) Change subject: cpu/x86/topology: Add node ID parser ...................................................................... Patch Set 5: (1 comment) File src/cpu/x86/topology.c: https://review.coreboot.org/c/coreboot/+/81515/comment/915ba381_56e37578 : PS5, Line 64: void set_cpu_node_id_leaf_1f_b(struct device *cpu) > maybe it would be helpful to add a parameter to indicate the level type to query, and return error w […] Why? get_cpu_package_bits returns the higest level type, no matter how many level's there are, and that's what set_cpu_node_id_leaf_1f_b is looking for. -- To view, visit https://review.coreboot.org/c/coreboot/+/81515?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia3ed1e5923aa18ca7619b32cde491fdb4da0fa0d Gerrit-Change-Number: 81515 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 11:16:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: tree: Get rid of some casts
by Elyes Haouas (Code Review) 27 Mar '24

27 Mar '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81538?usp=email ) Change subject: tree: Get rid of some casts ...................................................................... tree: Get rid of some casts Change-Id: Ic81702ddf18d32a479a9388a4d6fde0f72a405b7 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/drivers/intel/fsp1_1/vbt.c M src/soc/amd/common/block/graphics/graphics.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/vbt.c M src/soc/intel/common/vbt.h M src/soc/intel/elkhartlake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/skylake/chip.c M src/soc/intel/tigerlake/fsp_params.c 12 files changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/81538/1 diff --git a/src/drivers/intel/fsp1_1/vbt.c b/src/drivers/intel/fsp1_1/vbt.c index 37471e5..2043834 100644 --- a/src/drivers/intel/fsp1_1/vbt.c +++ b/src/drivers/intel/fsp1_1/vbt.c @@ -34,5 +34,5 @@ } else { printk(BIOS_DEBUG, "Not passing VBT to GOP\n"); } - params->GraphicsConfigPtr = (u32)vbt_data; + params->GraphicsConfigPtr = vbt_data; } diff --git a/src/soc/amd/common/block/graphics/graphics.c b/src/soc/amd/common/block/graphics/graphics.c index ea7308a..71490eaa 100644 --- a/src/soc/amd/common/block/graphics/graphics.c +++ b/src/soc/amd/common/block/graphics/graphics.c @@ -151,7 +151,7 @@ * vbt_get() function to not break the build with GOP driver enabled * (see fsps_return_value_handler() in fsp2_0/silicon_init.c */ -void *vbt_get(void) +uintptr_t vbt_get(void) { return NULL; } diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 33ebee3..462a065 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -638,7 +638,7 @@ const struct soc_intel_alderlake_config *config) { /* Load VBT before devicetree-specific config. */ - s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); + s_cfg->GraphicsConfigPtr = vbt_get(); /* Check if IGD is present and fill Graphics init param accordingly */ s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 15780d0..1c57193 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -643,7 +643,7 @@ struct device *dev; /* Load VBT before devicetree-specific config. */ - silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get(); + silconfig->GraphicsConfigPtr = vbt_get(); dev = pcidev_path_on_root(SA_DEVFN_ROOT); cfg = config_of(dev); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index c9ef548..bbae400 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -340,7 +340,7 @@ parse_devicetree(config, params); /* Load VBT before devicetree-specific config. */ - params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + params->GraphicsConfigPtr = vbt_get(); mainboard_silicon_init_params(supd); diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index c01db66..6ab1a45 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -7,7 +7,7 @@ #include "vbt.h" -void *vbt_get(void) +uintptr_t vbt_get(void) { if (!CONFIG(RUN_FSP_GOP)) return NULL; diff --git a/src/soc/intel/common/vbt.h b/src/soc/intel/common/vbt.h index 5cbb2c7..a80ec81 100644 --- a/src/soc/intel/common/vbt.h +++ b/src/soc/intel/common/vbt.h @@ -9,5 +9,5 @@ * Returns VBT pointer and mapping after checking prerequisites for Pre OS * Graphics initialization */ -void *vbt_get(void); +uintptr_t vbt_get(void); #endif diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 5e1bba7..b11295d 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -253,7 +253,7 @@ parse_devicetree(params); /* Load VBT before devicetree-specific config. */ - params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + params->GraphicsConfigPtr = vbt_get(); /* Check if IGD is present and fill Graphics init param accordingly */ params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 50fc136..a48085f 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -58,7 +58,7 @@ parse_devicetree(params); /* Load VBT before devicetree-specific config. */ - params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + params->GraphicsConfigPtr = vbt_get(); /* Check if IGD is present and fill Graphics init param accordingly */ params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index a02d4b9..233cdde 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -410,7 +410,7 @@ const struct soc_intel_meteorlake_config *config) { /* Load VBT before devicetree-specific config. */ - s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); + s_cfg->GraphicsConfigPtr = vbt_get(); /* Check if IGD is present and fill Graphics init param accordingly */ s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(PCI_DEVFN_IGD); diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index ea091ce..b92805d 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -223,7 +223,7 @@ FSP_S_CONFIG *params = &supd->FspsConfig; FSP_S_TEST_CONFIG *tconfig = &supd->FspsTestConfig; struct soc_intel_skylake_config *config; - uintptr_t vbt_data = (uintptr_t)vbt_get(); + uintptr_t vbt_data = vbt_get(); int i; config = config_of_soc(); @@ -240,7 +240,7 @@ printk(BIOS_DEBUG, "psys_pmax = %d\n", tconfig->PsysPmax); } - params->GraphicsConfigPtr = (u32)vbt_data; + params->GraphicsConfigPtr = vbt_data; for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { params->PortUsb20Enable[i] = diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index 3326935..b29a51b 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -312,7 +312,7 @@ parse_devicetree(params); /* Load VBT before devicetree-specific config. */ - params->GraphicsConfigPtr = (uintptr_t)vbt_get(); + params->GraphicsConfigPtr = vbt_get(); /* Check if IGD is present and fill Graphics init param accordingly */ params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); -- To view, visit https://review.coreboot.org/c/coreboot/+/81538?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic81702ddf18d32a479a9388a4d6fde0f72a405b7 Gerrit-Change-Number: 81538 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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