coreboot-gerrit March 2024

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
by Subrata Banik (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81212?usp=email ) Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache ...................................................................... Patch Set 7: (1 comment) File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/81212/comment/5d767aee_8bc8008d : PS3, Line 221: FSP_EXECUTE_FROM_CBFS_CACHE > @arthur, Let me know what think of the latest "implementation". assume you have OEM design with different types of SoCs (between celeron to i7) where you wish to enable this feature. For sure the celeron skus won't be able to meet the req and run into an issue. Having an assertion can avoid the device to run into the actual issue but I don't see an option about how one would mitigate the SPI size limitation and able to boot to OS with lower cache with this proposal? Intel should instead focus on the root cause: redesigning a minimal-footprint FSP. Note: Early boot operations are critical, and a leaner FSP would yield wider benefits for all OEMs and improve the overall user experience w/ compression in place, we have chances to run into two issues: 1. lower cache affinity 2. incresed boot time due to uncompress. -- To view, visit https://review.coreboot.org/c/coreboot/+/81212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Gerrit-Change-Number: 81212 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 16:56:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: [WIP]arch/x86/car.ld: Drop the mrc_var section
by Jérémy Compostella (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Arthur Heymans. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81449?usp=email ) Change subject: [WIP]arch/x86/car.ld: Drop the mrc_var section ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: I found one occurence where it might be indirectly used. ``` #+caption: coreboot::src/northbridge/intel/sandybridge/raminit_mrc.c #+begin_src c -n 234 #define DCACHE_RAM_MRC_VAR_BASE (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE \ + CONFIG_DCACHE_RAM_MRC_VAR_SIZE - 0x4000) #+end_src ``` ``` #+caption: coreboot::src/northbridge/intel/sandybridge/raminit_mrc.c #+begin_src c -n 416 /* Sanity check mrc_var location by verifying a known field */ mrc_var = (void *)DCACHE_RAM_MRC_VAR_BASE; if (mrc_var->tx_byte == pei_data.tx_byte_ptr) { printk(BIOS_DEBUG, "MRC_VAR pool occupied [%08x,%08x]\n", mrc_var->pool_base, mrc_var->pool_base + mrc_var->pool_used); #+end_src ``` But I am still a bit puzzled by the way the math is done in this file I am not familiar with and curious why they don't access the region through its symbol -- To view, visit https://review.coreboot.org/c/coreboot/+/81449?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3168ef332edde78e5cf726286ded3fd724550ba4 Gerrit-Change-Number: 81449 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 27 Mar 2024 16:48:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
by Subrata Banik (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81212?usp=email ) Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache ...................................................................... Patch Set 7: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81212/comment/2e119c3b_3677642f : PS6, Line 42: 2 MB > The goal is not to offer a one configuration fit all solution. Each project/board is free to use this feature as it fits the project. Also, SoC variants of a generation have a minimal cache size which we could rely on if it came to a point we wanted it to be the default of a soc configuration. > > But I don't believe it is going to make it to the default of a SoC configuration soon. I see it more like an option for a board where SPINOR constraints would be tight and without going through the burden of having to define a fixed `FSP_M_ADDR` and account for it. OEMs/ODMs often face challenges when testing devices across a wide range of configurations (from Celeron to i7) using a unified AP FW image. Hidden dependencies in the AP FW, such as minimum cache size requirements, can be easily overlooked, causing issues on low-end devices. We need a way for OEMs/ODMs to statically assess whether their SoC designs meet the requirements for specific AP FW features, which i don't believe is the process. -- To view, visit https://review.coreboot.org/c/coreboot/+/81212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Gerrit-Change-Number: 81212 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 16:47:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: Support for creating hybrid vboot images
by Vladimir Serbinenko (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Julius Werner, Nick Vaccaro, Yu-Ping Wu. Vladimir Serbinenko has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81508?usp=email ) Change subject: Support for creating hybrid vboot images ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > > 1) RW needs to stay the same as changing it would break ChromeOS mechanism […] Sorry, I missed a word: "with chromeos update mechanism". I used a custom depthcharge and it worked fine until update time came for ChromeOS. As part of update ChromeOS does firmware update even if the firmware didn't change. Update suceeds in either of 2 cases: 1) RO is writable. Then it reflashes both RO and RW 2) RO is locked but it's compatible with new RW. Compatible means same layout and same GBB keys. Then, bigger problem is that flash map is preloaded 2 times: 1) Inside the code that ends up referencing partition by fixed offsets instead of reading flashmap 2) In CAR. And the size of preloaded cache is exact: it means it has as many slots as there are partitions and loading any extras will cause panic. It can't be extended because next allocation in CAR follows. These 2 together preclude adding any partitions which makes it a necessity to find another place for SMMSTORE As for bootblock: it's a good possibility but isn't the code I modify part of bootblock? -- To view, visit https://review.coreboot.org/c/coreboot/+/81508?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b26c332f5bf6befd62b5930b19d1b20e76261e7 Gerrit-Change-Number: 81508 Gerrit-PatchSet: 5 Gerrit-Owner: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 16:44:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Comment-In-Reply-To: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
by Jérémy Compostella (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81212?usp=email ) Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache ...................................................................... Patch Set 7: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81212/comment/b14dbce7_d8f1735c : PS6, Line 42: 2 MB > i have worked on an Intel project where the CAR size is 1.25MB even. […] The goal is not to offer a one configuration fit all solution. Each project/board is free to use this feature as it fits the project. Also, SoC variants of a generation have a minimal cache size which we could rely on if it came to a point we wanted it to be the default of a soc configuration. But I don't believe it is going to make it to the default of a SoC configuration soon. I see it more like an option for a board where SPINOR constraints would be tight and without going through the burden of having to define a fixed `FSP_M_ADDR` and account for it. Patchset: PS3: > > I'm a bit confused how this works. FSP-M needs to be relocated at runtime for this to work. […] Done File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/81212/comment/851c3a81_60ff8e5f : PS3, Line 221: FSP_EXECUTE_FROM_CBFS_CACHE > I went with a warning instead of an error to align with other control performed during the compilati […] @arthur, Let me know what think of the latest "implementation". File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/81212/comment/3ebd6fc2_4e9e6923 : PS6, Line 221: config FSP_M_EXECUTE_FROM_CBFS_CACHE > I realized that PRERAM_CBFS_CACHE is a must item in car now, if there is an Kconfig like USE_PRERAM_ […] Pre-memory CBFS cache is always on. Only the size can be adjusted with zero meaning no CBFS cache. The Makefile warning if the size is not enough to accommodate the decompressed FSP-M take care of making sure the dependency is satisfied. https://review.coreboot.org/c/coreboot/+/81212/comment/d2bbe09a_ecd5a03f : PS6, Line 225: Select this value when FSP-M executes from CBFS cache. > i guess the assumptions are not drafted properly about how much temp memory is required to support t […] Done https://review.coreboot.org/c/coreboot/+/81212/comment/bd0a33b4_bdde2528 : PS6, Line 225: Select this value when FSP-M executes from CBFS cache. > > Maybe we can comment here, if FSP-M is compressed, it will be decompressed into PRERAM_CBFS_CACHE, […] I also they are technically separated notions even but I added a note about as the whole idea of running from CBFS cache is to have a compressed FSP-M in SPINOR. -- To view, visit https://review.coreboot.org/c/coreboot/+/81212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Gerrit-Change-Number: 81212 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 16:31:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
by Jérémy Compostella (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Tarun. Hello Andrey Petrov, Arthur Heymans, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81212?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Code-Review+1 by Shuo Liu, Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache ...................................................................... drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache If SPINOR space is limited and Cache-As-RAM (CAR) is large enough, FSP can be stored compressed, loaded in CBFS cache and executed from there. It allows to reduce the FSP-M SPINOR footprint with a limited boot time penalty. `FSP_M_EXECUTE_FROM_CBFS_CACHE' Kconfig can be set to turn on this feature. We performed some measurements on a Meteor Lake Rex board with a 2 MB Cache-As-RAM (`DCACHE_RAM_SIZE' at 0x200000 and `DCACHE_RAM_BASE' 0xea000000) and a few adjustments in the FSP to enable CAR to RAM PEIM (Pre-EFI Initialization Module) drivers migration. 1. Time impact | Compression algorithm | LZ4 | LZMA | |--------------------------+----------+----------| | Decompress duration | 1.9 ms | 75.6 ms | | Overall boot time impact | +15.9 ms | +77.4 ms | The overall boot time impact increase is explained by FSP-M loading being a bit faster (-18 ms) undermined by a longer Cache-As-RAM setup (32 ms). 2. SPINOR impact | CBFS file / Compression | LZ4 | LZMA | |----------------------------+----------------+-----------------| | romstage size | +4 KB (+3%) | +10 KB (+8%) | | fspm.bin size | -313 KB (-37%) | -456 KB (-54%) | |----------------------------+----------------+-----------------| | Total Per slot | -309 KB | -446 KB | | Total for SPINOR (3 slots) | -926 KB | -1339 KB | BUG=b:329237541 TEST=Verified on rex with Cache-AS-RAM size of 2 MB Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/Makefile.mk M src/drivers/intel/fsp2_0/memory_init.c M src/soc/intel/meteorlake/Kconfig 4 files changed, 30 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81212/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/81212?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2 Gerrit-Change-Number: 81212 Gerrit-PatchSet: 7 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: util/crossgcc/buildgcc: Use Intel mirror for ACPICA
by Felix Singer (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Martin L Roth. Hello Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80721?usp=email to look at the new patch set (#6). Change subject: util/crossgcc/buildgcc: Use Intel mirror for ACPICA ...................................................................... util/crossgcc/buildgcc: Use Intel mirror for ACPICA The binary hashes from GitHub releases are not stable. Use the Intel mirror. Change-Id: If3738b0cdab07c37ac1459a53e399e5de54435d5 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix-20230628_iasl.patch D util/crossgcc/sum/R06_28_23.tar.gz.cksum A util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum 4 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/80721/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/80721?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If3738b0cdab07c37ac1459a53e399e5de54435d5 Gerrit-Change-Number: 80721 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: util/crossgcc/buildgcc: Use Intel mirror for ACPICA
by Felix Singer (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Martin L Roth. Hello Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80721?usp=email to look at the new patch set (#5). Change subject: util/crossgcc/buildgcc: Use Intel mirror for ACPICA ...................................................................... util/crossgcc/buildgcc: Use Intel mirror for ACPICA Binary hashes downloaded from GitHub are not stable. Use the Intel mirror. Change-Id: If3738b0cdab07c37ac1459a53e399e5de54435d5 Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix-20230628_iasl.patch D util/crossgcc/sum/R06_28_23.tar.gz.cksum A util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum 4 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/80721/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/80721?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If3738b0cdab07c37ac1459a53e399e5de54435d5 Gerrit-Change-Number: 80721 Gerrit-PatchSet: 5 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: util/crossgcc/buildgcc: Use Intel mirror for ACPICA
by Felix Singer (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Martin L Roth. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80721?usp=email ) Change subject: util/crossgcc/buildgcc: Use Intel mirror for ACPICA ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/80721?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If3738b0cdab07c37ac1459a53e399e5de54435d5 Gerrit-Change-Number: 80721 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Wed, 27 Mar 2024 16:09:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: vendorcode/eltan: Fix building without separate romstage
by Arthur Heymans (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Erik van den Bogaert, Frans Hendriks. Hello Erik van den Bogaert, Frans Hendriks, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78933?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: vendorcode/eltan: Fix building without separate romstage ...................................................................... vendorcode/eltan: Fix building without separate romstage - Make sure build.h is there by adding it as a dependency for all stages - Remove obsolete CPU_MICROCODE_CBFS_LOC symbol from config Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ibb077f5a2ebcdbaff537d82564f5245e45009fc9 --- M configs/config.facebook_fbg1701.mboot_vboot M src/vendorcode/eltan/security/mboot/Makefile.mk 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/78933/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/78933?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibb077f5a2ebcdbaff537d82564f5245e45009fc9 Gerrit-Change-Number: 78933 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-MessageType: newpatchset

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