Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81540?usp=email )
Change subject: Update opensbi submodule to upstream master branch
......................................................................
Update opensbi submodule to upstream master branch
Updating from commit id 5019fd124b4c (2022-09-01):
include: sbi: Reduce includes in sbi_pmu.h
to commit id 5186da687deb (2024-03-20):
platform: generic: allwinner: sun20i-d1: Remove duplicated CSR definitions
This brings in 465 new commits.
Change-Id: I9af77fe464464a23e3643bbfca0bc6f0129bcb69
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
---
M 3rdparty/opensbi
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/81540/1
diff --git a/3rdparty/opensbi b/3rdparty/opensbi
index 5019fd1..5186da6 160000
--- a/3rdparty/opensbi
+++ b/3rdparty/opensbi
@@ -1 +1 @@
-Subproject commit 5019fd124b4c46e1581129c5154fc2cdd3b777ed
+Subproject commit 5186da687debaab5c4a81ec351e56d145d88c79c
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Change subject: mb/google/brya: Fix mux_conn index used by ec/google/chromeec
......................................................................
Patch Set 4:
(1 comment)
Patchset:
PS4:
> Thank you for providing background info. […]
@hadrosaur@google.com to test on Felwinter.
Emilie, please resolve this comment once you have tested on Felwinter.
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Change subject: include/device/pci_ids.h: Add DIDs for MTL Touch controller
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
nit: the commit message only mentions 0x7e49 and 0x7eb4, but you're adding 4 ids.
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Change subject: drivers/intel/pmc_mux/conn: Copy ACPI _PLD property from USB port to mux
......................................................................
Patch Set 8: Code-Review+1
(1 comment)
Patchset:
PS8:
Tested on mithrax with related coreboot fixes. LGTM!
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Change subject: ec/google/chromeec: Remove blank lines before '}' and after '{'
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Since this file is copied as-is from the [EC repo](https://chromium.googlesource.com/chromiumos/platform/ec/+/refs/heads… I don't see any benefit in removing empty line (or any other style change) here.
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Hello Andrey Petrov, Arthur Heymans, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Paul Menzel, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
......................................................................
drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
If SPINOR space is limited and Cache-As-RAM (CAR) is large enough, FSP
can be stored compressed, loaded in CBFS cache and executed from
there. It allows to reduce the FSP-M SPINOR footprint with a limited
boot time penalty. `FSP_M_EXECUTE_FROM_CBFS_CACHE' Kconfig can be set
to turn on this feature.
We performed some measurements on a Meteor Lake Rex board with a 2 MB
Cache-As-RAM (`DCACHE_RAM_SIZE' at 0x200000 and `DCACHE_RAM_BASE'
0xea000000) and a few adjustments in the FSP to enable CAR to RAM
PEIM (Pre-EFI Initialization Module) drivers migration.
1. Time impact
| Compression algorithm | LZ4 | LZMA |
|--------------------------+----------+----------|
| Decompress duration | 1.9 ms | 75.6 ms |
| Overall boot time impact | +15.9 ms | +77.4 ms |
The overall boot time impact increase is explained by FSP-M loading
being a bit faster (-18 ms) undermined by a longer Cache-As-RAM
setup (32 ms).
2. SPINOR impact
| CBFS file / Compression | LZ4 | LZMA |
|----------------------------+----------------+-----------------|
| romstage size | +4 KB (+3%) | +10 KB (+8%) |
| fspm.bin size | -313 KB (-37%) | -456 KB (-54%) |
|----------------------------+----------------+-----------------|
| Total Per slot | -309 KB | -446 KB |
| Total for SPINOR (3 slots) | -926 KB | -1339 KB |
BUG=b:329237541
TEST=Verified on rex with Cache-AS-RAM size of 2 MB
Change-Id: I8d42d765eb0ecf2e7a8fc6d8d15eb2df8975f6f2
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/intel/fsp2_0/Kconfig
M src/drivers/intel/fsp2_0/Makefile.mk
M src/drivers/intel/fsp2_0/memory_init.c
M src/soc/intel/meteorlake/Kconfig
4 files changed, 37 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/81212/8
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Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
......................................................................
Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81212/comment/0c46aecc_b8ffda68 :
PS6, Line 42: 2 MB
> > The goal is not to offer a one configuration fit all solution. […]
This commit goal is to offer an alternative to `FSP_M_ADDR` solution allowing the use FSP-M compression. The commit message also provides some information on the impact when used on particular board design for illustration. With this scope in mind, what would you suggest to add to this commit to help with your point ?
File src/drivers/intel/fsp2_0/Kconfig:
https://review.coreboot.org/c/coreboot/+/81212/comment/43ae905f_6f1aff37 :
PS3, Line 221: FSP_EXECUTE_FROM_CBFS_CACHE
> Having an assertion can avoid the device to run into the actual issue but I don't see an option about how one would mitigate the SPI size limitation and able to boot to OS with lower cache with this proposal?
I had it as an assert at some points but went back to a WARNING to align with what is done for other non-booting images within the same Makefile.
This commit has no vocation to provide any mitigation if FSP-M cannot fit in CAR. This feature should only be use if it can fit as stated in the Kconfig.
I totally agree that working on reducing the footprint is the way to go to minimize the occupation of the SPINOR in general as it yields better results. The point of this commit is not to force any decision for any particular design but to offer an extra way to reduce the SPINOR occupation by leveraging existing code in a more flexible way.
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