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Change subject: mb/google/nissa/var/glassway: Set VccIn Aux Imon IccMax to 25 A
......................................................................
Patch Set 8:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81445/comment/a66003cd_a6254fec :
PS6, Line 9: MBVR
> For FIVR design, the VccInAuxImonIccImax should be 27A, for MBVR design VccInAuxImonIccImax should b […]
Done
https://review.coreboot.org/c/coreboot/+/81445/comment/52419006_0dd06286 :
PS6, Line 9: Iccmax of VccIn_Aux is 25A with MBVR design.
> Intel FSP ADL default 27A
Done
File src/mainboard/google/brya/variants/glassway/ramstage.c:
https://review.coreboot.org/c/coreboot/+/81445/comment/92a61314_b75636ba :
PS6, Line 7: //
> One space?
Done
https://review.coreboot.org/c/coreboot/+/81445/comment/da6c23a7_349c2d6a :
PS6, Line 7: 25*4 For ADL-N
> 25 * 4 for ADL-N
Done
https://review.coreboot.org/c/coreboot/+/81445/comment/34f98e2c_ca076927 :
PS6, Line 10:
> build bot error: adding a line without newline at end of file
Done
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Change subject: mb/google/nissa/var/glassway: Set VccIn Aux Imon IccMax to 25 A
......................................................................
Patch Set 8: Code-Review+1
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81445/comment/1aad9879_652987cb :
PS6, Line 7: Update the VccIn Aux Imon IccMax
> Set VccIn Aux Imon IccMax to 25 A
Done
https://review.coreboot.org/c/coreboot/+/81445/comment/1cb14407_f63c2fc4 :
PS6, Line 9: Iccmax of VccIn_Aux is 25A with MBVR design.
> What is the current default?
Intel FSP ADL default 27A
https://review.coreboot.org/c/coreboot/+/81445/comment/dd669f57_778f7c96 :
PS6, Line 9: MBVR
> What does that mean?
For FIVR design, the VccInAuxImonIccImax should be 27A, for MBVR design VccInAuxImonIccImax should be 25A.
File src/mainboard/google/brya/variants/glassway/ramstage.c:
https://review.coreboot.org/c/coreboot/+/81445/comment/42bb8cd2_4b049af1 :
PS6, Line 10:
> Remove blank line, if possible (or Gerrit bug).
build bot error: adding a line without newline at end of file
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Change subject: mb/google/nissa/var/glassway: Set VccIn Aux Imon IccMax to 25 A
......................................................................
mb/google/nissa/var/glassway: Set VccIn Aux Imon IccMax to 25 A
Iccmax of VccIn_Aux is 25A with MBVR design.
BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST=Local build successfully and boot to OOBE normally.
Change-Id: I105dc9df53c624fd7fc697408a1097e023a3cd68
Signed-off-by: Frank Chu <frank_chu(a)pegatron.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/glassway/Makefile.mk
A src/mainboard/google/brya/variants/glassway/ramstage.c
2 files changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/81445/7
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Change subject: mb/google/nissa: Create sundance variant
......................................................................
Patch Set 11:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81347/comment/38136a44_bc05c998 :
PS7, Line 12: in
: inside
> What is “inside”? Is that Insyde?
No, the inside is means chroot
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Change subject: Support for creating hybrid vboot images
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> Sorry, I missed a word: "with chromeos update mechanism". […]
Okay, so you want to dual-boot, and you want ChromeOS to keep updating at the same time? That is indeed tricky. If you want to receive ChromeOS firmware updates and actually apply them then you will have to base the custom coreboot you're building on the appropriate ChromeOS firmware branch for your board, I think that's the only realistic way to make sure they're compatible. But do you really need firmware updates? We don't really send them out that often (especially if the board is older), and most of the time they are minor fixes or security things that wouldn't really make much of a difference if you're already running in such a makeshift unsupported configuration.
Would it be enough if we just allowed you (in developer mode) to configure the ChromeOS updater such that it will only apply kernel and rootfs updates, but not firmware updates? I can't promise anything but I could ask if that's a feature we could add.
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I'd like you to reexamine a change. Please visit
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Change subject: mb/google/nissa: Create sundance variant
......................................................................
mb/google/nissa: Create sundance variant
Create the sundance variant of nissa reference board by copying the
template files to a new directory named for the variant.
BUG=b:328505938
Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea
Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/sundance/include/variant/ec.h
A src/mainboard/google/brya/variants/sundance/include/variant/gpio.h
A src/mainboard/google/brya/variants/sundance/memory/Makefile.mk
A src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/sundance/overridetree.cb
8 files changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/81347/11
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Change subject: mb/google/nissa: Create sundance variant
......................................................................
mb/google/nissa: Create sundance variant
Create the sundance variant of nissa reference board by copying the
template files to a new directory named for the variant.
Due to new_variant.py limitation that repo can no longer be used in
inside, created this CL manually following google suggestion.
BUG=b:328505938
Change-Id: Ia8ba318f18d2cac69898687311631778e61bf2ea
Signed-off-by: Leo Chou <leo.chou(a)lcfc.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/Kconfig.name
A src/mainboard/google/brya/variants/sundance/include/variant/ec.h
A src/mainboard/google/brya/variants/sundance/include/variant/gpio.h
A src/mainboard/google/brya/variants/sundance/memory/Makefile.mk
A src/mainboard/google/brya/variants/sundance/memory/dram_id.generated.txt
A src/mainboard/google/brya/variants/sundance/memory/mem_parts_used.txt
A src/mainboard/google/brya/variants/sundance/overridetree.cb
8 files changed, 47 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/81347/10
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Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
......................................................................
mb/google/{brya,hades}: use soc index for variant_update_power_limits()
The power_limits_config variable for ADL/RPL is array data, but we got
soc_power_limits_config variable without its index. So correct the
code to get the proper pointer of the data for current CPU SKU.
I tried to override the PL4 value to 80W from 114W with following
table in ramstage.c as a test for bug b/328729536.
```
const struct cpu_power_limits limits[] = {
{PCI_DID_INTEL_RPL_P_ID3, 15, 6000, 15000, 55000, 55000, 80000},
}
```
And then verified the msr_pl4 value on ChromeOS using Intel PTAT tool.
- Before this CL: msr_pl4 was not chaged, it's always 114
- After this CL: msr_pl4 was changed to 80
BUG=None
BRANCH=None
TEST=Built and tested the function could adjust PL4 on xol in local.
Change-Id: I9f1ba25c2d673fda48babf773208c2f2d2386c53
Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com>
---
M src/mainboard/google/brya/variants/baseboard/brya/ramstage.c
M src/mainboard/google/brya/variants/baseboard/hades/ramstage.c
2 files changed, 63 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/81436/7
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