coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: arch/riscv: Add basic illegal instruction handling
by ron minnich (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Paul Menzel, Philipp Hug. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81306?usp=email ) Change subject: arch/riscv: Add basic illegal instruction handling ...................................................................... Patch Set 11: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/81306/comment/4f43bae4_145fbfc2 : PS11, Line 7: arch/riscv: Basic illegal instruction handling > Just a nit: It’d be great if you made this a statement by adding a verb in imperative mood. […] Done https://review.coreboot.org/c/coreboot/+/81306/comment/d57f3e1f_38e0857d : PS11, Line 23: > Other nit: The blank line can be removed. Done File src/arch/riscv/trap_handler.c: https://review.coreboot.org/c/coreboot/+/81306/comment/fb77d58a_63083eee : PS11, Line 116: testing_linuxcheck > Mention this in the commit message too? oops, that should not have been here, thanks. It's moved now. https://review.coreboot.org/c/coreboot/+/81306/comment/1204eefa_a7b5c2e3 : PS11, Line 128: provided > provide Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81306?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 Gerrit-Change-Number: 81306 Gerrit-PatchSet: 11 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 27 Mar 2024 15:41:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: arch/riscv: linuxcheck framework which runs from ramstage
by ron minnich (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Philipp Hug. Hello Arthur Heymans, Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81367?usp=email to look at the new patch set (#10). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/riscv: linuxcheck framework which runs from ramstage ...................................................................... arch/riscv: linuxcheck framework which runs from ramstage Errors in Linux booting are notoriously hard to debug. This change adds a linuxcheck framework that allows testing of things Linux (and other kernels) needs, without having to debug Linux. If LINUXCHECK is set during menuconfig, the linuxcheck function will be called, in S mode, from the ramstage. That function then runs code, in S mode, that tests coreboot M mode code such as SBI. This is extremely handy: because linuxcheck is built into the ramstage, it allows calling any ramstage function, e.g. printk, if required; at the same time, the function is running in S mode, so it is very easy to test SBI calls, instruction emulation, and so on. Note that, if CONFIG_LINUXCHECK is set, the PMPs should enable RWX permissions (instead of R permissions) on the ramstage. For now, until we get the rest of the debugging done, we unconditionally set the permissions. This is a very powerful approach that could also form the core of an SBI fuzzing suite; unlike the currently proposed one, which is based on the KVM fuzzer, this code would not require a Linux kernel to test. It is very light weight. This is also better than the older linuxcheck payload, since it does not need libpayload or seperate compilation. It reduces the testing of SBI and other trap code to its simplest form, and allows to focus on testing SBI, not fighting build systems and large complex kernels. Change-Id: I7d19147b9df57c63ec7301da243fd5541e9952a7 Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/arch/riscv/Kconfig M src/arch/riscv/Makefile.mk M src/arch/riscv/include/arch/cpu.h A src/arch/riscv/linuxcheck.c M src/arch/riscv/payload.c M src/arch/riscv/trap_handler.c 6 files changed, 129 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/81367/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/81367?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7d19147b9df57c63ec7301da243fd5541e9952a7 Gerrit-Change-Number: 81367 Gerrit-PatchSet: 10 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: arch/riscv: Add basic illegal instruction handling
by ron minnich (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Philipp Hug, ron minnich. Hello Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81306?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: arch/riscv: Add basic illegal instruction handling ...................................................................... arch/riscv: Add basic illegal instruction handling Add a simple illegal instruction handler, designed for lowest overhead as opposed to generality. coreboot SBI is designed to minimize SBI functionality. This minimization is reflected in the lack of generality in the code. On modern RISC-V systems, the trap will not even occur. At some point RISC-V community figured out that trapping on reading time was not always the best idea :-) So, in general, on future systems, reads will not trap. Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 --- M src/arch/riscv/trap_handler.c M src/arch/riscv/virtual_memory.c 2 files changed, 60 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/81306/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/81306?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078 Gerrit-Change-Number: 81306 Gerrit-PatchSet: 12 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: [WIP]arch/x86/car.ld: Drop the mrc_var section
by Arthur Heymans (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Jérémy Compostella. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81449?usp=email ) Change subject: [WIP]arch/x86/car.ld: Drop the mrc_var section ...................................................................... [WIP]arch/x86/car.ld: Drop the mrc_var section This section isn't used. Change-Id: I3168ef332edde78e5cf726286ded3fd724550ba4 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/arch/x86/car.ld 1 file changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/81449/1 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 8e1af15..218ce2f 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -114,10 +114,6 @@ . += CONFIG_FSP_M_RC_HEAP_SIZE; } -. = _car_region_end; -.car.mrc_var . (NOLOAD) : { - . += CONFIG_DCACHE_RAM_MRC_VAR_SIZE; -} .car.fspt_reserved . (NOLOAD) : { . += CONFIG_FSP_T_RESERVED_SIZE; } -- To view, visit https://review.coreboot.org/c/coreboot/+/81449?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3168ef332edde78e5cf726286ded3fd724550ba4 Gerrit-Change-Number: 81449 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/amd/noncar: Make sure preram CBMEM console is aligned
by Arthur Heymans (Code Review) 27 Mar '24

27 Mar '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81448?usp=email ) Change subject: soc/amd/noncar: Make sure preram CBMEM console is aligned ...................................................................... soc/amd/noncar: Make sure preram CBMEM console is aligned This fixed build issues when neither FSP, FSPM, nor x86 verstage is used, in which case the premem CBMEM console buffer would follow an alignment defined in memlayout_tranfer_buffer.inc. This is unaligned in the case of AMD Genoa. Change-Id: I677c09dbdeaf8f6803f55597514c6fe6ec25ab92 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/81448/1 diff --git a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld index 078b084..0a354c0 100644 --- a/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld @@ -112,6 +112,7 @@ VERSTAGE(CONFIG_VERSTAGE_ADDR, CONFIG_VERSTAGE_SIZE) #endif + . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE); PRERAM_CBMEM_CONSOLE(., CONFIG_PRERAM_CBMEM_CONSOLE_SIZE) #if CONFIG_CBFS_CACHE_SIZE > 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/81448?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I677c09dbdeaf8f6803f55597514c6fe6ec25ab92 Gerrit-Change-Number: 81448 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: Makefile.mk: Also add -libs to bootblock when !SEPARATE_ROMSTAGE
by Martin L Roth (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Arthur Heymans, Felix Singer. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79575?usp=email ) Change subject: Makefile.mk: Also add -libs to bootblock when !SEPARATE_ROMSTAGE ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79575?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18bf67cae7af90a92a030e552af6dc6b134a8357 Gerrit-Change-Number: 79575 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 27 Mar 2024 15:03:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: vc/wuffs: Fix compiling for 64bit and clang
by Martin L Roth (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Arthur Heymans, Patrick Georgi. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81382?usp=email ) Change subject: vc/wuffs: Fix compiling for 64bit and clang ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: This is why I think it might be better to have this as a submodule. We really want this fix to go to https://github.com/google/wuffs so that we don't need to merge when we update to the next version of wuffs. -- To view, visit https://review.coreboot.org/c/coreboot/+/81382?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23ef29010d60bd543e48af032795ec9fc2ff9ecb Gerrit-Change-Number: 81382 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Wed, 27 Mar 2024 15:01:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[M] Change in coreboot[main]: cpu/x86/Kconfig: Mark 64bit support as stable
by Martin L Roth (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Felix Held, Fred Reitberger, Jason Glenesk, Johnny Lin, Jonathan Zhang, Julius Werner, Jérémy Compostella, Lean Sheng Tan, Matt DeVillier, Patrick Rudolph, Shuo Liu, Tim Chu. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80338?usp=email ) Change subject: cpu/x86/Kconfig: Mark 64bit support as stable ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80338?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcf0a1a5097a2d7c064bb709ec0b09ebee13a47d Gerrit-Change-Number: 80338 Gerrit-PatchSet: 18 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 27 Mar 2024 14:58:04 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/amd/non_car/memlayout_x86.ld: Top align the code
by Martin L Roth (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Martin Roth, Matt DeVillier. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81433?usp=email ) Change subject: soc/amd/non_car/memlayout_x86.ld: Top align the code ...................................................................... Patch Set 2: Code-Review+2 (1 comment) File src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld: https://review.coreboot.org/c/coreboot/+/81433/comment/07af4ab7_1f644791 : PS1, Line 128: 64K > > I thought the whole point of this was that we didn't know the length, and it could be up to 128K w […] Perfect. Thanks. -- To view, visit https://review.coreboot.org/c/coreboot/+/81433?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18bdf262f9c358aa01795b11efcb863686edc79c Gerrit-Change-Number: 81433 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 27 Mar 2024 14:56:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: vendorcode/amd/opensil: Add CPP args to all stages
by Martin L Roth (Code Review) 27 Mar '24

27 Mar '24

Attention is currently required from: Arthur Heymans, Felix Held. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79576?usp=email ) Change subject: vendorcode/amd/opensil: Add CPP args to all stages ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79576?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic7edfdac43c2d71ee3dcbd9d8f59c9799595e7f8 Gerrit-Change-Number: 79576 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 27 Mar 2024 14:55:11 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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