coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

1 participants
3667 discussions

[S] Change in coreboot[main]: nb/intel/haswell: make IOMMU a runtime option
by Leah Rowe (Code Review) 03 Mar '24

03 Mar '24

Leah Rowe has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81016?usp=email ) Change subject: nb/intel/haswell: make IOMMU a runtime option ...................................................................... nb/intel/haswell: make IOMMU a runtime option When I tested graphics cards on a coreboot port for Dell OptiPlex 9020 SFF, I could not use a graphics card unless I set iommu=off on the Linux cmdline. The current coreboot behaviour is to check whether the CPU has vt-d support and, if it does, initialise the IOMMU. This patch maintains the current behaviour by default, but allows the user to turn *off* the IOMMU, even if vt-d is supported by the host CPU. If iommu=Disable is specified, the check will not be performed, and the IOMMU will be left disabled. This option has been added to all current Haswell boards, though it is recommended to leave the IOMMU turned on in most setups. Change-Id: Ib743bd00a872c7d73cf9711d618811c7778f2ffb Signed-off-by: Leah Rowe <info(a)minifree.org> --- M src/mainboard/asrock/b85m_pro4/cmos.default M src/mainboard/asrock/b85m_pro4/cmos.layout M src/mainboard/asrock/h81m-hds/cmos.default M src/mainboard/asrock/h81m-hds/cmos.layout M src/mainboard/google/beltino/cmos.layout M src/mainboard/google/slippy/cmos.layout M src/mainboard/intel/baskingridge/cmos.layout M src/mainboard/lenovo/haswell/cmos.default M src/mainboard/lenovo/haswell/cmos.layout M src/mainboard/lenovo/m900_tiny/cmos.default M src/mainboard/lenovo/m900_tiny/cmos.layout M src/mainboard/supermicro/x10slm-f/cmos.default M src/mainboard/supermicro/x10slm-f/cmos.layout M src/northbridge/intel/haswell/early_init.c 14 files changed, 47 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/81016/1 diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default index 01bf20a..dfc8b80 100644 --- a/src/mainboard/asrock/b85m_pro4/cmos.default +++ b/src/mainboard/asrock/b85m_pro4/cmos.default @@ -4,3 +4,4 @@ debug_level=Debug nmi=Enable power_on_after_fail=Disable +iommu=Enable diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout index efdc333..c9883ea 100644 --- a/src/mainboard/asrock/b85m_pro4/cmos.layout +++ b/src/mainboard/asrock/b85m_pro4/cmos.layout @@ -11,6 +11,7 @@ 395 4 e 4 debug_level 408 1 e 1 nmi 409 2 e 5 power_on_after_fail + 412 1 e 6 iommu 984 16 h 0 check_sum # ----------------------------------------------------------------- @@ -38,6 +39,8 @@ 5 0 Disable 5 1 Enable 5 2 Keep + 6 0 Disable + 6 1 Enable # ----------------------------------------------------------------- # ----------------------------------------------------------------- diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default index 01bf20a..dfc8b80 100644 --- a/src/mainboard/asrock/h81m-hds/cmos.default +++ b/src/mainboard/asrock/h81m-hds/cmos.default @@ -4,3 +4,4 @@ debug_level=Debug nmi=Enable power_on_after_fail=Disable +iommu=Enable diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout index c9ba76c..95ee3d3 100644 --- a/src/mainboard/asrock/h81m-hds/cmos.layout +++ b/src/mainboard/asrock/h81m-hds/cmos.layout @@ -21,6 +21,9 @@ 408 1 e 1 nmi 409 2 e 5 power_on_after_fail +# enable or disable iommu +412 1 e 6 iommu + # coreboot config options: check sums 984 16 h 0 check_sum @@ -52,6 +55,9 @@ 5 1 Enable 5 2 Keep +6 0 Disable +6 1 Enable + # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout index 78d44c1..c143979 100644 --- a/src/mainboard/google/beltino/cmos.layout +++ b/src/mainboard/google/beltino/cmos.layout @@ -19,6 +19,9 @@ 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +# enable or disable iommu +412 1 e 8 iommu + # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv @@ -47,6 +50,8 @@ 7 0 Disable 7 1 Enable 7 2 Keep +8 0 Disable +8 1 Enable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout index 78d44c1..c143979 100644 --- a/src/mainboard/google/slippy/cmos.layout +++ b/src/mainboard/google/slippy/cmos.layout @@ -19,6 +19,9 @@ 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +# enable or disable iommu +412 1 e 8 iommu + # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv @@ -47,6 +50,8 @@ 7 0 Disable 7 1 Enable 7 2 Keep +8 0 Disable +8 1 Enable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout index 78d44c1..f2c602f 100644 --- a/src/mainboard/intel/baskingridge/cmos.layout +++ b/src/mainboard/intel/baskingridge/cmos.layout @@ -19,6 +19,8 @@ 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +412 1 e 8 iommu + # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv @@ -47,6 +49,8 @@ 7 0 Disable 7 1 Enable 7 2 Keep +8 0 Disable +8 1 Enable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default index 08db97c..cc6b363 100644 --- a/src/mainboard/lenovo/haswell/cmos.default +++ b/src/mainboard/lenovo/haswell/cmos.default @@ -14,3 +14,4 @@ backlight=Keyboard enable_dual_graphics=Disable usb_always_on=Disable +iommu=Enable diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout index 27915d3..59df76b 100644 --- a/src/mainboard/lenovo/haswell/cmos.layout +++ b/src/mainboard/lenovo/haswell/cmos.layout @@ -23,6 +23,7 @@ # coreboot config options: EC 411 1 e 8 first_battery +413 1 e 14 iommu 415 1 e 1 wlan 416 1 e 1 trackpoint 417 1 e 1 fn_ctrl_swap @@ -72,6 +73,8 @@ 13 0 Disable 13 1 AC and battery 13 2 AC only +14 0 Disable +14 1 Enable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/m900_tiny/cmos.default b/src/mainboard/lenovo/m900_tiny/cmos.default index 84236aa..d78cdc9 100644 --- a/src/mainboard/lenovo/m900_tiny/cmos.default +++ b/src/mainboard/lenovo/m900_tiny/cmos.default @@ -4,3 +4,4 @@ debug_level=Debug power_on_after_fail=Disable nmi=Enable +iommu=Enable diff --git a/src/mainboard/lenovo/m900_tiny/cmos.layout b/src/mainboard/lenovo/m900_tiny/cmos.layout index 322fa7d..0b61f4e 100644 --- a/src/mainboard/lenovo/m900_tiny/cmos.layout +++ b/src/mainboard/lenovo/m900_tiny/cmos.layout @@ -24,6 +24,9 @@ 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +# turn iommu on or off +412 1 e 8 iommu + # coreboot config options: ME 416 1 e 2 me_state 417 3 h 0 me_state_counter @@ -54,6 +57,8 @@ 7 0 Disable 7 1 Enable 7 2 Keep +8 0 Disable +8 1 Enable # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default index 7ce38fb..6049e79 100644 --- a/src/mainboard/supermicro/x10slm-f/cmos.default +++ b/src/mainboard/supermicro/x10slm-f/cmos.default @@ -5,3 +5,4 @@ nmi=Enable power_on_after_fail=Keep hide_ast2400=Disable +iommu=Enable diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout index 38ba87a..24d39e9 100644 --- a/src/mainboard/supermicro/x10slm-f/cmos.layout +++ b/src/mainboard/supermicro/x10slm-f/cmos.layout @@ -21,6 +21,9 @@ 408 1 e 1 nmi 409 2 e 5 power_on_after_fail +# enable or disable iommu +412 1 e 6 iommu + # coreboot config options: mainboard 416 1 e 1 hide_ast2400 @@ -55,6 +58,9 @@ 5 1 Enable 5 2 Keep +6 0 Disable +6 1 Enable + # ----------------------------------------------------------------- checksums diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c index e47deb5..1a7e0b1 100644 --- a/src/northbridge/intel/haswell/early_init.c +++ b/src/northbridge/intel/haswell/early_init.c @@ -5,6 +5,7 @@ #include <device/mmio.h> #include <device/pci_def.h> #include <device/pci_ops.h> +#include <option.h> #include "haswell.h" @@ -157,6 +158,10 @@ static void haswell_setup_iommu(void) { const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A); + u8 enable_iommu = get_uint_option("iommu", 1); + + if (!enable_iommu) + return; if (capid0_a & VTD_DISABLE) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/81016?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib743bd00a872c7d73cf9711d618811c7778f2ffb Gerrit-Change-Number: 81016 Gerrit-PatchSet: 1 Gerrit-Owner: Leah Rowe <leahleahrowerowe(a)gmail.com> Gerrit-MessageType: newchange

1 0

[M] Change in coreboot[main]: mb/emulation/qemu-riscv: Change to -bios option
by Philipp Hug (Code Review) 03 Mar '24

03 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune. Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80746?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/emulation/qemu-riscv: Change to -bios option ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: as discussed, rebase this on top of 36486 to avoid fixed RAM size -- To view, visit https://review.coreboot.org/c/coreboot/+/80746?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I009d97fa3e13068b91c604e987e50a65e525407d Gerrit-Change-Number: 80746 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 03 Mar 2024 09:35:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: payload/external/edk2: Explicitly define the build arch
by Nicholas Sudsgaard (Code Review) 03 Mar '24

03 Mar '24

Attention is currently required from: Benjamin Doron, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Sean Rhodes, Stefan Reinauer. Nicholas Sudsgaard has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80883?usp=email ) Change subject: payload/external/edk2: Explicitly define the build arch ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > what issue are you seeing with the arch not specified / what problem does this resolve? Does this wo […] Without this option, the EDK2 UefiPayloadPkg will not build. One reason may be that it creates `workspace/Build/UefiPayloadPkg$(BUILD_ARCH)` (literally) instead of `workspace/Build/UefiPayloadPkgX64` when `BUILD_ARCH` is not defined. Regarding the UniversalPayload, I can get to the `Successfully build Universal Payload` without any issues with this change. I can't seem to get any further (with or without this change) as it throws this error: ``` Loading previous configuration from /home/nicholas/Development/coreboot/payloads/external/edk2/workspace/starlabsltd/Conf/BuildEnv.sh Using EDK2 in-source Basetools WORKSPACE: /home/nicholas/Development/coreboot/payloads/external/edk2/workspace EDK_TOOLS_PATH: /home/nicholas/Development/coreboot/payloads/external/edk2/workspace/starlabsltd/BaseTools CONF_PATH: /home/nicholas/Development/coreboot/payloads/external/edk2/workspace/starlabsltd/Conf Build environment: Linux-6.5.0-21-generic-x86_64-with-glibc2.35 Build start time: 00:56:51, Mar.03 2024 WORKSPACE = /home/nicholas/Development/coreboot/payloads/external/edk2/workspace PACKAGES_PATH = /home/nicholas/Development/coreboot/payloads/external/edk2/workspace/starlabsltd EDK_TOOLS_PATH = /home/nicholas/Development/coreboot/payloads/external/edk2/workspace/starlabsltd/BaseTools CONF_PATH = /home/nicholas/Development/coreboot/payloads/external/edk2/workspace/starlabsltd/Conf PYTHON_COMMAND = python3 Architecture(s) = IA32 X64 Build target = RELEASE Toolchain = COREBOOT Processing meta-data Active Platform = /home/nicholas/Development/coreboot/payloads/external/edk2/workspace/starlabsltd/UefiPayloadPkg/UefiPayloadPkg.dsc .Active Module = /home/nicholas/Development/coreboot/payloads/external/edk2/workspace/starlabsltd/UefiPayloadPkg/ShimLayer/ShimLayer.inf build.py... /home/nicholas/Development/coreboot/payloads/external/edk2/workspace/starlabsltd/UefiPayloadPkg/UefiPayloadPkg.dsc(...): error 4000: Instance of library class [UefiCpuLib] is not found in [/home/nicholas/Development/coreboot/payloads/external/edk2/workspace/starlabsltd/UefiPayloadPkg/ShimLayer/ShimLayer.inf] [IA32] consumed by module [/home/nicholas/Development/coreboot/payloads/external/edk2/workspace/starlabsltd/UefiPayloadPkg/ShimLayer/ShimLayer.inf] - Failed - Build end time: 00:56:52, Mar.03 2024 Build total time: 00:00:01 make[1]: *** [Makefile:295: /home/nicholas/Development/coreboot/payloads/external/edk2/workspace/Build/UefiPayloadPkgX64/RELEASE_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll] Error 1 make: *** [payloads/external/Makefile.mk:207: build/ShimmedUniversalPayload.elf] Error 2 ``` Doing some light digging it appears that `UefiCpuLib` was removed/merged into `CpuLib` (`git log --grep UefiCpuLib`). I changed all instances of `UefiCpuLib` to `CpuLib` and it appears to compile. One thing to note is that I'm not very familiar with edk2 and may be doing something wrong here. -- To view, visit https://review.coreboot.org/c/coreboot/+/80883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Gerrit-Change-Number: 80883 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sun, 03 Mar 2024 01:16:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: payload/external/edk2: Explicitly define the build arch
by Nicholas Sudsgaard (Code Review) 03 Mar '24

03 Mar '24

Attention is currently required from: Benjamin Doron, Lean Sheng Tan, Martin L Roth, Nicholas Sudsgaard, Sean Rhodes, Stefan Reinauer. Hello Benjamin Doron, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Sean Rhodes, Stefan Reinauer, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80883?usp=email to look at the new patch set (#2). Change subject: payload/external/edk2: Explicitly define the build arch ...................................................................... payload/external/edk2: Explicitly define the build arch Upstream commit 11ad164bce (UefiPayloadPkg: Make UPL build script arch agnostic, 2024-02-22) changes the build script's behavior to not assume the arch. Without defining BUILD_ARCH, the build script will not function properly and results in the payload failing to build. Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Signed-off-by: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> --- M payloads/external/edk2/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/80883/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Gerrit-Change-Number: 80883 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: lib/ramdetect: Limit probe size to function argument
by ron minnich (Code Review) 02 Mar '24

02 Mar '24

Attention is currently required from: Arthur Heymans, Nico Huber, Philipp Hug. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68842?usp=email ) Change subject: lib/ramdetect: Limit probe size to function argument ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/68842?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f915c6e150629eff235ee94719172467a54db2 Gerrit-Change-Number: 68842 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sat, 02 Mar 2024 22:23:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[main]: soc/sifive/fu740: Add FU740 SOC
by Maximilian Brune (Code Review) 02 Mar '24

02 Mar '24

Attention is currently required from: Martin L Roth, Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76689?usp=email ) Change subject: soc/sifive/fu740: Add FU740 SOC ...................................................................... Patch Set 13: (9 comments) File src/soc/sifive/fu740/Makefile.inc: https://review.coreboot.org/c/coreboot/+/76689/comment/7841b30c_e593f5f9 : PS12, Line 3: ifdef > This needs to be `ifeq ($(CONFIG_SOC_SIFIVE_FU740),y)` […] That was quite the blooper. I am wondering why it even compiled then. File src/soc/sifive/fu740/cbmem.c: https://review.coreboot.org/c/coreboot/+/76689/comment/793f52ba_fdd8254f : PS12, Line 11: #define FU740_MAXDRAM 0x800000000ULL // 32 GiB > Can we move this outside of the function? I only put it in here to emphasis it is only used here and for all other operations `sdram_size()` is supposed to be the source of truth regarding dram size. File src/soc/sifive/fu740/clint.c: https://review.coreboot.org/c/coreboot/+/76689/comment/0b49f026_6d0af326 : PS12, Line 11: (uint64_t *)(FU740_CLINT + 0xbff8); : HLS()->timecmp = (uint64_t *)(FU740_CLINT + 0x4000 + 8 * hart_id); > Can the magic numbers be made into #defines? Done https://review.coreboot.org/c/coreboot/+/76689/comment/0d7131c0_e5f85ad4 : PS12, Line 17: 4 * (uintptr_t)hartid > I assume this means we're always 32-bit? If that's not the case, should hartid be cast to a 32-bit v […] We are 64 bit always. Therefore before casting it to a (void *) I need to cast it to a 64 bit value. File src/soc/sifive/fu740/clock.c: https://review.coreboot.org/c/coreboot/+/76689/comment/5df3028d_d835770f : PS12, Line 16: * > Nit: Add some spaces around '*'? Done https://review.coreboot.org/c/coreboot/+/76689/comment/9c07af08_db2a32c5 : PS12, Line 153: Oszillator > oscillator? I accidentally used the german word. File src/soc/sifive/fu740/ddrregs.c: https://review.coreboot.org/c/coreboot/+/76689/comment/a4da0bb0_0d41ad04 : PS12, Line 1: /* SPDX-License-Identifier: Apache-2.0 */ > Did this file come from somewhere else? Why not just GPL? First I copied the magic values from our fu540 implementation (that is where the apache license comes from), but that didn't work so I got my values from SiFive u-boot devicetree. Since that is also GPL licensed, I removed the Apache license now. https://review.coreboot.org/c/coreboot/+/76689/comment/0092a354_92b24d89 : PS12, Line 9: DENALI_PHY_00_DATA > Why bother with the #defines? why not just include the data directly? good point. They are magic values anyway. File src/soc/sifive/fu740/spi_internal.h: https://review.coreboot.org/c/coreboot/+/76689/comment/784c9867_5b069fbf : PS12, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ > Put this into the include directory? This file contains the SPI stuff that is not needed outside of the SOC code. `include/soc/spi.h` contains the SPI code needed for configurating things in mainboard code. I tried to separate it similar to the fu540 SOC for future SiFive SOC common code. -- To view, visit https://review.coreboot.org/c/coreboot/+/76689?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a8fe02ef0adcb939aa65377a35874715c5ee58a Gerrit-Change-Number: 76689 Gerrit-PatchSet: 13 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sat, 02 Mar 2024 20:59:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[main]: soc/sifive/fu740: Add FU740 SOC
by Maximilian Brune (Code Review) 02 Mar '24

02 Mar '24

Attention is currently required from: Maximilian Brune, Philipp Hug, ron minnich. Hello Philipp Hug, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/76689?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Code-Review+2 by Philipp Hug, Code-Review+2 by ron minnich, Verified+1 by build bot (Jenkins) Change subject: soc/sifive/fu740: Add FU740 SOC ...................................................................... soc/sifive/fu740: Add FU740 SOC Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I4a8fe02ef0adcb939aa65377a35874715c5ee58a --- M src/soc/sifive/fu540/include/soc/spi.h A src/soc/sifive/fu740/Kconfig A src/soc/sifive/fu740/Makefile.inc A src/soc/sifive/fu740/TODO A src/soc/sifive/fu740/cbmem.c A src/soc/sifive/fu740/chip.c A src/soc/sifive/fu740/clint.c A src/soc/sifive/fu740/clock.c A src/soc/sifive/fu740/ddrregs.c A src/soc/sifive/fu740/gpio.c A src/soc/sifive/fu740/include/soc/addressmap.h A src/soc/sifive/fu740/include/soc/clock.h A src/soc/sifive/fu740/include/soc/gpio.h A src/soc/sifive/fu740/include/soc/otp.h A src/soc/sifive/fu740/include/soc/sdram.h A src/soc/sifive/fu740/include/soc/spi.h A src/soc/sifive/fu740/memlayout.ld A src/soc/sifive/fu740/otp.c A src/soc/sifive/fu740/sdram.c A src/soc/sifive/fu740/spi.c A src/soc/sifive/fu740/spi_internal.h A src/soc/sifive/fu740/uart.c 22 files changed, 3,190 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/76689/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/76689?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a8fe02ef0adcb939aa65377a35874715c5ee58a Gerrit-Change-Number: 76689 Gerrit-PatchSet: 13 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

1 0

[XL] Change in coreboot[main]: Revert "mb/sifive: Add Hifive Unmatched mainboard"
by Martin L Roth (Code Review) 02 Mar '24

02 Mar '24

Martin L Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80943?usp=email ) Change subject: Revert "mb/sifive: Add Hifive Unmatched mainboard" ...................................................................... Revert "mb/sifive: Add Hifive Unmatched mainboard" This reverts commit e26bcaefbeb1d64cf2a78ad54e0f6ad4affab086. Reason for revert: Patch submitted out of order. Change-Id: I71c024b13411c4e0c9b4d6358f9cd31c57bbbfe2 Signed-off-by: Martin Roth <gaumless(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80943 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: David Hendricks <david.hendricks(a)gmail.com> --- D src/mainboard/sifive/hifive-unmatched/Kconfig D src/mainboard/sifive/hifive-unmatched/Kconfig.name D src/mainboard/sifive/hifive-unmatched/Makefile.inc D src/mainboard/sifive/hifive-unmatched/board_info.txt D src/mainboard/sifive/hifive-unmatched/cbfs_spi.c D src/mainboard/sifive/hifive-unmatched/devicetree.cb D src/mainboard/sifive/hifive-unmatched/fixup_fdt.c D src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi D src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts D src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts D src/mainboard/sifive/hifive-unmatched/mainboard.c D src/mainboard/sifive/hifive-unmatched/romstage.c 12 files changed, 0 insertions(+), 1,189 deletions(-) Approvals: build bot (Jenkins): Verified David Hendricks: Looks good to me, approved diff --git a/src/mainboard/sifive/hifive-unmatched/Kconfig b/src/mainboard/sifive/hifive-unmatched/Kconfig deleted file mode 100644 index a163911..0000000 --- a/src/mainboard/sifive/hifive-unmatched/Kconfig +++ /dev/null @@ -1,24 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -if BOARD_SIFIVE_HIFIVE_UNMATCHED - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select SOC_SIFIVE_FU740 - select BOARD_ROMSIZE_KB_32768 - select MISSING_BOARD_RESET - select FLATTENED_DEVICE_TREE - select SPI_FLASH - select SPI_FLASH_ISSI - select SPI_SDCARD - -config HEAP_SIZE - default 0x10000 #TODO - -config MAINBOARD_DIR - default "sifive/hifive-unmatched" - -config MAINBOARD_PART_NUMBER - default "HiFive Unmatched" - -endif diff --git a/src/mainboard/sifive/hifive-unmatched/Kconfig.name b/src/mainboard/sifive/hifive-unmatched/Kconfig.name deleted file mode 100644 index bbba82c..0000000 --- a/src/mainboard/sifive/hifive-unmatched/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_SIFIVE_HIFIVE_UNMATCHED - bool "HiFive Unmatched" diff --git a/src/mainboard/sifive/hifive-unmatched/Makefile.inc b/src/mainboard/sifive/hifive-unmatched/Makefile.inc deleted file mode 100644 index 0463be5..0000000 --- a/src/mainboard/sifive/hifive-unmatched/Makefile.inc +++ /dev/null @@ -1,16 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += romstage.c -bootblock-y += cbfs_spi.c - -ramstage-y += cbfs_spi.c -ramstage-y += fixup_fdt.c - -DTB=$(obj)/hifive-unmatched.dtb -DTS=src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts -$(DTB): $(DTS) - dtc -I dts -O dtb -o $(DTB) $(DTS) - -cbfs-files-y += fallback/DTB -fallback/DTB-file := $(DTB) -fallback/DTB-type := raw diff --git a/src/mainboard/sifive/hifive-unmatched/board_info.txt b/src/mainboard/sifive/hifive-unmatched/board_info.txt deleted file mode 100644 index e48ba27..0000000 --- a/src/mainboard/sifive/hifive-unmatched/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Category: eval -ROM package: SOIC-16 -ROM protocol: SPI -ROM socketed: n -Flashrom support: n -Board URL: https://www.crowdsupply.com/sifive/hifive-unmatched diff --git a/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c b/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c deleted file mode 100644 index 787d8e7..0000000 --- a/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c +++ /dev/null @@ -1,173 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * This file is basically drivers/spi/cbfs_spi.cb but the boot device is not known at build time - */ - -#include <boot_device.h> -#include <cbfs.h> -#include <console/console.h> -#include <device/mmio.h> -#include <lib.h> -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <soc/spi.h> -#include <spi_flash.h> -#include <spi_sdcard.h> -#include <stdint.h> -#include <symbols.h> -#include <timer.h> - -// There are two different means of accessing the SPI flash. -// They are controlled by the fctrl register. -// 1. memory mapped access -// 2. FIFO based access - -/* follow is the FSBL boot device defined by ZSBL of sifive - * FSBL replaced by bootblock of coreboot - * MSEL_SPInx1 -> test if boot from memory-mapped on SPIn - * MSEL_SPInx4 -> test if boot from memory-mapped on QPIn - * MSEL_SPInSD -> test if boot from sdcard mount on SPIn */ -#define MSEL_SPI0x1(m) (((m) == 5) || ((m) == 14)) -#define MSEL_SPI0x4(m) (((m) == 6) || ((m) == 10) || ((m) == 15)) -#define MSEL_SPI1x1(m) ((m) == 12) -#define MSEL_SPI1x4(m) (((m) == 7) || ((m) == 13)) -#define MSEL_SPI1SD(m) ((m) == 8) -#define MSEL_SPI2x1(m) ((m) == 9) -#define MSEL_SPI2SD(m) ((m) == 11) - -#define MSEL_ACCESS_METHOD_MMAP(m) ((m == 5) || (m == 6) || (m == 7) || (m == 10) || (m == 13)) - -// probably something for devicetree -struct fu740_spi_config fu740_spi_configs[] = { - { 0 }, - { - .freq = 10*1000*1000, - }, - { 0 }, -}; - -static struct spi_sdcard spi2_sdcard; //TODO initialize SPI2 -//static struct spi_flash spi0_flash; -//static struct spi_flash spi1_flash; -static struct spi_flash spi_flash; -static bool spi_flash_init_done; - -static ssize_t sd_readat(const struct region_device *rdev, void *dest, - size_t offset, size_t count) -{ - spi_sdcard_read(&spi2_sdcard, dest, offset, count); - return count; -} - -static ssize_t spi_readat(const struct region_device *rd, void *b, size_t offset, size_t size) -{ - if (spi_flash_read(&spi_flash, offset, size, b)) - return -1; - return size; -} - -static ssize_t spi_writeat(const struct region_device *rd, const void *b, - size_t offset, size_t size) -{ - if (spi_flash_write(&spi_flash, offset, size, b)) - return -1; - return size; -} - -static ssize_t spi_eraseat(const struct region_device *rd, size_t offset, size_t size) -{ - if (spi_flash_erase(&spi_flash, offset, size)) - return -1; - return size; -} - -static const struct region_device_ops sd_ops = { - .mmap = mmap_helper_rdev_mmap, - .munmap = mmap_helper_rdev_munmap, - .readat = sd_readat, -}; - -static const struct region_device_ops spi_ops = { - .mmap = mmap_helper_rdev_mmap, - .munmap = mmap_helper_rdev_munmap, - .readat = spi_readat, - .writeat = spi_writeat, - .eraseat = spi_eraseat, -}; - -//TODO using postram cache means that all spi transitions are transferred to actual memory. -// Native memory mapping obviously doesnt have that problem. That can however only happen if -// memory has been initialized before accessing the boot device. So no CBFS access before boot. -//static struct mem_pool mem_cbfs_cache = -// MEM_POOL_INIT(_postram_cbfs_cache, REGION_SIZE(postram_cbfs_cache), CONFIG_CBFS_CACHE_ALIGN); -//static struct mmap_helper_region_device spi_mdev = -// MMAP_HELPER_DEV_INIT(&spi_ops, 0, CONFIG_ROM_SIZE, &mem_cbfs_cache); - -static struct mmap_helper_region_device spi_mdev = - MMAP_HELPER_DEV_INIT(&spi_ops, 0, CONFIG_ROM_SIZE, &cbfs_cache); - -static struct mmap_helper_region_device sd_mdev = - MMAP_HELPER_DEV_INIT(&sd_ops, 0, CONFIG_ROM_SIZE, &cbfs_cache); - -void boot_device_init(void) -{ - printk(BIOS_DEBUG, "%s 0\n", __func__); - if (spi_flash_init_done == true) - return; - - uint32_t m = read32((uint32_t *)FU740_MSEL); - // Pass the information of the flash read operation to the spi controller - //.pad_cnt = 6, - if (MSEL_SPI0x4(m) || MSEL_SPI1x4(m)) { - //config.ffmt_config.data_proto = FU740_SPI_PROTO_Q; - //config.ffmt_config.cmd_code = 0x6B; // Quad output read - //.cmd_code = 0xec, - } - if (MSEL_SPI1x1(m)) { - printk(BIOS_DEBUG, "%s 1\n", __func__); - fu740_spi_configs[1].ffmt_config.data_proto = FU740_SPI_PROTO_S; - fu740_spi_configs[1].ffmt_config.cmd_code = 0x03; // Normal read - //TODO SPI1x1 is always using programmed IO (FIFO)? (memory map did not work...) - if (spi_flash_probe(1, 0, &spi_flash)) { - printk(BIOS_EMERG, "failed to init SPI flash\n"); - return; - } - // initialize soc spi controller - //if (fu740_spi_setup(&spi1_flash.spi) == -1) { - // printk(BIOS_EMERG, "failed to configure mmap for SPI flash\n"); - //} - //hexdump((void*)0x10041000, 0x100); - //hexdump((void*)0x30000000, 0x100); - printk(BIOS_DEBUG, "%s 2\n", __func__); - } else if (MSEL_SPI2SD(m)) { - spi_sdcard_init(&spi2_sdcard, 2, 0); - } else { - die("Wrong configuration of MSEL\n"); - } - - spi_flash_init_done = true; -} - -/* Return the CBFS boot device. */ -const struct region_device *boot_device_ro(void) -{ - if (spi_flash_init_done != true) - return NULL; - - uint32_t m = read32((uint32_t *)FU740_MSEL); - - if (MSEL_SPI2SD(m) || MSEL_SPI1SD(m)) - return &sd_mdev.rdev; - return &spi_mdev.rdev; -} - -//const struct spi_flash *boot_device_spi_flash(void) -//{ -// boot_device_init(); -// -// if (spi_flash_init_done != true) -// return NULL; -// -// return &spi_flash; -//} diff --git a/src/mainboard/sifive/hifive-unmatched/devicetree.cb b/src/mainboard/sifive/hifive-unmatched/devicetree.cb deleted file mode 100644 index 3d52b54..0000000 --- a/src/mainboard/sifive/hifive-unmatched/devicetree.cb +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -chip soc/sifive/fu740 - device cpu_cluster 0 on end -end diff --git a/src/mainboard/sifive/hifive-unmatched/fixup_fdt.c b/src/mainboard/sifive/hifive-unmatched/fixup_fdt.c deleted file mode 100644 index ed24ee3..0000000 --- a/src/mainboard/sifive/hifive-unmatched/fixup_fdt.c +++ /dev/null @@ -1,106 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <stdint.h> -#include <stdlib.h> -#include <string.h> -#include <console/console.h> -#include <soc/otp.h> -#include <soc/sdram.h> -#include <cbfs.h> -#include <device_tree.h> -#include <bootstate.h> -#include <mcall.h> - -static void do_fixup_mac(struct device_tree_node *node) -{ - uint32_t serial = otp_read_serial(); - static unsigned char mac[6] = { 0x70, 0xb3, 0xd5, 0x92, 0xf0, 0x00 }; - if (serial != ~0) { - mac[5] |= (serial >> 0) & 0xff; - mac[4] |= (serial >> 8) & 0xff; - mac[3] |= (serial >> 16) & 0xff; - } - dt_add_bin_prop(node, "local-mac-address", mac, 6); -} - -static void fixup_mac(struct device_tree_node *parent) -{ - struct device_tree_property *prop; - const char *name = "local-mac-address"; - - list_for_each(prop, parent->properties, list_node) { - if (!strcmp(name, prop->prop.name)) - do_fixup_mac(parent); - } - - struct device_tree_node *child; - list_for_each(child, parent->children, list_node) { - fixup_mac(child); - } -} - -static void do_fixup_memory(struct device_tree_node *node) -{ - u64 addrs[1], sizes[1]; - addrs[0] = 0x80000000; - sizes[0] = sdram_size(); - dt_add_reg_prop(node, addrs, sizes, 1, 2, 2); -} - -static void fixup_memory(struct device_tree_node *parent) -{ - struct device_tree_property *prop; - const char *name = "device_type"; - const char *value = "memory"; - - list_for_each(prop, parent->properties, list_node) { - if (!strcmp(name, prop->prop.name)) { - if (!strcmp(value, (char *)prop->prop.data)) - do_fixup_memory(parent); - } - } - - struct device_tree_node *child; - list_for_each(child, parent->children, list_node) { - fixup_memory(child); - } -} - -static void fixup_fdt(void *unused) -{ - printk(BIOS_DEBUG, "fix up FDT\n"); - - void *fdt_rom; - struct device_tree *tree; - - /* load flat dt from cbfs */ - fdt_rom = cbfs_map("fallback/DTB", NULL); - - if (fdt_rom == NULL) { - printk(BIOS_ERR, "Unable to load fallback/DTB from CBFS\n"); - return; - } - - /* Expand DT into a tree */ - tree = fdt_unflatten(fdt_rom); - - /* fixup tree */ - fixup_mac(tree->root); - fixup_memory(tree->root); - - /* convert the tree to a flat dt */ - void *dt = malloc(dt_flat_size(tree)); - - if (dt == NULL) { - printk(BIOS_ERR, "Unable to allocate memory for flat device tree\n"); - return; - } - - dt_flatten(tree, dt); - - /* update HLS */ - for (int i = 0; i < CONFIG_MAX_CPUS; i++) - OTHER_HLS(i)->fdt = dt; -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_EXIT, fixup_fdt, NULL); diff --git a/src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi b/src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi deleted file mode 100644 index 823240c..0000000 --- a/src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi +++ /dev/null @@ -1,363 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/dts-v1/; - -/ { - #address-cells = <2>; - #size-cells = <2>; - compatible = "sifive,fu740-c000", "sifive,fu740"; - - aliases { - serial0 = &uart0; - serial1 = &uart1; - ethernet0 = &eth0; - }; - - chosen { - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - cpu0: cpu@0 { - compatible = "sifive,bullet0", "riscv"; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <16384>; - next-level-cache = <&ccache>; - reg = <0x0>; - riscv,isa = "rv64imac"; - // the S7 core does not support Supervisor mode and has no FPU - status = "disabled"; - cpu0_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu1: cpu@1 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x1>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu1_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu2: cpu@2 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x2>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu2_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu3: cpu@3 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x3>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu3_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - cpu4: cpu@4 { - compatible = "sifive,bullet0", "riscv"; - d-cache-block-size = <64>; - d-cache-sets = <64>; - d-cache-size = <32768>; - d-tlb-sets = <1>; - d-tlb-size = <40>; - device_type = "cpu"; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - i-tlb-sets = <1>; - i-tlb-size = <40>; - mmu-type = "riscv,sv39"; - next-level-cache = <&ccache>; - reg = <0x4>; - riscv,isa = "rv64imafdc"; - tlb-split; - cpu4_intc: interrupt-controller { - #interrupt-cells = <1>; - compatible = "riscv,cpu-intc"; - interrupt-controller; - }; - }; - - cpu-map { - cluster0 { - core0 { - cpu = <&cpu0>; - }; - - core1 { - cpu = <&cpu1>; - }; - - core2 { - cpu = <&cpu2>; - }; - - core3 { - cpu = <&cpu3>; - }; - - core4 { - cpu = <&cpu4>; - }; - }; - }; - }; - soc { - #address-cells = <2>; - #size-cells = <2>; - compatible = "simple-bus"; - ranges; - // clint is mainly used by openSBI and not the OS, since interrupts-extended currently only - // contains machine mode interrupts which the OS will ignore if not running in machine mode - clint: clint@2000000 { - compatible = "riscv,clint0"; - //TODO Add RISCV_M_SOFT_IRQ and RISCV_M_TIME_IRQ macros for better readability - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7 - &cpu1_intc 3 &cpu1_intc 7 - &cpu2_intc 3 &cpu2_intc 7 - &cpu3_intc 3 &cpu3_intc 7 - &cpu4_intc 3 &cpu4_intc 7>; - reg = <0x0 0x2000000 0x0 0x10000>; - }; - plic0: interrupt-controller@c000000 { - #interrupt-cells = <1>; - #address-cells = <0>; - compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0"; - reg = <0x0 0xc000000 0x0 0x4000000>; - riscv,ndev = <69>; - interrupt-controller; - interrupts-extended = - <&cpu0_intc 0xffffffff>, - <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>, - <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>, - <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>, - <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>; - }; - prci: clock-controller@10000000 { - compatible = "sifive,fu740-c000-prci"; - reg = <0x0 0x10000000 0x0 0x1000>; - clocks = <&hfclk>, <&rtcclk>; - #clock-cells = <1>; - #reset-cells = <1>; - }; - uart0: serial@10010000 { - compatible = "sifive,fu740-c000-uart", "sifive,uart0"; - reg = <0x0 0x10010000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <39>; - clocks = <&prci 7>; - status = "disabled"; - }; - uart1: serial@10011000 { - compatible = "sifive,fu740-c000-uart", "sifive,uart0"; - reg = <0x0 0x10011000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <40>; - clocks = <&prci 7>; - status = "disabled"; - }; - i2c0: i2c@10030000 { - compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; - reg = <0x0 0x10030000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <52>; - clocks = <&prci 7>; - reg-shift = <2>; - reg-io-width = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - i2c1: i2c@10031000 { - compatible = "sifive,fu740-c000-i2c", "sifive,i2c0"; - reg = <0x0 0x10031000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <53>; - clocks = <&prci 7>; - reg-shift = <2>; - reg-io-width = <1>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi0: spi@10040000 { - compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10040000 0x0 0x1000>, - <0x0 0x20000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <41>; - clocks = <&prci 7>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - qspi1: spi@10041000 { - compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10041000 0x0 0x1000>, - <0x0 0x30000000 0x0 0x10000000>; - interrupt-parent = <&plic0>; - interrupts = <42>; - clocks = <&prci 7>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - spi0: spi@10050000 { - compatible = "sifive,fu740-c000-spi", "sifive,spi0"; - reg = <0x0 0x10050000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <43>; - clocks = <&prci 7>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; - eth0: ethernet@10090000 { - compatible = "sifive,fu540-c000-gem"; - interrupt-parent = <&plic0>; - interrupts = <55>; - reg = <0x0 0x10090000 0x0 0x2000>, - <0x0 0x100a0000 0x0 0x1000>; - local-mac-address = [00 00 00 00 00 00]; - clock-names = "pclk", "hclk"; - clocks = <&prci 2>, - <&prci 2>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - phandle = <0x13>; //TODO remove - }; - pwm0: pwm@10020000 { - compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10020000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <44>, <45>, <46>, <47>; - clocks = <&prci 7>; - #pwm-cells = <3>; - status = "disabled"; - }; - pwm1: pwm@10021000 { - compatible = "sifive,fu740-c000-pwm", "sifive,pwm0"; - reg = <0x0 0x10021000 0x0 0x1000>; - interrupt-parent = <&plic0>; - interrupts = <48>, <49>, <50>, <51>; - clocks = <&prci 7>; - #pwm-cells = <3>; - status = "disabled"; - }; - ccache: cache-controller@2010000 { - compatible = "sifive,fu740-c000-ccache", "cache"; - cache-block-size = <64>; - cache-level = <2>; - cache-sets = <2048>; - cache-size = <2097152>; - cache-unified; - interrupt-parent = <&plic0>; - interrupts = <19>, <21>, <22>, <20>; - reg = <0x0 0x2010000 0x0 0x1000>; - }; - gpio: gpio@10060000 { - compatible = "sifive,fu740-c000-gpio", "sifive,gpio0"; - interrupt-parent = <&plic0>; - interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>, - <30>, <31>, <32>, <33>, <34>, <35>, <36>, - <37>, <38>; - reg = <0x0 0x10060000 0x0 0x1000>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - clocks = <&prci 7>; - status = "disabled"; - }; - pcie@e00000000 { - compatible = "sifive,fu740-pcie"; - #address-cells = <3>; - #size-cells = <2>; - #interrupt-cells = <1>; - reg = <0xe 0x00000000 0x0 0x80000000>, - <0xd 0xf0000000 0x0 0x10000000>, - <0x0 0x100d0000 0x0 0x1000>; - reg-names = "dbi", "config", "mgmt"; - device_type = "pci"; - dma-coherent; - bus-range = <0x0 0xff>; - //TODO - //ranges = <0x81000000 0x0 0x60080000 0x0 0x60080000 0x0 0x10000>, /* I/O */ - // <0x82000000 0x0 0x60090000 0x0 0x60090000 0x0 0xff70000>, /* mem */ - // <0x82000000 0x0 0x70000000 0x0 0x70000000 0x0 0x1000000>, /* mem */ - // <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>; /* mem prefetchable */ - ranges = <0x81000000 0x00 0x60080000 0x00 0x60080000 0x00 0x10000 0x82000000 0x00 0x60090000 0x00 0x60090000 0x00 0xff70000 0x82000000 0x00 0x70000000 0x00 0x70000000 0x00 0x10000000 0xc3000000 0x20 0x00 0x20 0x00 0x20 0x00>; - num-lanes = <0x8>; - interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>; - interrupt-names = "msi", "inta", "intb", "intc", "intd"; - interrupt-parent = <&plic0>; - interrupt-map-mask = <0x0 0x0 0x0 0x7>; - interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>, - <0x0 0x0 0x0 0x2 &plic0 58>, - <0x0 0x0 0x0 0x3 &plic0 59>, - <0x0 0x0 0x0 0x4 &plic0 60>; - clock-names = "pcie_aux"; - clocks = <&prci 8>; - pwren-gpios = <&gpio 5 0>; - reset-gpios = <&gpio 8 0>; - resets = <&prci 4>; - status = "okay"; - }; - }; -}; diff --git a/src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts b/src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts deleted file mode 100644 index 715ec1b..0000000 --- a/src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts +++ /dev/null @@ -1,232 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/include/ "fu740-c000.dtsi" - -/ { - model = "SiFive HiFive Unmatched A00"; - compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", "sifive,fu740"; - - cpus { - //TODO replace with CLOCK_FREQUENCY macro that is used in both code and here to have a single source of truth - timebase-frequency = <1000000>; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x4 0x00000000>; - }; - - hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - clock-output-names = "hfclk"; - }; - - rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1000000>; - clock-output-names = "rtcclk"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - vcc-supply = <&vdd_bpro>; - interrupt-parent = <&gpio>; - interrupts = <6 8>; - }; - - eeprom@54 { - compatible = "microchip,24c02", "atmel,24c02"; - reg = <0x54>; - label = "board-id"; - vcc-supply = <0x10>; - pagesize = <16>; - read-only; - size = <256>; - }; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio>; - interrupts = <1 8>; - interrupt-controller; - - onkey { - compatible = "dlg,da9063-onkey"; - }; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - - regulators { - vdd_bcore: bcores-merged { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-min-microamp = <4800000>; - regulator-max-microamp = <4800000>; - regulator-always-on; - }; - - vdd_bpro: bpro { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-min-microamp = <2400000>; - regulator-max-microamp = <2400000>; - regulator-always-on; - }; - - vdd_bperi: bperi { - regulator-min-microvolt = <1060000>; - regulator-max-microvolt = <1060000>; - regulator-min-microamp = <1500000>; - regulator-max-microamp = <1500000>; - regulator-always-on; - }; - - vdd_bmem_bio: bmem-bio-merged { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <3000000>; - regulator-always-on; - }; - - vdd_ldo1: ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo2: ldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo3: ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo4: ldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_ldo5: ldo5 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo6: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo7: ldo7 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo8: ldo8 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ld09: ldo9 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - vdd_ldo10: ldo10 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_ldo11: ldo11 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - }; - }; - -}; - -&qspi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&spi0 { - status = "okay"; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3300 3300>; - disable-wp; - gpios = <0x11 0x0f 0x01>; - }; -}; - -&eth0 { - status = "okay"; - phy-mode = "gmii"; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&gpio { - status = "okay"; - gpio-line-names = "J29.1", "PMICNTB", "PMICSHDN", "J8.1", "J8.3", - "PCIe_PWREN", "THERM", "UBRDG_RSTN", "PCIe_PERSTN", - "ULPI_RSTN", "J8.2", "UHUB_RSTN", "GEMGXL_RST", "J8.4", - "EN_VDD_SD", "SD_CD"; -}; diff --git a/src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts b/src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts deleted file mode 100644 index 715ec1b..0000000 --- a/src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts +++ /dev/null @@ -1,232 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/include/ "fu740-c000.dtsi" - -/ { - model = "SiFive HiFive Unmatched A00"; - compatible = "sifive,hifive-unmatched-a00", "sifive,fu740-c000", "sifive,fu740"; - - cpus { - //TODO replace with CLOCK_FREQUENCY macro that is used in both code and here to have a single source of truth - timebase-frequency = <1000000>; - }; - - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0x4 0x00000000>; - }; - - hfclk: hfclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <26000000>; - clock-output-names = "hfclk"; - }; - - rtcclk: rtcclk { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <1000000>; - clock-output-names = "rtcclk"; - }; -}; - -&uart0 { - status = "okay"; -}; - -&uart1 { - status = "okay"; -}; - -&i2c0 { - status = "okay"; - - temperature-sensor@4c { - compatible = "ti,tmp451"; - reg = <0x4c>; - vcc-supply = <&vdd_bpro>; - interrupt-parent = <&gpio>; - interrupts = <6 8>; - }; - - eeprom@54 { - compatible = "microchip,24c02", "atmel,24c02"; - reg = <0x54>; - label = "board-id"; - vcc-supply = <0x10>; - pagesize = <16>; - read-only; - size = <256>; - }; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio>; - interrupts = <1 8>; - interrupt-controller; - - onkey { - compatible = "dlg,da9063-onkey"; - }; - - rtc { - compatible = "dlg,da9063-rtc"; - }; - - watchdog { - compatible = "dlg,da9063-watchdog"; - }; - - regulators { - vdd_bcore: bcores-merged { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-min-microamp = <4800000>; - regulator-max-microamp = <4800000>; - regulator-always-on; - }; - - vdd_bpro: bpro { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-min-microamp = <2400000>; - regulator-max-microamp = <2400000>; - regulator-always-on; - }; - - vdd_bperi: bperi { - regulator-min-microvolt = <1060000>; - regulator-max-microvolt = <1060000>; - regulator-min-microamp = <1500000>; - regulator-max-microamp = <1500000>; - regulator-always-on; - }; - - vdd_bmem_bio: bmem-bio-merged { - regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; - regulator-min-microamp = <3000000>; - regulator-max-microamp = <3000000>; - regulator-always-on; - }; - - vdd_ldo1: ldo1 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo2: ldo2 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo3: ldo3 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo4: ldo4 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_ldo5: ldo5 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo6: ldo6 { - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - - vdd_ldo7: ldo7 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ldo8: ldo8 { - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_ld09: ldo9 { - regulator-min-microvolt = <1050000>; - regulator-max-microvolt = <1050000>; - regulator-always-on; - }; - - vdd_ldo10: ldo10 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; - regulator-always-on; - }; - - vdd_ldo11: ldo11 { - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - }; - }; - -}; - -&qspi0 { - status = "okay"; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <50000000>; - m25p,fast-read; - spi-tx-bus-width = <4>; - spi-rx-bus-width = <4>; - }; -}; - -&spi0 { - status = "okay"; - mmc@0 { - compatible = "mmc-spi-slot"; - reg = <0>; - spi-max-frequency = <20000000>; - voltage-ranges = <3300 3300>; - disable-wp; - gpios = <0x11 0x0f 0x01>; - }; -}; - -&eth0 { - status = "okay"; - phy-mode = "gmii"; - phy-handle = <&phy0>; - phy0: ethernet-phy@0 { - reg = <0>; - }; -}; - -&pwm0 { - status = "okay"; -}; - -&pwm1 { - status = "okay"; -}; - -&gpio { - status = "okay"; - gpio-line-names = "J29.1", "PMICNTB", "PMICSHDN", "J8.1", "J8.3", - "PCIe_PWREN", "THERM", "UBRDG_RSTN", "PCIe_PERSTN", - "ULPI_RSTN", "J8.2", "UHUB_RSTN", "GEMGXL_RST", "J8.4", - "EN_VDD_SD", "SD_CD"; -}; diff --git a/src/mainboard/sifive/hifive-unmatched/mainboard.c b/src/mainboard/sifive/hifive-unmatched/mainboard.c deleted file mode 100644 index 83a3096..0000000 --- a/src/mainboard/sifive/hifive-unmatched/mainboard.c +++ /dev/null @@ -1,5 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> - -struct chip_operations mainboard_ops = { }; diff --git a/src/mainboard/sifive/hifive-unmatched/romstage.c b/src/mainboard/sifive/hifive-unmatched/romstage.c deleted file mode 100644 index a6a1c13..0000000 --- a/src/mainboard/sifive/hifive-unmatched/romstage.c +++ /dev/null @@ -1,25 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <arch/encoding.h> -#include <cbmem.h> -#include <console/console.h> -#include <program_loading.h> -#include <romstage_common.h> -#include <soc/addressmap.h> -#include <soc/clock.h> -#include <soc/sdram.h> - -void __noreturn romstage_main(void) -{ - write_csr(0x7c1, 0); // CSR_U74_FEATURE_DISABLE (enable all Features) - - clock_init(); - - console_init(); - - sdram_init((u64)16*GiB); - - cbmem_initialize_empty(); - - run_ramstage(); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/80943?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I71c024b13411c4e0c9b4d6358f9cd31c57bbbfe2 Gerrit-Change-Number: 80943 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-MessageType: merged

1 0

[XL] Change in coreboot[main]: Revert "mb/sifive: Add Hifive Unmatched mainboard"
by Martin L Roth (Code Review) 02 Mar '24

02 Mar '24

Attention is currently required from: Maximilian Brune, Philipp Hug, ron minnich. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80943?usp=email ) Change subject: Revert "mb/sifive: Add Hifive Unmatched mainboard" ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Merging to fix broken build. -- To view, visit https://review.coreboot.org/c/coreboot/+/80943?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I71c024b13411c4e0c9b4d6358f9cd31c57bbbfe2 Gerrit-Change-Number: 80943 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: David Hendricks <david.hendricks(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Sat, 02 Mar 2024 18:09:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[XL] Change in coreboot[main]: soc/sifive/fu740: Add FU740 SOC
by Martin L Roth (Code Review) 02 Mar '24

02 Mar '24

Attention is currently required from: Maximilian Brune. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76689?usp=email ) Change subject: soc/sifive/fu740: Add FU740 SOC ...................................................................... Patch Set 12: (8 comments) File src/soc/sifive/fu740/cbmem.c: https://review.coreboot.org/c/coreboot/+/76689/comment/5d2c80c3_116a20b0 : PS12, Line 11: #define FU740_MAXDRAM 0x800000000ULL // 32 GiB Can we move this outside of the function? File src/soc/sifive/fu740/clint.c: https://review.coreboot.org/c/coreboot/+/76689/comment/4e0be3c7_a057fca8 : PS12, Line 11: (uint64_t *)(FU740_CLINT + 0xbff8); : HLS()->timecmp = (uint64_t *)(FU740_CLINT + 0x4000 + 8 * hart_id); Can the magic numbers be made into #defines? https://review.coreboot.org/c/coreboot/+/76689/comment/ca322a35_15c19bd6 : PS12, Line 17: 4 * (uintptr_t)hartid I assume this means we're always 32-bit? If that's not the case, should hartid be cast to a 32-bit value? File src/soc/sifive/fu740/clock.c: https://review.coreboot.org/c/coreboot/+/76689/comment/d9d6e01a_b2ae9372 : PS12, Line 16: * Nit: Add some spaces around '*'? https://review.coreboot.org/c/coreboot/+/76689/comment/dd838532_642f88b8 : PS12, Line 153: Oszillator oscillator? File src/soc/sifive/fu740/ddrregs.c: https://review.coreboot.org/c/coreboot/+/76689/comment/ca504f2e_6798e480 : PS12, Line 1: /* SPDX-License-Identifier: Apache-2.0 */ Did this file come from somewhere else? Why not just GPL? https://review.coreboot.org/c/coreboot/+/76689/comment/e20a3b76_fd1eb4e3 : PS12, Line 9: DENALI_PHY_00_DATA Why bother with the #defines? why not just include the data directly? File src/soc/sifive/fu740/spi_internal.h: https://review.coreboot.org/c/coreboot/+/76689/comment/919fcd69_e8a9fc45 : PS12, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ Put this into the include directory? -- To view, visit https://review.coreboot.org/c/coreboot/+/76689?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a8fe02ef0adcb939aa65377a35874715c5ee58a Gerrit-Change-Number: 76689 Gerrit-PatchSet: 12 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Sat, 02 Mar 2024 18:08:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2024