coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

1 participants
3667 discussions

[XL] Change in coreboot[main]: soc/sifive/fu740: Add FU740 SOC
by ron minnich (Code Review) 03 Mar '24

03 Mar '24

Attention is currently required from: Martin L Roth, Maximilian Brune, Philipp Hug. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76689?usp=email ) Change subject: soc/sifive/fu740: Add FU740 SOC ...................................................................... Patch Set 13: Code-Review+2 (2 comments) File src/soc/sifive/fu740/cbmem.c: https://review.coreboot.org/c/coreboot/+/76689/comment/915e84ef_6fe1b34b : PS12, Line 11: #define FU740_MAXDRAM 0x800000000ULL // 32 GiB > I only put it in here to emphasis it is only used here and for all other operations `sdram_size()` i […] Acknowledged File src/soc/sifive/fu740/spi_internal.h: https://review.coreboot.org/c/coreboot/+/76689/comment/ebbb8984_9a384b75 : PS12, Line 1: /* SPDX-License-Identifier: GPL-2.0-only */ > This file contains the SPI stuff that is not needed outside of the SOC code. `include/soc/spi. […] Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/76689?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a8fe02ef0adcb939aa65377a35874715c5ee58a Gerrit-Change-Number: 76689 Gerrit-PatchSet: 13 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Jan Samek <jan.samek(a)siemens.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Marvin Drees <marvin.drees(a)9elements.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Sun, 03 Mar 2024 21:19:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: 3rdparty: Remove chromeec submodule
by Martin L Roth (Code Review) 03 Mar '24

03 Mar '24

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81024?usp=email ) Change subject: 3rdparty: Remove chromeec submodule ...................................................................... 3rdparty: Remove chromeec submodule The chromeec submodule is the largest submodule being pulled into the coreboot tree, at over 400MB. The main branch also contains the majority of these commits, so restricting it to a single branch still fetches over 350MB. Because there is only a single mainboard directory that enables the build of the chromeec codebase by default, most people are fetching this repo for no reason. Based on this, we're going to change the way that the chromeec submodule is used, fetching it the way we currently fetch external payloads. This gives us 2 large advantages: 1) Only builds that actually need the chromeec repo will pull it down. 2) Each board that wants to build the chromeec codebase can use a different commit, unlike submodules which all use the same "current" commit. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: I357c4c9b506dd3817a308232446144ae889bc220 --- M .gitmodules D 3rdparty/chromeec 2 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/81024/1 diff --git a/.gitmodules b/.gitmodules index 5241f58..1738869 100644 --- a/.gitmodules +++ b/.gitmodules @@ -13,9 +13,6 @@ [submodule "arm-trusted-firmware"] path = 3rdparty/arm-trusted-firmware url = ../arm-trusted-firmware.git -[submodule "3rdparty/chromeec"] - path = 3rdparty/chromeec - url = ../chrome-ec.git [submodule "libhwbase"] path = 3rdparty/libhwbase url = ../libhwbase.git diff --git a/3rdparty/chromeec b/3rdparty/chromeec deleted file mode 160000 index e486b38..0000000 --- a/3rdparty/chromeec +++ /dev/null @@ -1 +0,0 @@ -Subproject commit e486b388a73f1e19f3142774d0b3ee166e8f41ff -- To view, visit https://review.coreboot.org/c/coreboot/+/81024?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I357c4c9b506dd3817a308232446144ae889bc220 Gerrit-Change-Number: 81024 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: mb/google/oak: Don't build the ChromeEC codebase by default
by Martin L Roth (Code Review) 03 Mar '24

03 Mar '24

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81023?usp=email ) Change subject: mb/google/oak: Don't build the ChromeEC codebase by default ...................................................................... mb/google/oak: Don't build the ChromeEC codebase by default Currently, the oak boards are the only boards that build the ChromeEC by default as a part of the coreboot build. As a part of replacing the chromeec submodule with a different build mechanism, disable this default. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Idd4fe45e52dbdd1c8dccf0d2c09d5cf6d61aa839 --- M src/mainboard/google/oak/Kconfig 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/81023/1 diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index 3eba1f0..07c22d4 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -46,14 +46,6 @@ int default 9 -config EC_GOOGLE_CHROMEEC_BOARDNAME - string - default "oak" - -config EC_GOOGLE_CHROMEEC_PD_BOARDNAME - string - default "oak_pd" - ########################################################## #### Update below when adding a new derivative board. #### ########################################################## -- To view, visit https://review.coreboot.org/c/coreboot/+/81023?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idd4fe45e52dbdd1c8dccf0d2c09d5cf6d61aa839 Gerrit-Change-Number: 81023 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

1 0

[L] Change in coreboot[main]: mb/asrock: Add Z87E-ITX (Haswell)
by Nicholas Chin (Code Review) 03 Mar '24

03 Mar '24

Nicholas Chin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81022?usp=email ) Change subject: mb/asrock: Add Z87E-ITX (Haswell) ...................................................................... mb/asrock: Add Z87E-ITX (Haswell) This was done using Haswell autoport, with manual fixes to get the output to build against current main. I do not physically have this board; I was sent the output of autoport with some fixes on top of which I added additional changes. Working: - Haswell MRC.bin Not Working: - S3 resume Not Tested: Change-Id: I56c22d8f5505f9a4da25f8b4406b00978af1a586 Signed-off-by: Nicholas Chin <nic.c3.14(a)gmail.com> --- A src/mainboard/asrock/z87e-itx/Kconfig A src/mainboard/asrock/z87e-itx/Kconfig.name A src/mainboard/asrock/z87e-itx/Makefile.mk A src/mainboard/asrock/z87e-itx/acpi/ec.asl A src/mainboard/asrock/z87e-itx/acpi/platform.asl A src/mainboard/asrock/z87e-itx/acpi/superio.asl A src/mainboard/asrock/z87e-itx/board_info.txt A src/mainboard/asrock/z87e-itx/bootblock.c A src/mainboard/asrock/z87e-itx/data.vbt A src/mainboard/asrock/z87e-itx/devicetree.cb A src/mainboard/asrock/z87e-itx/dsdt.asl A src/mainboard/asrock/z87e-itx/gma-mainboard.ads A src/mainboard/asrock/z87e-itx/gpio.c A src/mainboard/asrock/z87e-itx/hda_verb.c A src/mainboard/asrock/z87e-itx/romstage.c 15 files changed, 539 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/81022/1 diff --git a/src/mainboard/asrock/z87e-itx/Kconfig b/src/mainboard/asrock/z87e-itx/Kconfig new file mode 100644 index 0000000..908c45c --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/Kconfig @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_Z87E_ITX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87e-itx" + +config MAINBOARD_PART_NUMBER + default "Z87E-ITX" + +config USBDEBUG_HCD_INDEX + int + default 1 # This is the top most of the USB-2.0-only ports +endif diff --git a/src/mainboard/asrock/z87e-itx/Kconfig.name b/src/mainboard/asrock/z87e-itx/Kconfig.name new file mode 100644 index 0000000..f152649 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_ASROCK_Z87E_ITX + bool "Z87E-ITX" diff --git a/src/mainboard/asrock/z87e-itx/Makefile.mk b/src/mainboard/asrock/z87e-itx/Makefile.mk new file mode 100644 index 0000000..058a390 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87e-itx/acpi/ec.asl b/src/mainboard/asrock/z87e-itx/acpi/ec.asl new file mode 100644 index 0000000..16990d4 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87e-itx/acpi/platform.asl b/src/mainboard/asrock/z87e-itx/acpi/platform.asl new file mode 100644 index 0000000..aff432b --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87e-itx/acpi/superio.asl b/src/mainboard/asrock/z87e-itx/acpi/superio.asl new file mode 100644 index 0000000..ee2eabe --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <drivers/pc80/pc/ps2_controller.asl> diff --git a/src/mainboard/asrock/z87e-itx/board_info.txt b/src/mainboard/asrock/z87e-itx/board_info.txt new file mode 100644 index 0000000..4b2f887 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/intel/z87e-itx/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87e-itx/bootblock.c b/src/mainboard/asrock/z87e-itx/bootblock.c new file mode 100644 index 0000000..a64cdfb --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/bootblock.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pnp_ops.h> +#include <superio/nuvoton/common/nuvoton.h> +#include <superio/nuvoton/nct6776/nct6776.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_superio(void) +{ + const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); + const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); + const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + + /* Power RAM in S3 and let the PCH handle power failure actions. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); +} diff --git a/src/mainboard/asrock/z87e-itx/data.vbt b/src/mainboard/asrock/z87e-itx/data.vbt new file mode 100644 index 0000000..4bb8666 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/data.vbt Binary files differ diff --git a/src/mainboard/asrock/z87e-itx/devicetree.cb b/src/mainboard/asrock/z87e-itx/devicetree.cb new file mode 100644 index 0000000..9cce8ef --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/devicetree.cb @@ -0,0 +1,147 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +chip northbridge/intel/haswell # FIXME: check ec_present, usb_xhci_on_resume, gfx + register "ec_present" = "false" + register "gfx" = "GMA_STATIC_DISPLAYS(0)" + register "gpu_ddi_e_connected" = "1" + register "gpu_dp_b_hotplug" = "4" + register "gpu_dp_c_hotplug" = "4" + register "gpu_dp_d_hotplug" = "4" + register "panel_cfg" = "{ + .up_delay_ms = 0, + .down_delay_ms = 0, + .cycle_delay_ms = 500, + .backlight_on_delay_ms = 0, + .backlight_off_delay_ms = 0, + .backlight_pwm_hz = 0, + }" + register "usb_xhci_on_resume" = "false" + + chip cpu/intel/haswell + device cpu_cluster 0 on ops haswell_cpu_bus_ops end + end + + device domain 0 on + ops haswell_pci_domain_ops + + device pci 00.0 on # Desktop Host bridge + subsystemid 0x1849 0x0c00 + end + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 on # Internal graphics VGA controller + subsystemid 0x1849 0x0412 + end + device pci 03.0 on # Mini-HD audio + subsystemid 0x1849 0x0c0c + end + + chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0241" + register "gen3_dec" = "0x000c0251" + register "gpe0_en_1" = "0x46" + register "gpe0_en_2" = "0x0" + register "sata_port0_gen3_dtle" = "0x2" + register "sata_port1_gen3_dtle" = "0x2" + register "sata_port_map" = "0x3f" + + device pci 14.0 on # xHCI Controller + subsystemid 0x1849 0x8c31 + end + device pci 16.0 on # Management Engine Interface 1 + subsystemid 0x1849 0x8c3a + end + device pci 16.1 off # Management Engine Interface 2 + end + device pci 16.2 off # Management Engine IDE-R + end + device pci 16.3 off # Management Engine KT + end + device pci 19.0 on # Intel Gigabit Ethernet + subsystemid 0x1849 0x153b + end + device pci 1a.0 on # USB2 EHCI #2 + subsystemid 0x1849 0x8c2d + end + device pci 1b.0 on # High Definition Audio + subsystemid 0x1849 0x1150 + end + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 + device pci 1c.2 on end # PCIe Port #3 + device pci 1c.3 on end # PCIe Port #4 + device pci 1c.4 on end # PCIe Port #5 + device pci 1c.5 on end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 on end # PCIe Port #8 + device pci 1d.0 on # USB2 EHCI #1 + subsystemid 0x1849 0x8c26 + end + device pci 1f.0 on # LPC bridge + subsystemid 0x1849 0x8c44 + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 off end # Parallel + device pnp 2e.2 off end # UART A + device pnp 2e.3 off end # UART B, IR + device pnp 2e.5 on # PS/2 Keyboard/Mouse + io 0x60 = 0x0060 + io 0x62 = 0x0064 + irq 0x70 = 1 # + Keyboard IRQ + irq 0x72 = 12 # + Mouse IRQ (unused) + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 on # GPIO8 + irq 0xe4 = 0xef # + GPIO8 direction + irq 0xe5 = 0 # + GPIO8 value + end + device pnp 2e.107 off end # GPIO9 + device pnp 2e.8 off end # WDT + device pnp 2e.108 off end # GPIO0 + device pnp 2e.208 on end # GPIOA + device pnp 2e.308 off end # GPIO base + device pnp 2e.109 on end # GPIO1 + device pnp 2e.209 on # GPIO2 + irq 0xe0 = 0xff # + GPIO2 direction + end + device pnp 2e.309 off end # GPIO3 + device pnp 2e.409 off end # GPIO4 + device pnp 2e.509 on # GPIO5 + irq 0xf4 = 0x7f # + GPIO5 direction + irq 0xf5 = 0x80 # + GPIO5 value + end + device pnp 2e.609 off end # GPIO6 + device pnp 2e.709 on end # GPIO7 + device pnp 2e.a on # ACPI + irq 0xe6 = 0x4c + irq 0xf0 = 0x40 + end + device pnp 2e.b on # HWM, LED + irq 0x30 = 0xe1 # + Fan RPM sense pins + io 0x60 = 0x0290 # + HWM base address + irq 0x70 = 0 + irq 0xf7 = 0 # + Front Panel Green LED + end + device pnp 2e.d off end # VID + device pnp 2e.e off end # CIR wake-up + device pnp 2e.f off end # GPIO PP/OD + device pnp 2e.14 off end # SVID + device pnp 2e.16 off end # Deep sleep + device pnp 2e.17 on # GPIOA + irq 0xe0 = 0 # + GPIOA direction + irq 0xe1 = 0 # + GPIOA value + end + end + end + device pci 1f.2 on # SATA Controller (AHCI) + subsystemid 0x1849 0x8c02 + end + device pci 1f.3 on # SMBus + subsystemid 0x1849 0x8c22 + end + device pci 1f.5 off end # SATA Controller (Legacy) + device pci 1f.6 off end # Thermal + end + end +end diff --git a/src/mainboard/asrock/z87e-itx/dsdt.asl b/src/mainboard/asrock/z87e-itx/dsdt.asl new file mode 100644 index 0000000..b62c922 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include <acpi/dsdt_top.asl> + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/common/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl> + #include <southbridge/intel/common/acpi/sleepstates.asl> + + Device (\_SB.PCI0) + { + #include <northbridge/intel/haswell/acpi/hostbridge.asl> + #include <southbridge/intel/lynxpoint/acpi/pch.asl> + } +} diff --git a/src/mainboard/asrock/z87e-itx/gma-mainboard.ads b/src/mainboard/asrock/z87e-itx/gma-mainboard.ads new file mode 100644 index 0000000..133fde5 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/gma-mainboard.ads @@ -0,0 +1,23 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + -- FIXME: check this + ports : constant Port_List := + (DP1, + DP2, + DP3, + HDMI1, + HDMI2, + HDMI3, + Analog, + LVDS, + eDP); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87e-itx/gpio.c b/src/mainboard/asrock/z87e-itx/gpio.c new file mode 100644 index 0000000..ff9a21d --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/gpio.c @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87e-itx/hda_verb.c b/src/mainboard/asrock/z87e-itx/hda_verb.c new file mode 100644 index 0000000..8a3c78f --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/hda_verb.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek */ + 0x18491150, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491150), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), + +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87e-itx/romstage.c b/src/mainboard/asrock/z87e-itx/romstage.c new file mode 100644 index 0000000..2887ccc --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/romstage.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <stdint.h> +#include <northbridge/intel/haswell/haswell.h> +#include <northbridge/intel/haswell/raminit.h> +#include <southbridge/intel/lynxpoint/pch.h> + +void mainboard_config_rcba(void) +{ +} + +/* FIXME: called after romstage_common, remove it if not used */ +void mb_late_romstage_setup(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + /* FIXME: check this */ + spdi->addresses[0] = 0x50; + spdi->addresses[1] = 0x51; + spdi->addresses[2] = 0x52; + spdi->addresses[3] = 0x53; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* FIXME: Length and Location are computed from IOBP values, may be inaccurate */ + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/81022?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I56c22d8f5505f9a4da25f8b4406b00978af1a586 Gerrit-Change-Number: 81022 Gerrit-PatchSet: 1 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: payload/external/edk2: Explicitly define the build arch
by Matt DeVillier (Code Review) 03 Mar '24

03 Mar '24

Attention is currently required from: Benjamin Doron, Lean Sheng Tan, Martin L Roth, Nicholas Sudsgaard, Sean Rhodes, Stefan Reinauer. Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80883?usp=email ) Change subject: payload/external/edk2: Explicitly define the build arch ...................................................................... Patch Set 2: Code-Review-1 (1 comment) Patchset: PS1: > Without this option, the EDK2 UefiPayloadPkg will not build. I'm not seeing that here on 4.22, 24.02, or main. Nor are there any build failures for jenkins. > One reason may be that it creates workspace/Build/UefiPayloadPkg$(BUILD_ARCH) (literally) no, it doesn't. it creates: payloads/external/edk2/workspace/Build/UefiPayloadPkgX64/RELEASE_COREBOOT/... payloads/external/edk2/workspace/<remote repo name>/<edk2 source tree>/ -- To view, visit https://review.coreboot.org/c/coreboot/+/80883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Gerrit-Change-Number: 80883 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sun, 03 Mar 2024 20:56:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Sean Rhodes <sean(a)starlabs.systems> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: lib/ramdetect: Limit probe size to function argument
by Philipp Hug (Code Review) 03 Mar '24

03 Mar '24

Attention is currently required from: Arthur Heymans, Maximilian Brune, Nico Huber. Philipp Hug has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68842?usp=email ) Change subject: lib/ramdetect: Limit probe size to function argument ...................................................................... Patch Set 10: (1 comment) File src/lib/ramdetect.c: https://review.coreboot.org/c/coreboot/+/68842/comment/35b51496_a2b0ab3d : PS7, Line 50: /* Find the MSB + 1. */ > I'd change it to a generic while loop, while keeping the if statement below. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/68842?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie7f915c6e150629eff235ee94719172467a54db2 Gerrit-Change-Number: 68842 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Sun, 03 Mar 2024 20:18:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Philipp Hug <philipp(a)hug.cx> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: payload/external/edk2: Explicitly define the build arch
by Sean Rhodes (Code Review) 03 Mar '24

03 Mar '24

Attention is currently required from: Benjamin Doron, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nicholas Sudsgaard, Stefan Reinauer. Sean Rhodes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80883?usp=email ) Change subject: payload/external/edk2: Explicitly define the build arch ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Without this option, the EDK2 UefiPayloadPkg will not build. […] This patch as is will cause problems with UPL (ignoring the build error for now). Not sure how/why you see this - I just tried in Docker and zero issues - can you post a verbose log? -- To view, visit https://review.coreboot.org/c/coreboot/+/80883?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icd942d0c15a99231d09f9cbdc5eb48333b6aa6e5 Gerrit-Change-Number: 80883 Gerrit-PatchSet: 2 Gerrit-Owner: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sun, 03 Mar 2024 19:30:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-MessageType: comment

1 0

[XS] Change in coreboot[main]: arch/x86/Kconfig: Deduplicate ARCH_SUPPORTS_CLANG selection
by Elyes Haouas (Code Review) 03 Mar '24

03 Mar '24

Attention is currently required from: Elyes Haouas, Jérémy Compostella. Hello Jérémy Compostella, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81020?usp=email to look at the new patch set (#2). Change subject: arch/x86/Kconfig: Deduplicate ARCH_SUPPORTS_CLANG selection ...................................................................... arch/x86/Kconfig: Deduplicate ARCH_SUPPORTS_CLANG selection Change-Id: Iced69e0bce345748a43eb1c14bf17a683e26ba60 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M src/arch/x86/Kconfig 1 file changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/81020/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iced69e0bce345748a43eb1c14bf17a683e26ba60 Gerrit-Change-Number: 81020 Gerrit-PatchSet: 2 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-MessageType: newpatchset

1 0

[XS] Change in coreboot[main]: Set x86_{32;64} as supported architecture for clang
by Felix Singer (Code Review) 03 Mar '24

03 Mar '24

Attention is currently required from: Elyes Haouas, Jérémy Compostella. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81020?usp=email ) Change subject: Set x86_{32;64} as supported architecture for clang ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81020/comment/fbb840cd_b9a99fa8 : PS1, Line 7: Set x86_{32;64} as supported architecture for clang This suggests that something new is introduced, while it is just a clean up. How about: ``` arch/x86/Kconfig: Deduplicate ARCH_SUPPORTS_CLANG selection ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/81020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iced69e0bce345748a43eb1c14bf17a683e26ba60 Gerrit-Change-Number: 81020 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Sun, 03 Mar 2024 18:53:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/brya: Create yavista variant
by Henry Sun (Code Review) 03 Mar '24

03 Mar '24

Attention is currently required from: Derek Huang, Eric Lai, Kapil Porwal, Nick Vaccaro, Paul Menzel, Rasheed Hsueh, Subrata Banik. Henry Sun has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80342?usp=email ) Change subject: mb/google/brya: Create yavista variant ...................................................................... Patch Set 5: Code-Review-1 (1 comment) Patchset: PS5: Hi Rash, Yavista should be under Nissa instead of Brya, please confirm or follow up. Thanks! -- To view, visit https://review.coreboot.org/c/coreboot/+/80342?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6fa464a4dcd9551a42e8746e64c724b3582dbe02 Gerrit-Change-Number: 80342 Gerrit-PatchSet: 5 Gerrit-Owner: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Henry Sun <henrysun(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Garen Wu <wu.garen(a)inventec.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Ryan Lin <ryan.lin(a)intel.corp-partner.google.com> Gerrit-CC: Steven Yeh <yeh.stevenct(a)inventec.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Derek Huang <derekhuang(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Rasheed Hsueh <hsueh.rasheed(a)inventec.corp-partner.google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sun, 03 Mar 2024 17:05:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2024