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Change subject: soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSION
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/soc/intel/common/block/cse/Kconfig:
https://review.coreboot.org/c/coreboot/+/80924/comment/f1a991cf_85fa281d :
PS1, Line 236: enabling automatic detection
Is there an option which lets the user to enable it explicitly or is it available implicit with Meteor Lake and newer?
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Change subject: soc/intel/cmn/cse: Use CSE RW partition version directly for CBFS entry
......................................................................
Patch Set 2: Code-Review+2
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Change subject: soc/intel/cmn/cse: Use CSE RW partition version directly for CBFS entry
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/cse/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/80923/comment/aaf86b41_099705a3 :
PS1, Line 101: $(eval $(word $(index),$(VERSIONS)) := $(shell printf "%d" 0x$(shell echo $(shell echo $(shell xxd -p $(TEMP_DATA)) | cut -c3-4)$(shell echo $(shell xxd -p $(TEMP_DATA)) | cut -c1-2))) )
> > > Does this still support version number parts that contains more than two digits? […]
OK, I misread the code. Indeed it just takes a 16 bit value (2 bytes) and prints it in decimal. Thanks for the link, looks good to me now.
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Change subject: nb/haswell: Disable iGPU when dGPU is used
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
Regarding the new patch set: I made it only disable VGA decode. But I have a question: what about nvidia optimus setups? T440p and W541 thinkpads sometimes have this, and in this setup, the Intel GPU should still be used for framebuffer. I have a hunch that this patch might break the display on those machines, when the nvidia gpu is enabled, because it would do vga decode on the nvidia gpu, even though it should only be used for render offloading on those setups.
A workaround might be to make the decode-disable only apply if broadwell mrc isn't used, but that isn't a real solution. Another solution would be to additionally make vga-decode-disable (the behaviour in this patch) a toggle in option table - in other words, let the user make it so that coreboot does not disable vga decode, to work around such quirky setups.
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Hello Angel Pons, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/80717?usp=email
to look at the new patch set (#3).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: nb/haswell: Disable iGPU when dGPU is used
......................................................................
nb/haswell: Disable iGPU when dGPU is used
This is usually is handled by Haswell mrc.bin, disabling VGA
decode on the iGPU when a dGPU is installed. However, Broadwell
mrc.bin does not, so the iGPU and dGPU are both enabled.
This patch disables legacy VGA cycles for iGPU, under such
conditions. It has been tested on Broadwell mrc.bin when
using a graphics card on Dell OptiPlex 9020 SFF (currently
under review at this time of writing, submitted by Mate
Kukri).
This patch has also been tested when Haswell mrc.bin is used,
and there are seemingly no breaking changes caused by it.
Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b
Signed-off-by: Leah Rowe <info(a)minifree.org>
---
M src/northbridge/intel/haswell/gma.c
1 file changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/80717/3
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Change subject: soc/intel/cmn/cse: Use CSE RW partition version directly for CBFS entry
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/common/block/cse/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/80923/comment/febd3f23_3ca099f1 :
PS1, Line 101: $(eval $(word $(index),$(VERSIONS)) := $(shell printf "%d" 0x$(shell echo $(shell echo $(shell xxd -p $(TEMP_DATA)) | cut -c3-4)$(shell echo $(shell xxd -p $(TEMP_DATA)) | cut -c1-2))) )
> > Does this still support version number parts that contains more than two digits?
> > Intel tends to use build numbers (last version entry) that are 4 digits long.
>
> This is as per the ME specification where CSE major/minor/hotfix/build all are 2 byte long.
may be https://winraid.level1techs.com/t/intel-cs-me-cs-txe-cs-sps-gsc-pmc-pchc-ph… link has some details about CSE version control for last several generations.
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Change subject: soc/intel/cmn/cse: Use CSE RW partition version directly for CBFS entry
......................................................................
Patch Set 2:
(2 comments)
File src/soc/intel/common/block/cse/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/80923/comment/3a4d3f4d_e0453a6a :
PS1, Line 101: $(eval $(word $(index),$(VERSIONS)) := $(shell printf "%d" 0x$(shell echo $(shell echo $(shell xxd -p $(TEMP_DATA)) | cut -c3-4)$(shell echo $(shell xxd -p $(TEMP_DATA)) | cut -c1-2))) )
> Does this still support version number parts that contains more than two digits?
> Intel tends to use build numbers (last version entry) that are 4 digits long.
This is as per the ME specification where CSE major/minor/hotfix/build all are 2 byte long.
https://review.coreboot.org/c/coreboot/+/80923/comment/ab1c94b5_3834b1f8 :
PS1, Line 103: TEMP_FILE
> Shouldn't this be TEMP_DATA? Or, if you insist on TEMP_FILE (which I find a better name), then you s […]
Acknowledged
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Change subject: soc/intel/cmn/cse: Use CSE RW partition version directly for CBFS entry
......................................................................
Patch Set 1:
(1 comment)
File src/soc/intel/common/block/cse/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/80923/comment/f6c2c5df_54bd3729 :
PS1, Line 101: $(eval $(word $(index),$(VERSIONS)) := $(shell printf "%d" 0x$(shell echo $(shell echo $(shell xxd -p $(TEMP_DATA)) | cut -c3-4)$(shell echo $(shell xxd -p $(TEMP_DATA)) | cut -c1-2))) )
Does this still support version number parts that contains more than two digits?
Intel tends to use build numbers (last version entry) that are 4 digits long.
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Change subject: soc/intel/cmn/cse: Use CSE RW partition version directly for CBFS entry
......................................................................
Patch Set 1: Code-Review+1
(1 comment)
File src/soc/intel/common/block/cse/Makefile.mk:
https://review.coreboot.org/c/coreboot/+/80923/comment/a79ce450_742ce9ee :
PS1, Line 103: TEMP_FILE
Shouldn't this be TEMP_DATA? Or, if you insist on TEMP_FILE (which I find a better name), then you should change it accordingly.
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