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Change subject: Revert "Revert "mb/sifive: Add Hifive Unmatched mainboard""
......................................................................
Patch Set 5: Code-Review+2
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/81052/comment/f24a31b5_00f3527b :
PS1, Line 7: Revert "Revert
> Change to "Reland"
Done
https://review.coreboot.org/c/coreboot/+/81052/comment/d3cce09f_9de4e485 :
PS1, Line 11: <reland>
> The commit that this commit relied on has now been merged.
Acknowledged
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Hello David Hendricks, Martin L Roth, Maximilian Brune, Philipp Hug, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81052?usp=email
to look at the new patch set (#5).
Change subject: Revert "Revert "mb/sifive: Add Hifive Unmatched mainboard""
......................................................................
Revert "Revert "mb/sifive: Add Hifive Unmatched mainboard""
This reverts commit ec7b48076009cfe82e5ee91050f5fc66c4850193.
Reason for revert: <Reland>
I made the commit out of order with the fu740 commit; that's now
merged so there should be no problem.
Signed-off-by: ron minnich <rminnich(a)gmail.com>
Change-Id: I2fb8c2e0a7fcd5f26f4a004e0949332b108b6fcf
---
A src/mainboard/sifive/hifive-unmatched/Kconfig
A src/mainboard/sifive/hifive-unmatched/Kconfig.name
A src/mainboard/sifive/hifive-unmatched/Makefile.inc
A src/mainboard/sifive/hifive-unmatched/board_info.txt
A src/mainboard/sifive/hifive-unmatched/cbfs_spi.c
A src/mainboard/sifive/hifive-unmatched/devicetree.cb
A src/mainboard/sifive/hifive-unmatched/fixup_fdt.c
A src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi
A src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts
A src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts
A src/mainboard/sifive/hifive-unmatched/mainboard.c
A src/mainboard/sifive/hifive-unmatched/romstage.c
12 files changed, 1,189 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/81052/5
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Hello David Hendricks, Martin L Roth, Maximilian Brune, Philipp Hug, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/81052?usp=email
to look at the new patch set (#4).
Change subject: Revert "Revert "mb/sifive: Add Hifive Unmatched mainboard""
......................................................................
Revert "Revert "mb/sifive: Add Hifive Unmatched mainboard""
This reverts commit ec7b48076009cfe82e5ee91050f5fc66c4850193.
Reason for revert: <reland>
I made the commit out of order with the fu740 commit; that's now
merged so there should be no problem.
Signed-off-by: ron minnich <rminnich(a)gmail.com>
Change-Id: I2fb8c2e0a7fcd5f26f4a004e0949332b108b6fcf
---
A src/mainboard/sifive/hifive-unmatched/Kconfig
A src/mainboard/sifive/hifive-unmatched/Kconfig.name
A src/mainboard/sifive/hifive-unmatched/Makefile.inc
A src/mainboard/sifive/hifive-unmatched/board_info.txt
A src/mainboard/sifive/hifive-unmatched/cbfs_spi.c
A src/mainboard/sifive/hifive-unmatched/devicetree.cb
A src/mainboard/sifive/hifive-unmatched/fixup_fdt.c
A src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi
A src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts
A src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts
A src/mainboard/sifive/hifive-unmatched/mainboard.c
A src/mainboard/sifive/hifive-unmatched/romstage.c
12 files changed, 1,189 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/81052/4
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Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81025?usp=email )
Change subject: ec/google/chromeec: Enclose Kconfig in 'if/endif' block
......................................................................
ec/google/chromeec: Enclose Kconfig in 'if/endif' block
Instead of having things depend on EC_GOOGLE_CHROMEEC, just put an if/
endif block around the configs.
The 'source' line stays outside of the if block because the source
always happens, even if it's inside an if/endif block. Each of the
sub-Kconfigs here already has an if/endif block surrounding the
contents.
Signed-off-by: Martin Roth <gaumless(a)gmail.com>
Change-Id: If88ba7d36ae04d879332037292c5cf9a3c8c3cab
---
M src/ec/google/chromeec/Kconfig
1 file changed, 7 insertions(+), 12 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/81025/1
diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig
index 3b0beda..19790d1 100644
--- a/src/ec/google/chromeec/Kconfig
+++ b/src/ec/google/chromeec/Kconfig
@@ -6,6 +6,8 @@
help
Google's Chrome EC
+if EC_GOOGLE_CHROMEEC
+
config EC_GOOGLE_CHROMEEC_ACPI_MEMMAP
depends on EC_GOOGLE_CHROMEEC_LPC
def_bool n
@@ -15,20 +17,17 @@
the LPC bus.
config EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER
- depends on EC_GOOGLE_CHROMEEC
def_bool n
help
Expose methods for enabling and disabling port power on individual USB
ports through the EC.
config EC_GOOGLE_CHROMEEC_BOARDID
- depends on EC_GOOGLE_CHROMEEC
def_bool n
help
Provides common routine for reading boardid from Chrome EC.
config EC_GOOGLE_CHROMEEC_I2C
- depends on EC_GOOGLE_CHROMEEC
bool
default n
help
@@ -51,7 +50,7 @@
Use only proto3 for i2c EC communication.
config EC_GOOGLE_CHROMEEC_ESPI
- depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play.
+ depends on ARCH_X86 # Needs Plug-and-play.
def_bool n
select EC_GOOGLE_CHROMEEC_LPC
help
@@ -62,7 +61,7 @@
still needs to correctly configure the bus transactions.
config EC_GOOGLE_CHROMEEC_LPC
- depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play.
+ depends on ARCH_X86 # Needs Plug-and-play.
def_bool n
help
Google Chrome EC via LPC bus.
@@ -75,13 +74,11 @@
Microchip EC variant for LPC register access.
config EC_GOOGLE_CHROMEEC_PD
- depends on EC_GOOGLE_CHROMEEC
def_bool n
help
Indicates that Google's Chrome USB PD chip is present.
config EC_GOOGLE_CHROMEEC_SPI
- depends on EC_GOOGLE_CHROMEEC
def_bool n
help
Google's Chrome EC via SPI bus.
@@ -108,7 +105,6 @@
Provides common routine for reporting the skuid to ChromeOS.
config EC_GOOGLE_CHROMEEC_BOARDNAME
- depends on EC_GOOGLE_CHROMEEC
string "Chrome EC board name for EC"
default ""
help
@@ -126,7 +122,6 @@
build the EC firmware and add it to the image.
config EC_GOOGLE_CHROMEEC_RTC
- depends on EC_GOOGLE_CHROMEEC
bool "Enable ChromeOS EC RTC"
help
Enable support for the real-time clock on the ChromeOS EC. This
@@ -134,7 +129,6 @@
choice
prompt "Chrome EC firmware source"
- depends on EC_GOOGLE_CHROMEEC
default EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN if EC_GOOGLE_CHROMEEC_BOARDNAME != ""
default EC_GOOGLE_CHROMEEC_FIRMWARE_NONE
@@ -193,7 +187,7 @@
The path and filename of the PD firmware file to use.
config EC_GOOGLE_CHROMEEC_SWITCHES
- depends on EC_GOOGLE_CHROMEEC && VBOOT
+ depends on VBOOT
bool
help
Enable support for ChromeOS mode switches provided by the ChromeOS
@@ -207,9 +201,10 @@
32 bits of firmware configuration.
config EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL
- depends on EC_GOOGLE_CHROMEEC
bool "Enable automatic fan control"
help
Put the fan in auto mode at boot.
+endif # EC_GOOGLE_CHROMEEC
+
source "src/ec/google/chromeec/*/Kconfig"
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Change subject: mb/dell: Add OptiPlex 7020/9020 port
......................................................................
Patch Set 33:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/55232/comment/4e89e3a7_cc60c740 :
PS33, Line 11: PWN
Typo: PWM
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Change subject: mb/dell: Add OptiPlex 7020/9020 port
......................................................................
Patch Set 33:
(1 comment)
Patchset:
PS32:
> edit, to be clear: mate knows of these issues but other readers don't. […]
Also:
the pwm issue doesn't affect safety on the default i3/i5 CPUs that come on these machines, but can be problematic when upgrading to a much hotter CPU. i have an i7-4790k (90w TDP!) in mine
i got it running stable, on sff, but airflow is quite inadequate by default. i replaced all the fans and i hardwire them to run at a higher speed, to get around the pwm issue
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Change subject: mb/dell: Add OptiPlex 7020/9020 port
......................................................................
Patch Set 33:
(4 comments)
File src/mainboard/dell/optiplex_9020/Kconfig:
https://review.coreboot.org/c/coreboot/+/55232/comment/69b3d83e_9fcd40fc :
PS32, Line 10: select HAVE_OPTION_TABLE
: select HAVE_CMOS_DEFAULT
> Swap these to keep the list in alphabetical order
Done
File src/mainboard/dell/optiplex_9020/board_info.txt:
https://review.coreboot.org/c/coreboot/+/55232/comment/bd45796b_9aaa584d :
PS32, Line 3: 2014
> Nit: The 9020 seems to have been released in 2013 and the 7020 in 2014
Done
File src/mainboard/dell/optiplex_9020/cmos.default:
PS32:
> Needs an SPDX header, refer to commit e623845df6 (mb/*: Add SPDX headers for cmos. […]
Done
File src/mainboard/dell/optiplex_9020/romstage.c:
https://review.coreboot.org/c/coreboot/+/55232/comment/9833b862_b84318dc :
PS32, Line 3: #include <northbridge/intel/haswell/haswell.h>
> This doesn't seem to be necessary. Seems to build fine if I remove it.
Done
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Change subject: mb/dell: Add OptiPlex 7020/9020 port
......................................................................
Patch Set 32:
(1 comment)
Patchset:
PS32:
> i saw that this was +2'd but there are two issues left to investigate: the PWM issue and the IOMMU i […]
edit, to be clear: mate knows of these issues but other readers don't. when you boot this board with a graphics card, you get corruption in xorg but the payload/TTYs etc still work. more testing needed - tested in debian 12.
and the pwm issue: fans remain at low speed even on 100% CPU usage and even when the system gets really hot. the mitigation for now is to hardwire fan speeds, to a higher speed, suitable for stress conditions.
probably better to mention about thermal performance/mods on sff, if using higher CPU like i7-4790k - the stock cooler can cool roughly 60-70w tdp only, but the system can take higher CPUs.
if these issues aren't fixed now, and the patch is merged, they can be fixed in later follow-up patches. none of them prevent reliable operation of the machine. but i think that if they aren't fixed before merge, they should be mentioned in documentation.
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