coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

1 participants
3668 discussions

[S] Change in coreboot[main]: soc/intel/xeon_sp/util: Enhance lock_pam0123
by Lean Sheng Tan (Code Review) 05 Mar '24

05 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80101?usp=email ) Change subject: soc/intel/xeon_sp/util: Enhance lock_pam0123 ...................................................................... soc/intel/xeon_sp/util: Enhance lock_pam0123 - Only compile code in ramstage - Lock PAM on all sockets - Instead of manually crafting S:B:D:F numbers for each PCI device search for the devices by PCI vendor and device ID. This adds PCI multi-segment support … [View More]without any further code modifications, since the correct PCI segment will be stored in the devicetree. Change-Id: Ic8b3bfee8f0d02790620280b30a9dc9a05da1be8 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80101 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> --- M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h M src/soc/intel/xeon_sp/util.c 4 files changed, 18 insertions(+), 13 deletions(-) Approvals: build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 614f42a..762e2e2 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -13,6 +13,7 @@ #define SAD_ALL_PAM0123_CSR 0x40 #define PAM_LOCK BIT(0) #define SAD_ALL_PAM456_CSR 0x44 +#define SAD_ALL_DEVID 0x344f #if !defined(__SIMPLE_DEVICE__) #define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 8b3c36c..ec52153 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -24,6 +24,7 @@ #define SAD_ALL_PAM0123_CSR 0x40 #define PAM_LOCK BIT(0) #define SAD_ALL_PAM456_CSR 0x44 +#define SAD_ALL_DEVID 0x2054 #if !defined(__SIMPLE_DEVICE__) #define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h index 1d7dedd..0ad5ea0 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h @@ -35,6 +35,7 @@ #define SAD_ALL_FUNC 0 #define SAD_ALL_PAM0123_CSR 0x80 #define SAD_ALL_PAM456_CSR 0x84 +#define SAD_ALL_DEVID 0x344f #if !defined(__SIMPLE_DEVICE__) #define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 7fc903a..956973e 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -17,19 +17,6 @@ #include <soc/util.h> #include <timer.h> -void lock_pam0123(void) -{ - if (get_lockdown_config() != CHIPSET_LOCKDOWN_COREBOOT) - return; - - /* section 16.3.19 of Intel doc. #612246 */ - uint32_t pam0123_lock = 0x33333331; - uint32_t bus1 = get_socket_ubox_busno(0); - - pci_s_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), - SAD_ALL_PAM0123_CSR, pam0123_lock); -} - void unlock_pam_regions(void) { uint32_t pam0123_unlock_dram = 0x33333330; @@ -121,6 +108,21 @@ } #if ENV_RAMSTAGE /* Setting devtree variables is only allowed in ramstage. */ + +void lock_pam0123(void) +{ + const uint32_t pam0123_lock = 0x33333331; + struct device *dev; + + if (get_lockdown_config() != CHIPSET_LOCKDOWN_COREBOOT) + return; + + dev = NULL; + /* Look for SAD_ALL devices on all sockets */ + while ((dev = dev_find_device(PCI_VID_INTEL, SAD_ALL_DEVID, dev))) + pci_write_config32(dev, SAD_ALL_PAM0123_CSR, pam0123_lock); +} + /* return true if command timed out else false */ static bool wait_for_bios_cmd_cpl(struct device *pcu1, uint32_t reg, uint32_t mask, uint32_t target) -- To view, visit https://review.coreboot.org/c/coreboot/+/80101?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic8b3bfee8f0d02790620280b30a9dc9a05da1be8 Gerrit-Change-Number: 80101 Gerrit-PatchSet: 12 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur.heymans(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged [View Less]

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add memory type check utils
by Lean Sheng Tan (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Jincheng Li, Johnny Lin, Nico Huber, Patrick Rudolph, Paul Menzel, Ray Ni, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80632?usp=email ) Change subject: soc/intel/xeon_sp: Add memory type check utils ...................................................................... Patch Set 9: Code-Review+1 -- To view, visit https://review.coreboot.… [View More]

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add memory type check utils
by Lean Sheng Tan (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Jincheng Li, Johnny Lin, Nico Huber, Patrick Rudolph, Ray Ni, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80632?usp=email ) Change subject: soc/intel/xeon_sp: Add memory type check utils ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/xeon_sp/spr/soc_util.c: https://… [View More]review.coreboot.org/c/coreboot/+/80632/comment/b9aab9b8_d285bf33 : PS6, Line 189: * vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h, > Done do you know when will it be uploaded? -- To view, visit https://review.coreboot.org/c/coreboot/+/80632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f5f3c0f16dc50bc739146e46afce2e5fbf4f62c Gerrit-Change-Number: 80632 Gerrit-PatchSet: 9 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 11:18:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment [View Less]

1 0

[XS] Change in coreboot[main]: soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SP
by Lean Sheng Tan (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Patrick Rudolph, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80634?usp=email ) Change subject: soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SP ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Patchset: PS2: > this pending for long time, can we move ahead to … [View More]

1 0

[S] Change in coreboot[main]: drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug
by Lean Sheng Tan (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Chen, Gang C, Christian Walter, Felix Singer, Jincheng Li, Johnny Lin, Jérémy Compostella, Nico Huber, Patrick Rudolph, Paul Menzel, Ray Ni, Ronak Kanabar, Shuo Liu, Tim Chu. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80579?usp=email ) Change subject: drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug ............................................................… [View More].......... Patch Set 6: Code-Review+2 (1 comment) Patchset: PS6: since it has been reviewed and tested, gave my +2 for this to move ahead if no further concerns. -- To view, visit https://review.coreboot.org/c/coreboot/+/80579?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4 Gerrit-Change-Number: 80579 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 11:16:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment [View Less]

1 0

[S] Change in coreboot[main]: drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug
by Shuo Liu (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Chen, Gang C, Christian Walter, Felix Singer, Jincheng Li, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Ray Ni, Ronak Kanabar, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80579?usp=email ) Change subject: drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug ............................................................… [View More].......... Patch Set 6: Code-Review+1 (4 comments) Patchset: PS6: done tests and can move ahead to merge now. File src/drivers/intel/fsp2_0/Kconfig: https://review.coreboot.org/c/coreboot/+/80579/comment/5b0c77ab_2713e941 : PS4, Line 227: there > s/there/the Done https://review.coreboot.org/c/coreboot/+/80579/comment/7c41fcc1_7297fb3b : PS4, Line 229: This code implicitly assumes that the top of FSP heap is FspStackBase + > suggest to update here as well for clarity. Done File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/80579/comment/cda59c91_3fb003ca : PS4, Line 175: extern char *_fspm_heap; > Need to use extern car _fspm_heap[] instead to make sure the symbol is instantiated as an immediate […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80579?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4 Gerrit-Change-Number: 80579 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 11:07:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: comment [View Less]

1 0

[M] Change in coreboot[main]: soc/intel/xeon_sp: Add memory type check utils
by Shuo Liu (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Jincheng Li, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Ray Ni, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80632?usp=email ) Change subject: soc/intel/xeon_sp: Add memory type check utils ...................................................................... Patch Set 9: (1 comment) Patchset: PS9: it's pending long, can we move ahead to … [View More]

1 0

[S] Change in coreboot[main]: drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug
by Shuo Liu (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Chen, Gang C, Christian Walter, Felix Singer, Jincheng Li, Johnny Lin, Jérémy Compostella, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Ray Ni, Ronak Kanabar, Shuo Liu, Tim Chu. Shuo Liu has uploaded a new patch set (#6) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/80579?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change … [View More]subject: drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug ...................................................................... drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug Starting with Intel CPX there is a bug in the reference code during the Pipe init. This code synchronises the CAR between sockets in FSP-M. This code implicitly assumes that the FSP heap is right above the RC heap, where both of them are located at the bottom part of CAR. Work around this issue by making that implicit assumption done in FSP explicit in the coreboot linker script and allocation. TEST=intel/archercity CRB Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4 --- M src/arch/x86/car.ld M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/memory_init.c M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/spr/Kconfig 5 files changed, 25 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/80579/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/80579?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4 Gerrit-Change-Number: 80579 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset [View Less]

1 0

[XS] Change in coreboot[main]: mb/google/corsola: Add registers reset for ALC5650
by Xuxin Xiong (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Hung-Te Lin, Yang Wu, Yidi Lin, Yu-Ping Wu. Xuxin Xiong has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81077?usp=email ) Change subject: mb/google/corsola: Add registers reset for ALC5650 ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/81077?usp=email To unsubscribe, or for help writing mail filters, visit … [View More]

1 0

[S] Change in coreboot[main]: lib/program.ld: Make (NOLOAD) and to_load more explicit
by Maximilian Brune (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Nico Huber. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80803?usp=email ) Change subject: lib/program.ld: Make (NOLOAD) and to_load more explicit ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80803?usp=email To unsubscribe, or for help writing mail filters, visit https://… [View More]

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2024