coreboot-gerrit March 2024

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SP
by Shuo Liu (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Patrick Rudolph, Tim Chu. Hello Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80634?usp=email to look at the new patch set (#3). Change subject: soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SP ...................................................................... soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SP Move MEM_ADDR_64MB_SHIFT_BITS from FSP headers to Xeon-SP common layer to reduce the dependency. TEST=intel/archercity CRB Change-Id: I4e1a652ad58233f7514cb9b23813d75144b8d435 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/include/soc/util.h M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h M src/vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/defs_memmap.h M src/vendorcode/intel/fsp/fsp2_0/skylake_sp/hob_memmap.h 4 files changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/80634/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/80634?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e1a652ad58233f7514cb9b23813d75144b8d435 Gerrit-Change-Number: 80634 Gerrit-PatchSet: 3 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SP
by Shuo Liu (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80634?usp=email ) Change subject: soc/intel/xeon_sp: Move MEM_ADDR_64MB_SHIFT_BITS to Xeon-SP ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: this pending for long time, can we move ahead to merge? -- To view, visit https://review.coreboot.org/c/coreboot/+/80634?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4e1a652ad58233f7514cb9b23813d75144b8d435 Gerrit-Change-Number: 80634 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 10:28:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSION
by Subrata Banik (Code Review) 05 Mar '24

05 Mar '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80924?usp=email ) Change subject: soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSION ...................................................................... soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSION This patch marks CONFIG_SOC_INTEL_CSE_RW_VERSION as deprecated, as future platforms will automatically determine the CSE RW version using CSE RW partition. BUG=b:327842062 TEST=CSE RW update successful on Screebo. Change-Id: I8c3e5c759e4d9a43c3bce3a0c032086f17592a67 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80924 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/soc/intel/common/block/cse/Kconfig 1 file changed, 5 insertions(+), 1 deletion(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Dinesh Gehlot: Looks good to me, approved Werner Zeh: Looks good to me, approved Kapil Porwal: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 4f585c0..b0524ea 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -226,13 +226,17 @@ Intel CSE CBFS RW blob path and file name config SOC_INTEL_CSE_RW_VERSION - string "Intel CSE RW firmware version" if SOC_INTEL_CSE_RW_UPDATE + string "Intel CSE RW firmware version (deprecated)" if SOC_INTEL_CSE_RW_UPDATE default "" help This config contains the Intel CSE RW version of the blob that is provided by SOC_INTEL_CSE_RW_FILE config and the version must be set in the format major.minor.hotfix.build (ex: 14.0.40.1209). + This config may be deprecated in the future. Consider not providing the CSE RW + firmware version here and let the CSE version be automatically queried from the CSE + binary at build time (available with Meteor Lake and following platforms). + config SOC_INTEL_CSE_SET_EOP bool default n -- To view, visit https://review.coreboot.org/c/coreboot/+/80924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c3e5c759e4d9a43c3bce3a0c032086f17592a67 Gerrit-Change-Number: 80924 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection
by Subrata Banik (Code Review) 05 Mar '24

05 Mar '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80738?usp=email ) Change subject: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection ...................................................................... vc/google/chromeos: Implement dynamic ChromeOS boot logo selection * Introduces logic to display context-specific boot splash logos. * Logo selection considers: * Chromebook-Plus hardware compliance (using factory_config). * VPD-based product segmentation (soft-branded vs. regular chromebook). * Default Chromebook logo as fallback for regular Chromebook. This patch fixes the problem where existing logic was unable to pick correct ChromeOS boot splash logo based on the product segmentation. Relation between product segment and boot splash screen: 1. Chromebook-Plus Hard-branded device: Renders "cb_plus_logo.bmp" logo 2. Chromebook-Plus Soft-branded device: Renders "cb_plus_logo.bmp" logo 3. Regular Chromebook device: Renders "cb_logo.bmp" BUG=b:324107408 TEST=Verified logo selection based on compliance and product requirements. Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80738 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/vendorcode/google/chromeos/chromeos.h M src/vendorcode/google/chromeos/splash.c M src/vendorcode/google/chromeos/tpm_factory_config.c 3 files changed, 37 insertions(+), 14 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index a4315c3..540f363 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -35,17 +35,28 @@ */ uint64_t chromeos_get_factory_config(void); /* - * Determines whether a ChromeOS device is branded as a Chromebook Plus + * Determines whether a ChromeOS device is branded as a Chromebook-Plus * based on specific bit flags: * * - Bit 4 (0x10): Indicates whether the device chassis has the * "chromebook-plus" branding. - * - Bits 3-0 (0x1): Must be 0x1 to signify compliance with Chromebook Plus + * - Bits 3-0 (0x1): Must be 0x1 to signify compliance with Chromebook-Plus * hardware specifications. * - * To be considered a Chromebook Plus, either of these conditions needs to be met. + * To be considered a Chromebook-Plus, both of these conditions need to be met. */ -bool chromeos_device_branded_plus(void); +bool chromeos_device_branded_plus_hard(void); + +/* + * Determines whether a ChromeOS device is soft-branded as a Chromebook-Plus + * after meeting below conditions: + * + * - Device is compliant to the Chromebook-Plus Hardware Specification. + * - Business decision makes this device qualified as Chromebook-Plus. + * + * To be considered a soft-branded Chromebook-Plus, both of these conditions need to be met. + */ +bool chromeos_device_branded_plus_soft(void); /* * Declaration for mainboards to use to generate ACPI-specific ChromeOS needs. diff --git a/src/vendorcode/google/chromeos/splash.c b/src/vendorcode/google/chromeos/splash.c index 3532fb8..f63f526 100644 --- a/src/vendorcode/google/chromeos/splash.c +++ b/src/vendorcode/google/chromeos/splash.c @@ -5,7 +5,9 @@ const char *bmp_logo_filename(void) { - if (chromeos_device_branded_plus()) + if (chromeos_device_branded_plus_hard()) + return "cb_plus_logo.bmp"; + else if (chromeos_device_branded_plus_soft()) return "cb_plus_logo.bmp"; else return "cb_logo.bmp"; diff --git a/src/vendorcode/google/chromeos/tpm_factory_config.c b/src/vendorcode/google/chromeos/tpm_factory_config.c index 44fb9f0..5ce0862 100644 --- a/src/vendorcode/google/chromeos/tpm_factory_config.c +++ b/src/vendorcode/google/chromeos/tpm_factory_config.c @@ -2,13 +2,12 @@ #include <assert.h> #include <console/console.h> +#include <drivers/vpd/vpd.h> #include <security/tpm/tss.h> #include <types.h> #include <vendorcode/google/chromeos/chromeos.h> #define CHROMEBOOK_PLUS_HARD_BRANDED BIT(4) -#define CHROMEBOOK_PLUS_SOFT_BRANDED BIT(0) -#define CHROMEBOOK_PLUS_DEVICE (CHROMEBOOK_PLUS_HARD_BRANDED | CHROMEBOOK_PLUS_SOFT_BRANDED) uint64_t chromeos_get_factory_config(void) { @@ -39,22 +38,33 @@ } /* - * Determines whether a ChromeOS device is branded as a Chromebook Plus + * Determines whether a ChromeOS device is branded as a Chromebook-Plus * based on specific bit flags: * * - Bit 4 (0x10): Indicates whether the device chassis has the * "chromebook-plus" branding. - * - Bits 3-0 (0x1): Must be 0x1 to signify compliance with Chromebook Plus - * hardware specifications. - * - * To be considered a Chromebook Plus, either of these conditions needs to be met. */ -bool chromeos_device_branded_plus(void) +bool chromeos_device_branded_plus_hard(void) { uint64_t factory_config = chromeos_get_factory_config(); if (factory_config == UNDEFINED_FACTORY_CONFIG) return false; - return factory_config & CHROMEBOOK_PLUS_DEVICE; + return (factory_config & CHROMEBOOK_PLUS_HARD_BRANDED) == CHROMEBOOK_PLUS_HARD_BRANDED; +} + +/* + * Use 'feature_level' populated by ChromeOS libsegmentation library to know if the device + * is a chromebook plus or not. + * + * Note: After powerwash or dev/normal mode switch, the splash screen may be incorrect + * on first boot until VPD is updated. + */ +bool chromeos_device_branded_plus_soft(void) +{ + if (vpd_get_feature_level() > 1) + return true; + + return false; } -- To view, visit https://review.coreboot.org/c/coreboot/+/80738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b Gerrit-Change-Number: 80738 Gerrit-PatchSet: 13 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: drivers/vpd: Add vpd_get_feature_level() API
by Subrata Banik (Code Review) 05 Mar '24

05 Mar '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80805?usp=email ) Change subject: drivers/vpd: Add vpd_get_feature_level() API ...................................................................... drivers/vpd: Add vpd_get_feature_level() API This patch introduces the vpd_get_feature_level() API to specifically extract the "feature_level" field from the "feature_device_info" VPD key. This is used to distinguish between Chromebook-Plus and regular Chromebook devices. The previous vpd_get_feature_device_info() API is removed as vpd_get_feature_level() is enough to find VPD and extract the data. Note: The new API decodes the base64-encoded "feature_device_info" VPD data. BUG=b:324107408 TEST=Able to build and boot google/rex0. Change-Id: I76fc220ed792abdfefb0b1a37873b5b828bfdda8 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80805 Reviewed-by: Gwendal Grignou <gwendal(a)chromium.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Dinesh Gehlot <digehlot(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/drivers/vpd/vpd.h M src/drivers/vpd/vpd_device_feature.c 2 files changed, 33 insertions(+), 9 deletions(-) Approvals: Kapil Porwal: Looks good to me, approved Dinesh Gehlot: Looks good to me, approved Eric Lai: Looks good to me, approved Gwendal Grignou: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index a23005f..a6631aa 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -60,8 +60,9 @@ bool vpd_get_int(const char *key, enum vpd_region region, int *val); /* - * Return the value after reading the VPD key named "feature_device_info". + * Extracts the "feature_level" from the "feature_device_info" VPD key. + * This key holds a base64-encoded protobuf where "feature_level" is the first entry. */ -const char *vpd_get_feature_device_info(void); +uint8_t vpd_get_feature_level(void); #endif /* __VPD_H__ */ diff --git a/src/drivers/vpd/vpd_device_feature.c b/src/drivers/vpd/vpd_device_feature.c index 1c8682a..7b92756 100644 --- a/src/drivers/vpd/vpd_device_feature.c +++ b/src/drivers/vpd/vpd_device_feature.c @@ -1,15 +1,38 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <b64_decode.h> +#include <console/console.h> #include <drivers/vpd/vpd.h> +#include <stdlib.h> #define VPD_KEY_FEATURE_DEVICE_INFO "feature_device_info" -#define VPD_FEATURE_DEVICE_INFO_LEN 64 -const char *vpd_get_feature_device_info(void) +/* + * Extracts the "feature_level" from the "feature_device_info" VPD key. + * This key holds a base64-encoded protobuf where "feature_level" is the first entry. + */ +uint8_t vpd_get_feature_level(void) { - static char device_info[VPD_FEATURE_DEVICE_INFO_LEN]; - if (vpd_gets(VPD_KEY_FEATURE_DEVICE_INFO, device_info, VPD_FEATURE_DEVICE_INFO_LEN, - VPD_RW)) - return device_info; - return ""; + const uint8_t *device_info; + int device_info_size, feature_level = 0; + uint8_t *decoded_device_info; + size_t decoded_size; + + device_info = vpd_find(VPD_KEY_FEATURE_DEVICE_INFO, &device_info_size, VPD_RW); + if (!device_info) + return feature_level; + + decoded_size = B64_DECODED_SIZE(device_info_size); + decoded_device_info = malloc(decoded_size); + if (!decoded_device_info) { + printk(BIOS_ERR, "%s: failed allocating %zd bytes\n", __func__, decoded_size); + return feature_level; + } + + /* The index 1 of the decoded data is the "feature level" value */ + if (b64_decode(device_info, device_info_size, decoded_device_info)) + feature_level = decoded_device_info[1]; + + free(decoded_device_info); + return feature_level; } -- To view, visit https://review.coreboot.org/c/coreboot/+/80805?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I76fc220ed792abdfefb0b1a37873b5b828bfdda8 Gerrit-Change-Number: 80805 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platforms
by Shuo Liu (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81041?usp=email ) Change subject: soc/intel/xeon_sp: Unshare UDK binding among Xeon-SP platforms ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81041/comment/556504f9_88b1a9a4 : PS2, Line 7: Unshare UDK binding among Xeon-SP platforms > To support newer platforms? Right. -- To view, visit https://review.coreboot.org/c/coreboot/+/81041?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I285549daad87fe1ad6e8a94853e0a92cd5930e04 Gerrit-Change-Number: 81041 Gerrit-PatchSet: 2 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 10:15:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/corsola: Add registers reset for ALC5650
by Yang Wu (Code Review) 05 Mar '24

05 Mar '24

Yang Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81077?usp=email ) Change subject: mb/google/corsola: Add registers reset for ALC5650 ...................................................................... mb/google/corsola: Add registers reset for ALC5650 The power of codec isn't dropped down when cold reboot on corsola, so in devbeep sences, the first beep will be loudly due to codec may not have been initialized. Therefore, we reset codec registers in configure_alc5645(). BRANCH=corsola BUG=b:323606238 TEST=Verify devbeep in depthcharge Change-Id: I8f74f0b95f20bdcf81a5e1c605e841caa0e0fb1a Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/mainboard.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/81077/1 diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index a1ba5f9..1eff98b 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -3,6 +3,7 @@ #include <bootmode.h> #include <console/console.h> #include <device/device.h> +#include <device/i2c_simple.h> #include <fw_config.h> #include <gpio.h> #include <soc/bl31.h> @@ -38,6 +39,9 @@ /* Init I2C bus timing register for audio codecs */ mtk_i2c_bus_init(I2C5, I2C_SPEED_STANDARD); + + /* Reset the codec/regs */ + i2c_write_field(I2C5, 0x1a, 0x00, 0x00, 0xFF, 0); } static void mainboard_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/81077?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8f74f0b95f20bdcf81a5e1c605e841caa0e0fb1a Gerrit-Change-Number: 81077 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: mb/google/corsola: Add registers reset for ALC5650
by Yang Wu (Code Review) 05 Mar '24

05 Mar '24

Yang Wu has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/81076?usp=email ) Change subject: mb/google/corsola: Add registers reset for ALC5650 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/81076?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f74f0b95f20bdcf81a5e1c605e841caa0e0fb1a Gerrit-Change-Number: 81076 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[master]: mb/google/corsola: Add registers reset for ALC5650
by Yang Wu (Code Review) 05 Mar '24

05 Mar '24

Yang Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81076?usp=email ) Change subject: mb/google/corsola: Add registers reset for ALC5650 ...................................................................... mb/google/corsola: Add registers reset for ALC5650 The power of codec isn't dropped down when cold reboot on corsola, so in devbeep sences, the first beep will be loudly due to codec may not have been initialized. Therefore, we reset codec registers in configure_alc5645(). BRANCH=corsola BUG=b:323606238 TEST=Verify devbeep in depthcharge Change-Id: I8f74f0b95f20bdcf81a5e1c605e841caa0e0fb1a Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/corsola/mainboard.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/81076/1 diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index a1ba5f9..1eff98b 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -3,6 +3,7 @@ #include <bootmode.h> #include <console/console.h> #include <device/device.h> +#include <device/i2c_simple.h> #include <fw_config.h> #include <gpio.h> #include <soc/bl31.h> @@ -38,6 +39,9 @@ /* Init I2C bus timing register for audio codecs */ mtk_i2c_bus_init(I2C5, I2C_SPEED_STANDARD); + + /* Reset the codec/regs */ + i2c_write_field(I2C5, 0x1a, 0x00, 0x00, 0xFF, 0); } static void mainboard_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/81076?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f74f0b95f20bdcf81a5e1c605e841caa0e0fb1a Gerrit-Change-Number: 81076 Gerrit-PatchSet: 1 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection
by Dinesh Gehlot (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Gwendal Grignou, Paul Menzel, Paz Zcharya, Subrata Banik. Dinesh Gehlot has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80738?usp=email ) Change subject: vc/google/chromeos: Implement dynamic ChromeOS boot logo selection ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bb1e868764738333977bd8c990bea4253c9d37b Gerrit-Change-Number: 80738 Gerrit-PatchSet: 12 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Paz Zcharya <pazz(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paz Zcharya <pazz(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Gwendal Grignou <gwendal(a)chromium.org> Gerrit-Comment-Date: Tue, 05 Mar 2024 09:43:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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