coreboot-gerrit March 2024

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Rewrite acpi_create_satc
by Arthur Heymans (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, Tim Chu. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81049?usp=email ) Change subject: soc/intel/xeon_sp: Rewrite acpi_create_satc ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81049?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1dfc56ccf279b77cfab4ae3457aa8799d2d57a34 Gerrit-Change-Number: 81049 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 08:02:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Rewrite acpi_create_satc
by Shuo Liu (Code Review) 05 Mar '24

05 Mar '24

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Rewrite acpi_create_drhd
by Shuo Liu (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81048?usp=email ) Change subject: soc/intel/xeon_sp: Rewrite acpi_create_drhd ...................................................................... soc/intel/xeon_sp: Rewrite acpi_create_drhd Change-Id: Idcfa899c764ffe51db5ed202ead07ad7b6868864 Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/uncore_acpi.c 1 file changed, 91 insertions(+), 76 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/81048/1 diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index b7c6640..1ae6a1f 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -248,77 +248,76 @@ return (atsr_size + pci_br_size); } -static unsigned long acpi_create_drhd(unsigned long current, int socket, - int stack, const IIO_UDS *hob) +static unsigned long acpi_create_drhd(unsigned long current, int socket, const IIO_UDS *hob) { + struct device *domain, *dev = NULL; + struct device *iommu0 = NULL; + struct resource *resource; unsigned long tmp = current; - const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; - const uint32_t bus = ri->BusBase; - const uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; - const uint32_t reg_base = ri->VtdBarAddress; - printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", - __func__, socket, stack, bus, pcie_seg, reg_base); + int pcie_seg, stack, bus, bus_range; + uint32_t reg_base; - /* Do not generate DRHD for non-PCIe stack */ - if (!reg_base) - return current; + while ((dev = dev_find_device(PCI_VID_INTEL, MMAP_VTD_CFG_REG_DEVID, dev))) { + /* Only add devices for the current socket */ + if (iio_pci_domain_socket_from_dev(dev) != socket) + continue; - // Add DRHD Hardware Unit + /* See if there is a resource with the appropriate index. */ + resource = probe_resource(dev, VTD_BAR_CSR); + if (!resource) + continue; + reg_base = (uint32_t) resource->base; - if (socket == 0 && stack == IioStack0) { - printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " - "Register Base Address: 0x%x\n", - DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); - current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, - pcie_seg, reg_base); - } else { + /* Leave IOMMU0 handling to the latest */ + stack = iio_pci_domain_stack_from_dev(dev); + domain = dev_get_pci_domain(dev); + if (!domain) + continue; + pcie_seg = domain_to_pcie_segment_group(domain); + bus = domain->downstream->secondary; + bus_range = domain->downstream->max_subordinate - bus; + if (socket == 0 && stack == IioStack0) { + iommu0 = dev; + continue; + } + + // Add DRHD Hardware Unit printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); - } - // Add PCH IOAPIC - if (socket == 0 && stack == IioStack0) { - union p2sb_bdf ioapic_bdf = p2sb_get_ioapic_bdf(); - printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", get_ioapic_id(IO_APIC_ADDR), ioapic_bdf.bus, - ioapic_bdf.dev, ioapic_bdf.fn); - current += acpi_create_dmar_ds_ioapic_from_hw(current, - IO_APIC_ADDR, ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); - } - -/* SPR has no per stack IOAPIC or CBDMA devices */ + /* SPR has no per stack IOAPIC or CBDMA devices */ #if CONFIG(SOC_INTEL_SKYLAKE_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP) - uint32_t enum_id; - // Add IOAPIC entry - enum_id = soc_get_iio_ioapicid(socket, stack); - printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); - current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, - APIC_DEV_NUM, APIC_FUNC_NUM); + uint32_t enum_id; + // Add IOAPIC entry + enum_id = soc_get_iio_ioapicid(socket, stack); + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, + APIC_DEV_NUM, APIC_FUNC_NUM); - // Add CBDMA devices for CSTACK - if (socket != 0 && stack == CSTACK) { - for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { - printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " - "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, CBDMA_DEV_NUM, cbdma_func_id); - current += acpi_create_dmar_ds_pci(current, - bus, CBDMA_DEV_NUM, cbdma_func_id); + // Add CBDMA devices for CSTACK + if (socket != 0 && stack == CSTACK) { + for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, CBDMA_DEV_NUM, cbdma_func_id); + current += acpi_create_dmar_ds_pci(current, + bus, CBDMA_DEV_NUM, cbdma_func_id); + } } - } #endif - // Add PCIe Ports - if (socket != 0 || stack != IioStack0) { - struct device *dev = pcidev_path_on_bus(bus, PCI_DEVFN(0, 0)); - while (dev) { - if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) + // Add PCIe Ports + struct device *dev1; + dev1 = pcidev_path_on_bus(bus, PCI_DEVFN(0, 0)); + while (dev1) { + if ((dev1->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) current += acpi_create_dmar_ds_pci_br_for_port( - current, dev, pcie_seg, false, NULL); + current, dev1, pcie_seg, false, NULL); - dev = dev->sibling; + dev1 = dev1->sibling; } #if CONFIG(SOC_INTEL_SKYLAKE_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP) @@ -332,32 +331,49 @@ bus, VMD_DEV_NUM, VMD_FUNC_NUM); } #endif - } - // Add IOAT End Points (with memory resources. We don't report every End Point device.) - if (CONFIG(HAVE_IOAT_DOMAINS) && is_ioat_iio_stack_res(ri)) { - for (int b = ri->BusBase; b <= ri->BusLimit; ++b) { - struct device *dev = pcidev_path_on_bus(b, PCI_DEVFN(0, 0)); - while (dev) { - /* This may also require a check for IORESOURCE_PREFETCH, - * but that would not include the FPU (4942/0) */ - if ((dev->resource_list->flags & - (IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED)) == - (IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED)) { - const uint32_t d = PCI_SLOT(dev->path.pci.devfn); - const uint32_t f = PCI_FUNC(dev->path.pci.devfn); - printk(BIOS_DEBUG, " [PCIE Endpoint Device] " - "Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " - " PCI Path: 0x%x, 0x%x\n", 0, b, d, f); - current += acpi_create_dmar_ds_pci(current, b, d, f); + // Add IOAT End Points (with memory resources. We don't report every End Point device.) + if (CONFIG(HAVE_IOAT_DOMAINS) && is_dev_on_ioat_domain(domain)) { + for (int b = bus; b <= bus + bus_range; ++b) { + struct device *dev2; + dev2 = pcidev_path_on_bus(b, PCI_DEVFN(0, 0)); + while (dev1) { + /* This may also require a check for IORESOURCE_PREFETCH, + * but that would not include the FPU (4942/0) */ + if ((dev2->resource_list->flags & + (IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED)) == + (IORESOURCE_MEM | IORESOURCE_PCI64 | IORESOURCE_ASSIGNED)) { + const uint32_t d = PCI_SLOT(dev2->path.pci.devfn); + const uint32_t f = PCI_FUNC(dev2->path.pci.devfn); + printk(BIOS_DEBUG, " [PCIE Endpoint Device] " + "Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + " PCI Path: 0x%x, 0x%x\n", 0, b, d, f); + current += acpi_create_dmar_ds_pci(current, b, d, f); + } + dev2 = dev2->sibling; } - dev = dev->sibling; } } + } - // Add HPET - if (socket == 0 && stack == IioStack0) { + /* Handle IOMMU0 */ + if (iommu0) { + // Add DRHD Hardware Unit + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", + DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + pcie_seg, reg_base); + + // Add PCH IOAPIC + union p2sb_bdf ioapic_bdf = p2sb_get_ioapic_bdf(); + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", get_ioapic_id(IO_APIC_ADDR), ioapic_bdf.bus, + ioapic_bdf.dev, ioapic_bdf.fn); + current += acpi_create_dmar_ds_ioapic_from_hw(current, + IO_APIC_ADDR, ioapic_bdf.bus, ioapic_bdf.dev, ioapic_bdf.fn); + uint16_t hpet_capid = read16p(HPET_BASE_ADDRESS); uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", @@ -544,8 +560,7 @@ for (int socket = (CONFIG_MAX_SOCKET - 1); socket >= 0; --socket) { if (!soc_cpu_is_enabled(socket)) continue; - for (int stack = (MAX_LOGIC_IIO_STACK - 1); stack >= 0; --stack) - current = acpi_create_drhd(current, socket, stack, hob); + current = acpi_create_drhd(current, socket, hob); } // RMRR -- To view, visit https://review.coreboot.org/c/coreboot/+/81048?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idcfa899c764ffe51db5ed202ead07ad7b6868864 Gerrit-Change-Number: 81048 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Add domain_to_pcie_segment_group
by Shuo Liu (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Hello Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/81047?usp=email to review the following change. Change subject: soc/intel/xeon_sp: Add domain_to_pcie_segment_group ...................................................................... soc/intel/xeon_sp: Add domain_to_pcie_segment_group Change-Id: Ie9626c125a2ea07fab7be2b2dbe922a3574dc3bf Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/81047/1 diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index f89532d..73978c9 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -316,3 +316,13 @@ return false; } +int domain_to_pcie_segment_group(const struct device *dev) +{ + assert(dev->path.type == DEVICE_PATH_DOMAIN); + const union xeon_domain_path dn = { + .domain_path = dev->path.domain.domain + }; + const IIO_UDS *hob = get_iio_uds(); + assert(hob != NULL); + return hob->PlatformData.CpuQpiInfo[dn.socket].PcieSegment; +} diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 683df03..33980a7 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -44,4 +44,6 @@ bool is_dev_on_ioat_domain(struct device *dev); bool is_dev_on_ubox_domain(struct device *dev); +int domain_to_pcie_segment_group(const struct device *dev); + #endif /* _CHIP_COMMON_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81047?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9626c125a2ea07fab7be2b2dbe922a3574dc3bf Gerrit-Change-Number: 81047 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add is_dev_on_pcie/ubox/ioat_domain
by Shuo Liu (Code Review) 05 Mar '24

05 Mar '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81046?usp=email ) Change subject: soc/intel/xeon_sp: Add is_dev_on_pcie/ubox/ioat_domain ...................................................................... soc/intel/xeon_sp: Add is_dev_on_pcie/ubox/ioat_domain Change-Id: I6b31c29564c774c27e86f55749ca9eca057a0cfe Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/include/soc/chip_common.h 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/81046/1 diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 03ae70a..f89532d 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -268,3 +268,51 @@ } } } + +bool is_dev_on_pcie_domain(struct device *dev) +{ + struct device *domain; + domain = dev_get_pci_domain(dev); + + if ((!domain) || (!domain->name)) + return false; + + if (strstr(domain->name, DOMAIN_TYPE_PCIE)) + return true; + + return false; +} + +bool is_dev_on_ubox_domain(struct device *dev) +{ + struct device *domain; + domain = dev_get_pci_domain(dev); + + if ((!domain) || (!domain->name)) + return false; + + if (strstr(domain->name, DOMAIN_TYPE_UBX0) || + strstr(domain->name, DOMAIN_TYPE_UBX1)) + return true; + + return false; +} + +bool is_dev_on_ioat_domain(struct device *dev) +{ + struct device *domain; + domain = dev_get_pci_domain(dev); + + if ((!domain) || (!domain->name)) + return false; + + if (strstr(domain->name, DOMAIN_TYPE_CPM0) || + strstr(domain->name, DOMAIN_TYPE_CPM1) || + strstr(domain->name, DOMAIN_TYPE_DINO) || + strstr(domain->name, DOMAIN_TYPE_HQM0) || + strstr(domain->name, DOMAIN_TYPE_HQM1)) + return true; + + return false; +} + diff --git a/src/soc/intel/xeon_sp/include/soc/chip_common.h b/src/soc/intel/xeon_sp/include/soc/chip_common.h index 03bceb5..683df03 100644 --- a/src/soc/intel/xeon_sp/include/soc/chip_common.h +++ b/src/soc/intel/xeon_sp/include/soc/chip_common.h @@ -40,4 +40,8 @@ int iio_pci_domain_socket_from_dev(struct device *dev); int iio_pci_domain_stack_from_dev(struct device *dev); +bool is_dev_on_pcie_domain(struct device *dev); +bool is_dev_on_ioat_domain(struct device *dev); +bool is_dev_on_ubox_domain(struct device *dev); + #endif /* _CHIP_COMMON_H_ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/81046?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6b31c29564c774c27e86f55749ca9eca057a0cfe Gerrit-Change-Number: 81046 Gerrit-PatchSet: 1 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: vc/intel/fsp/twinlake: Add FspProducerDataHeader.h header
by V Sowmya (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Ronak Kanabar. V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81037?usp=email ) Change subject: vc/intel/fsp/twinlake: Add FspProducerDataHeader.h header ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81037?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie33c681676d2a699b7aec8185dbdb90555ef8fe2 Gerrit-Change-Number: 81037 Gerrit-PatchSet: 2 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 07:59:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSION
by Werner Zeh (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Nick Vaccaro, Subrata Banik. Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80924?usp=email ) Change subject: soc/intel/cmn/cse: Deprecate CONFIG_SOC_INTEL_CSE_RW_VERSION ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8c3e5c759e4d9a43c3bce3a0c032086f17592a67 Gerrit-Change-Number: 80924 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 07:18:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: amdfwtool: Set the table size for L1 separately
by Bao Zheng (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Felix Held, Martin Roth, Nikolai Vyssotski, Zheng Bao. Hello Felix Held, Martin Roth, Nikolai Vyssotski, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78274?usp=email to look at the new patch set (#14). Change subject: amdfwtool: Set the table size for L1 separately ...................................................................... amdfwtool: Set the table size for L1 separately The space defined by size of the L1 table can not overlap with ISH header. For other cases, the size defines the directory and its content. The PSP spec does not say it quite clearly. This change is partly based on guess and can make extraction tool work so far. Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 23 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/78274/14 -- To view, visit https://review.coreboot.org/c/coreboot/+/78274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289 Gerrit-Change-Number: 78274 Gerrit-PatchSet: 14 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: amdfwtool: Set the table size for L1 separately
by Bao Zheng (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Felix Held, Martin Roth, Nikolai Vyssotski, Zheng Bao. Hello Felix Held, Martin Roth, Nikolai Vyssotski, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/78274?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Code-Review+1 by Felix Held, Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Set the table size for L1 separately ...................................................................... amdfwtool: Set the table size for L1 separately The space defined by size of the L1 table can not overlap with ISH header. For other cases, the size defines the directory and its content. The PSP spec does not say it quite clearly. This change is partly based on guess and can make extraction tool work so far. Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 22 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/78274/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/78274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289 Gerrit-Change-Number: 78274 Gerrit-PatchSet: 13 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: amdfwtool: Set the table size for L1 separately
by Bao Zheng (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Felix Held, Martin Roth, Nikolai Vyssotski, Zheng Bao. Bao Zheng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78274?usp=email ) Change subject: amdfwtool: Set the table size for L1 separately ...................................................................... Patch Set 12: (2 comments) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/78274/comment/dfb566d3_dc5e9bbf : PS11, Line 655: if (cookie == PSP_COOKIE && cb_config->need_ish) : table_size = TABLE_ALIGNMENT; : else > good point. […] Done File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/78274/comment/9fb029c4_c9094537 : PS12, Line 576: uint32_t align_end = cb_config->need_ish ? TABLE_ALIGNMENT : 1; > shouldn't the table be always aligned to TABLE_ALIGNMENT? i'm fine with leaving this as it is right […] Actually all the table is aligned as 0x1000 at beginning of integrate_psp_firmwares. Maybe we will adjust the align in the future to save some space. The L1 with ISH can not be affected. -- To view, visit https://review.coreboot.org/c/coreboot/+/78274?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id4fbc6d57d7ea070a9478649a96af92be9441289 Gerrit-Change-Number: 78274 Gerrit-PatchSet: 12 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Nikolai Vyssotski <nikolai.vyssotski(a)amd.corp-partner.google.com> Gerrit-Attention: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 05 Mar 2024 06:28:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Bao Zheng <fishbaozi(a)gmail.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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