coreboot-gerrit March 2024

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[S] Change in coreboot[main]: ec/google/chromeec: Enclose Kconfig in 'if/endif' block
by Felix Held (Code Review) 05 Mar '24

05 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81025?usp=email ) Change subject: ec/google/chromeec: Enclose Kconfig in 'if/endif' block ...................................................................... ec/google/chromeec: Enclose Kconfig in 'if/endif' block Instead of having things depend on EC_GOOGLE_CHROMEEC, just put an if/ endif block around the configs. The 'source' line stays outside of the if block because the source always happens, even if it's inside an if/endif block. Each of the sub-Kconfigs here already has an if/endif block surrounding the contents. Signed-off-by: Martin Roth <gaumless(a)gmail.com> Change-Id: If88ba7d36ae04d879332037292c5cf9a3c8c3cab Reviewed-on: https://review.coreboot.org/c/coreboot/+/81025 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Caveh Jalali <caveh(a)chromium.org> --- M src/ec/google/chromeec/Kconfig 1 file changed, 7 insertions(+), 12 deletions(-) Approvals: build bot (Jenkins): Verified Caveh Jalali: Looks good to me, approved diff --git a/src/ec/google/chromeec/Kconfig b/src/ec/google/chromeec/Kconfig index 3b0beda..19790d1 100644 --- a/src/ec/google/chromeec/Kconfig +++ b/src/ec/google/chromeec/Kconfig @@ -6,6 +6,8 @@ help Google's Chrome EC +if EC_GOOGLE_CHROMEEC + config EC_GOOGLE_CHROMEEC_ACPI_MEMMAP depends on EC_GOOGLE_CHROMEEC_LPC def_bool n @@ -15,20 +17,17 @@ the LPC bus. config EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER - depends on EC_GOOGLE_CHROMEEC def_bool n help Expose methods for enabling and disabling port power on individual USB ports through the EC. config EC_GOOGLE_CHROMEEC_BOARDID - depends on EC_GOOGLE_CHROMEEC def_bool n help Provides common routine for reading boardid from Chrome EC. config EC_GOOGLE_CHROMEEC_I2C - depends on EC_GOOGLE_CHROMEEC bool default n help @@ -51,7 +50,7 @@ Use only proto3 for i2c EC communication. config EC_GOOGLE_CHROMEEC_ESPI - depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. + depends on ARCH_X86 # Needs Plug-and-play. def_bool n select EC_GOOGLE_CHROMEEC_LPC help @@ -62,7 +61,7 @@ still needs to correctly configure the bus transactions. config EC_GOOGLE_CHROMEEC_LPC - depends on EC_GOOGLE_CHROMEEC && ARCH_X86 # Needs Plug-and-play. + depends on ARCH_X86 # Needs Plug-and-play. def_bool n help Google Chrome EC via LPC bus. @@ -75,13 +74,11 @@ Microchip EC variant for LPC register access. config EC_GOOGLE_CHROMEEC_PD - depends on EC_GOOGLE_CHROMEEC def_bool n help Indicates that Google's Chrome USB PD chip is present. config EC_GOOGLE_CHROMEEC_SPI - depends on EC_GOOGLE_CHROMEEC def_bool n help Google's Chrome EC via SPI bus. @@ -108,7 +105,6 @@ Provides common routine for reporting the skuid to ChromeOS. config EC_GOOGLE_CHROMEEC_BOARDNAME - depends on EC_GOOGLE_CHROMEEC string "Chrome EC board name for EC" default "" help @@ -126,7 +122,6 @@ build the EC firmware and add it to the image. config EC_GOOGLE_CHROMEEC_RTC - depends on EC_GOOGLE_CHROMEEC bool "Enable ChromeOS EC RTC" help Enable support for the real-time clock on the ChromeOS EC. This @@ -134,7 +129,6 @@ choice prompt "Chrome EC firmware source" - depends on EC_GOOGLE_CHROMEEC default EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN if EC_GOOGLE_CHROMEEC_BOARDNAME != "" default EC_GOOGLE_CHROMEEC_FIRMWARE_NONE @@ -193,7 +187,7 @@ The path and filename of the PD firmware file to use. config EC_GOOGLE_CHROMEEC_SWITCHES - depends on EC_GOOGLE_CHROMEEC && VBOOT + depends on VBOOT bool help Enable support for ChromeOS mode switches provided by the ChromeOS @@ -207,9 +201,10 @@ 32 bits of firmware configuration. config EC_GOOGLE_CHROMEEC_AUTO_FAN_CTRL - depends on EC_GOOGLE_CHROMEEC bool "Enable automatic fan control" help Put the fan in auto mode at boot. +endif # EC_GOOGLE_CHROMEEC + source "src/ec/google/chromeec/*/Kconfig" -- To view, visit https://review.coreboot.org/c/coreboot/+/81025?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If88ba7d36ae04d879332037292c5cf9a3c8c3cab Gerrit-Change-Number: 81025 Gerrit-PatchSet: 2 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: mb/google/brya/var/xol: Add VGPIO configurations for PEG60
by Felix Held (Code Review) 05 Mar '24

05 Mar '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81033?usp=email ) ( 2 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/brya/var/xol: Add VGPIO configurations for PEG60 ...................................................................... mb/google/brya/var/xol: Add VGPIO configurations for PEG60 Add VGPIO configurations for NVMe on PEG60. BUG=b:326481458, b:372086400 BRANCH=firmware-brya-14505.B TEST=Verified DUT could detect NVMe. Install ChromeOS into NVMe and boot from it. Change-Id: I5520dc2a4bf6e788701a774674d223b7e8ad5b44 Signed-off-by: Seunghwan Kim <sh_.kim(a)samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81033 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/xol/gpio.c 1 file changed, 22 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/xol/gpio.c b/src/mainboard/google/brya/variants/xol/gpio.c index 2c56869..3a92b8e 100644 --- a/src/mainboard/google/brya/variants/xol/gpio.c +++ b/src/mainboard/google/brya/variants/xol/gpio.c @@ -193,6 +193,28 @@ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /* Add virtual GPIOs for CPU PCIe RP */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1), }; const struct pad_config *variant_gpio_override_table(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/81033?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5520dc2a4bf6e788701a774674d223b7e8ad5b44 Gerrit-Change-Number: 81033 Gerrit-PatchSet: 4 Gerrit-Owner: SH Kim <sh_.kim(a)samsung.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[XS] Change in em100[main]: em100: add missing long options for --upload and --voltage
by Name of user not set (Code Review) 05 Mar '24

05 Mar '24

c.koehne(a)beckhoff.com has uploaded this change for review. ( https://review.coreboot.org/c/em100/+/81078?usp=email ) Change subject: em100: add missing long options for --upload and --voltage ...................................................................... em100: add missing long options for --upload and --voltage Our usage says that those long options exists. Unfortunately, we do not parse them which may lead to confused user. Change-Id: I4a4e8d5ffa38e8ffef47f9966262eca874520f2c Signed-off-by: Corvin Köhne <c.koehne(a)beckhoff.com> --- M em100.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/em100 refs/changes/78/81078/1 diff --git a/em100.c b/em100.c index 68407c3..fe02d8d 100644 --- a/em100.c +++ b/em100.c @@ -785,6 +785,7 @@ {"download", 1, 0, 'd'}, {"start-address", 1, 0, 'a'}, {"address-mode", 1, 0, 'm'}, + {"upload", 1, 0, 'u'}, {"start", 0, 0, 'r'}, {"stop", 0, 0, 's'}, {"verify", 0, 0, 'v'}, @@ -794,6 +795,7 @@ {"trace", 0, 0, 't'}, {"offset", 1, 0, 'O'}, {"set-serialno", 1, 0, 'S'}, + {"set-voltage", 1, 0, 'V'}, {"firmware-update", 1, 0, 'F'}, {"firmware-dump", 1, 0, 'f'}, {"firmware-write", 1, 0, 'g'}, -- To view, visit https://review.coreboot.org/c/em100/+/81078?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: em100 Gerrit-Branch: main Gerrit-Change-Id: I4a4e8d5ffa38e8ffef47f9966262eca874520f2c Gerrit-Change-Number: 81078 Gerrit-PatchSet: 1 Gerrit-Owner: c.koehne(a)beckhoff.com Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Add memory type check utils
by Shuo Liu (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Christian Walter, Felix Held, Jincheng Li, Johnny Lin, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Paul Menzel, Ray Ni, Tim Chu. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80632?usp=email ) Change subject: soc/intel/xeon_sp: Add memory type check utils ...................................................................... Patch Set 9: (1 comment) File src/soc/intel/xeon_sp/spr/soc_util.c: https://review.coreboot.org/c/coreboot/+/80632/comment/b7a08de3_7264075f : PS6, Line 189: * vendorcode/intel/fsp/fsp2_0/sapphirerapids_sp/MemoryMapDataHob.h, > do you know when will it be uploaded? Not sure at the moment, we are recently told that EGS might not follow the same sharing way as CPX. -- To view, visit https://review.coreboot.org/c/coreboot/+/80632?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f5f3c0f16dc50bc739146e46afce2e5fbf4f62c Gerrit-Change-Number: 80632 Gerrit-PatchSet: 9 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 12:55:35 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/cmn/cse: Simplify logic to get CSE RW version
by Subrata Banik (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Kapil Porwal, Nick Vaccaro. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81051?usp=email ) Change subject: soc/intel/cmn/cse: Simplify logic to get CSE RW version ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81051?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86f2848788d0576a8fe3557fa8048e4162e61e05 Gerrit-Change-Number: 81051 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 05 Mar 2024 12:48:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/cmn/cse: Use CSE RW partition version directly for CBFS entry
by Kapil Porwal (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Subrata Banik. Kapil Porwal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80923?usp=email ) Change subject: soc/intel/cmn/cse: Use CSE RW partition version directly for CBFS entry ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/cse/Makefile.mk: https://review.coreboot.org/c/coreboot/+/80923/comment/65bd7c6b_c8cad13a : PS3, Line 99: $(foreach index,$(INDEXES), \ : $(shell dd if=$(INPUT_FILE) of=$(TEMP_FILE) bs=1 skip=$(word $(index),$(OFFSETS)) count=2 status=none) \ : $(eval $(word $(index),$(VERSIONS)) := $(shell printf "%d" 0x$(shell echo $(shell echo $(shell xxd -p $(TEMP_FILE)) | cut -c3-4)$(shell echo $(shell xxd -p $(TEMP_FILE)) | cut -c1-2))) ) \ : ) : rm -f $(TEMP_FILE) : $(eval CSE_RW_CBFS_VERSION := $(shell printf "%d.%d.%d.%d" $(CSE_VERSION_MAJOR)$(CSE_VERSION_MINOR)$(CSE_VERSION_HOTFIX)$(CSE_VERSION_BUILD))) > > It can be reduced to […] Done. CB:81051 -- To view, visit https://review.coreboot.org/c/coreboot/+/80923?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0165d81b0e4b38e0e097956f250bb7484d774145 Gerrit-Change-Number: 80923 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 12:42:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/cmn/cse: Simplify logic to get CSE RW version
by Kapil Porwal (Code Review) 05 Mar '24

05 Mar '24

Kapil Porwal has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81051?usp=email ) Change subject: soc/intel/cmn/cse: Simplify logic to get CSE RW version ...................................................................... soc/intel/cmn/cse: Simplify logic to get CSE RW version BUG=none TEST=Build and boot to google/screebo TEST=CSE RW version remains same with and without this change. ``` $ cbfstool image-screebo.bin extract -r FW_MAIN_A -n me_rw.version -f me_rw.version Found file me_rw.version at 0x81b40, type raw, compressed 12, size 12 $ hexdump -C me_rw.version 00000000 31 38 2e 30 2e 35 2e 32 31 30 37 0a |18.0.5.2107.| 0000000c ``` Signed-off-by: Kapil Porwal <kapilporwal(a)google.com> Change-Id: I86f2848788d0576a8fe3557fa8048e4162e61e05 --- M src/soc/intel/common/block/cse/Makefile.mk 1 file changed, 1 insertion(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/81051/1 diff --git a/src/soc/intel/common/block/cse/Makefile.mk b/src/soc/intel/common/block/cse/Makefile.mk index 653d674..50011ec 100644 --- a/src/soc/intel/common/block/cse/Makefile.mk +++ b/src/soc/intel/common/block/cse/Makefile.mk @@ -89,20 +89,8 @@ $(CSE_LITE_ME_RW)-compression := LZMA endif -INPUT_FILE := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) -TEMP_FILE := $(shell mktemp) -OFFSETS := 16 18 20 22 # Offsets for CSE version components -VERSIONS := CSE_VERSION_MAJOR CSE_VERSION_MINOR CSE_VERSION_HOTFIX CSE_VERSION_BUILD -INDEXES := $(shell seq 1 $(words $(OFFSETS))) - $(obj)/cse_rw.version: - $(foreach index,$(INDEXES), \ - $(shell dd if=$(INPUT_FILE) of=$(TEMP_FILE) bs=1 skip=$(word $(index),$(OFFSETS)) count=2 status=none) \ - $(eval $(word $(index),$(VERSIONS)) := $(shell printf "%d" 0x$(shell echo $(shell echo $(shell xxd -p $(TEMP_FILE)) | cut -c3-4)$(shell echo $(shell xxd -p $(TEMP_FILE)) | cut -c1-2))) ) \ - ) - rm -f $(TEMP_FILE) - $(eval CSE_RW_CBFS_VERSION := $(shell printf "%d.%d.%d.%d" $(CSE_VERSION_MAJOR)$(CSE_VERSION_MINOR)$(CSE_VERSION_HOTFIX)$(CSE_VERSION_BUILD))) - @echo '$(CSE_RW_CBFS_VERSION)' > $@ + @echo $(shell hexdump -s 16 -n 8 -e '4/2 "%d."' $(CSE_RW_FILE) | sed 's/\.$$//') > $@ CSE_RW_VERSION = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME)) regions-for-file-$(CSE_RW_VERSION) = FW_MAIN_A,FW_MAIN_B -- To view, visit https://review.coreboot.org/c/coreboot/+/81051?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86f2848788d0576a8fe3557fa8048e4162e61e05 Gerrit-Change-Number: 81051 Gerrit-PatchSet: 1 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanel
by Subrata Banik (Code Review) 05 Mar '24

05 Mar '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80850?usp=email ) Change subject: mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanel ...................................................................... mb/google/nissa/var/gothrax: Add probe and GPIO config for touchpanel Add FW_CONFIG probe to separate touch panel settings. TOUCH_PANEL_ENABLE/TOUCH_PANEL_DISABLE Use different gpio tables based on the value of TOUCH_PANEL. BUG=b:325987249 TEST=emerge-nissa coreboot and run in DUT Change-Id: I23c62406a932815ff1cfafe05b70468b1f9cca54 Signed-off-by: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80850 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Kyle Lin <kylelinck(a)google.com> --- M src/mainboard/google/brya/variants/gothrax/gpio.c M src/mainboard/google/brya/variants/gothrax/overridetree.cb 2 files changed, 22 insertions(+), 3 deletions(-) Approvals: Eric Lai: Looks good to me, approved Yunlong Jia: Looks good to me, but someone else must approve build bot (Jenkins): Verified Kyle Lin: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/gothrax/gpio.c b/src/mainboard/google/brya/variants/gothrax/gpio.c index 0bf1b52..077c850 100644 --- a/src/mainboard/google/brya/variants/gothrax/gpio.c +++ b/src/mainboard/google/brya/variants/gothrax/gpio.c @@ -2,6 +2,7 @@ #include <baseboard/variants.h> #include <soc/gpio.h> +#include <fw_config.h> /* Pad configuration in ramstage */ static const struct pad_config override_gpio_table[] = { @@ -80,6 +81,13 @@ PAD_CFG_GPO(GPP_H20, 1, DEEP), }; +static const struct pad_config romstage_gpio_table_nontp[] = { + /* H12 : UART0_RTS# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H12, 1, DEEP), + /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */ + PAD_CFG_GPO(GPP_H20, 1, DEEP), +}; + const struct pad_config *variant_gpio_override_table(size_t *num) { *num = ARRAY_SIZE(override_gpio_table); @@ -94,6 +102,11 @@ const struct pad_config *variant_romstage_gpio_table(size_t *num) { - *num = ARRAY_SIZE(romstage_gpio_table); - return romstage_gpio_table; + if (fw_config_probe(FW_CONFIG(TOUCH_PANEL, TOUCH_PANEL_DISABLE))) { + *num = ARRAY_SIZE(romstage_gpio_table_nontp); + return romstage_gpio_table_nontp; + } else { + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; + } } diff --git a/src/mainboard/google/brya/variants/gothrax/overridetree.cb b/src/mainboard/google/brya/variants/gothrax/overridetree.cb index b36ff07..77be31c 100644 --- a/src/mainboard/google/brya/variants/gothrax/overridetree.cb +++ b/src/mainboard/google/brya/variants/gothrax/overridetree.cb @@ -24,6 +24,10 @@ option WFC_PRESENT 0 option WFC_ABSENT 1 end + field TOUCH_PANEL 9 + option TOUCH_PANEL_ENABLE 0 + option TOUCH_PANEL_DISABLE 1 + end end chip soc/intel/alderlake @@ -226,7 +230,9 @@ register "generic.enable_delay_ms" = "6" register "generic.has_power_resource" = "1" register "hid_desc_reg_offset" = "0x01" - device i2c 0x10 on end + device i2c 0x10 on + probe TOUCH_PANEL TOUCH_PANEL_ENABLE + end end end device ref i2c2 on -- To view, visit https://review.coreboot.org/c/coreboot/+/80850?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I23c62406a932815ff1cfafe05b70468b1f9cca54 Gerrit-Change-Number: 80850 Gerrit-PatchSet: 4 Gerrit-Owner: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kyle Lin <kylelinck(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yunlong Jia <yunlong.jia(a)ecs.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: soc/intel/xeon_sp: Drop unused helper functions
by Lean Sheng Tan (Code Review) 05 Mar '24

05 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80143?usp=email ) Change subject: soc/intel/xeon_sp: Drop unused helper functions ...................................................................... soc/intel/xeon_sp: Drop unused helper functions Change-Id: Ib319643f6b0b91d8c5854da531e035d333f04d75 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80143 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/include/soc/soc_util.h M src/soc/intel/xeon_sp/spr/soc_util.c 6 files changed, 0 insertions(+), 31 deletions(-) Approvals: Shuo Liu: Looks good to me, but someone else must approve Lean Sheng Tan: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index c3d07af..d1ce7bf 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -25,7 +25,6 @@ const struct SystemMemoryMapHob *get_system_memory_map(void); uint8_t socket0_get_ubox_busno(const uint8_t stack); -uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); uint8_t get_cxl_node_count(void); int soc_get_stack_for_port(int port); diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index b7cc24b..5dbac98 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -47,15 +47,6 @@ return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff; } -uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) -{ - const IIO_UDS *hob = get_iio_uds(); - - assert(socket < CONFIG_MAX_SOCKET && stack < MAX_LOGIC_IIO_STACK); - - return hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; -} - /* * EX: CPX-SP * Ports Stack Stack(HOB) IioConfigIou diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index b86322c..0c4f998 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -11,7 +11,6 @@ const struct SystemMemoryMapHob *get_system_memory_map(void); uint8_t socket0_get_ubox_busno(const uint8_t stack); -uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); int soc_get_stack_for_port(int port); uint8_t get_cxl_node_count(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index aee3f81..12d30d4 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -96,15 +96,6 @@ return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff; } -uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) -{ - const IIO_UDS *hob = get_iio_uds(); - - assert(socket < MAX_SOCKET && stack < MAX_IIO_STACK); - - return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; -} - #if ENV_RAMSTAGE void config_reset_cpl3_csrs(void) { diff --git a/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h b/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h index a7bf06c..631601e 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h @@ -31,8 +31,6 @@ const struct SystemMemoryMapHob *get_system_memory_map(void); const struct SystemMemoryMapElement *get_system_memory_map_elment(uint8_t *num); -uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); - bool is_iio_cxl_stack_res(const STACK_RES *res); void soc_display_iio_universal_data_hob(const IIO_UDS *hob); diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index be1e06c..b8f06ac 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -135,15 +135,6 @@ return count; } -uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack) -{ - const IIO_UDS *hob = get_iio_uds(); - - assert(socket < CONFIG_MAX_SOCKET && stack < MAX_LOGIC_IIO_STACK); - - return hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; -} - /* Returns the UBOX(offset) bus number for socket0 */ uint8_t socket0_get_ubox_busno(uint8_t offset) { -- To view, visit https://review.coreboot.org/c/coreboot/+/80143?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib319643f6b0b91d8c5854da531e035d333f04d75 Gerrit-Change-Number: 80143 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Drop code to locate the UBOX bus
by Lean Sheng Tan (Code Review) 05 Mar '24

05 Mar '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80102?usp=email ) Change subject: soc/intel/xeon_sp: Drop code to locate the UBOX bus ...................................................................... soc/intel/xeon_sp: Drop code to locate the UBOX bus Drop the code to retrieve the UBOX bus numbers. Only keep a minial function that works when called from socket0 to retrieve the bus for UBOX(1). Change-Id: I2b18f02f62b69ec7c73cd5665102cb6bfc6e64b5 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80102 Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/mainboard/ocp/deltalake/ramstage.c M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/include/soc/soc_util.h M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/util.c 8 files changed, 16 insertions(+), 35 deletions(-) Approvals: Shuo Liu: Looks good to me, but someone else must approve build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index f846055..55a10ad 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -195,7 +195,7 @@ printk(BIOS_ERR, "Failed to get IPMI PCIe config\n"); for (index = 0; index < ARRAY_SIZE(stack_busnos); index++) - stack_busnos[index] = get_stack_busno(index); + stack_busnos[index] = socket0_get_ubox_busno(index); for (index = 0; index < ARRAY_SIZE(slotinfo); index++) { uint8_t characteristics_1 = 0; diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 91919b8..c3d07af 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -24,9 +24,8 @@ const struct SystemMemoryMapHob *get_system_memory_map(void); -uint8_t get_stack_busno(const uint8_t stack); +uint8_t socket0_get_ubox_busno(const uint8_t stack); uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); -uint32_t get_socket_ubox_busno(uint32_t socket); uint8_t get_cxl_node_count(void); int soc_get_stack_for_port(int port); diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index 836cd0c..b7cc24b 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -35,7 +35,8 @@ return res->Personality == TYPE_UBOX; } -uint8_t get_stack_busno(const uint8_t stack) +/* Returns the UBOX(stack) bus number when called from socket0 */ +uint8_t socket0_get_ubox_busno(const uint8_t stack) { if (stack >= MAX_IIO_STACK) { printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack); @@ -55,14 +56,6 @@ return hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; } -uint32_t get_socket_ubox_busno(uint32_t socket) -{ - if (socket == 0) - return get_stack_busno(PCU_IIO_STACK); - - return get_socket_stack_busno(socket, PCU_IIO_STACK); -} - /* * EX: CPX-SP * Ports Stack Stack(HOB) IioConfigIou diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 379cdc8..b86322c 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -10,9 +10,8 @@ const struct SystemMemoryMapHob *get_system_memory_map(void); -uint8_t get_stack_busno(const uint8_t stack); +uint8_t socket0_get_ubox_busno(const uint8_t stack); uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); -uint32_t get_socket_ubox_busno(uint32_t socket); int soc_get_stack_for_port(int port); uint8_t get_cxl_node_count(void); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index 4201d10..aee3f81 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -84,7 +84,8 @@ return false; } -uint8_t get_stack_busno(const uint8_t stack) +/* Returns the UBOX(stack) bus number when called from socket0 */ +uint8_t socket0_get_ubox_busno(const uint8_t stack) { if (stack >= MAX_IIO_STACK) { printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack); @@ -104,14 +105,6 @@ return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; } -uint32_t get_socket_ubox_busno(uint32_t socket) -{ - if (socket == 0) - return get_stack_busno(PCU_IIO_STACK); - - return get_socket_stack_busno(socket, PCU_IIO_STACK); -} - #if ENV_RAMSTAGE void config_reset_cpl3_csrs(void) { diff --git a/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h b/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h index 997cdb4..a7bf06c 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h @@ -45,8 +45,7 @@ const EWL_PRIVATE_DATA *get_ewl_hob(void); -uint32_t get_ubox_busno(uint32_t socket, uint8_t offset); -uint32_t get_socket_ubox_busno(uint32_t socket); +uint8_t socket0_get_ubox_busno(uint8_t offset); void soc_set_mrc_cold_boot_flag(bool cold_boot_required); void soc_config_iio(FSPM_UPD *mupd, const UPD_IIO_PCIE_PORT_CONFIG_ENTRY mb_iio_table[CONFIG_MAX_SOCKET][IIO_PORT_SETTINGS], const UINT8 mb_iio_bifur[CONFIG_MAX_SOCKET][5]); diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index 344fa5b..be1e06c 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -144,25 +144,20 @@ return hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; } -uint32_t get_ubox_busno(uint32_t socket, uint8_t offset) +/* Returns the UBOX(offset) bus number for socket0 */ +uint8_t socket0_get_ubox_busno(uint8_t offset) { const IIO_UDS *hob = get_iio_uds(); - assert(socket < CONFIG_MAX_SOCKET); for (int stack = 0; stack < MAX_LOGIC_IIO_STACK; ++stack) { - if (hob->PlatformData.IIO_resource[socket].StackRes[stack].Personality + if (hob->PlatformData.IIO_resource[0].StackRes[stack].Personality == TYPE_UBOX) - return (hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase + return (hob->PlatformData.IIO_resource[0].StackRes[stack].BusBase + offset); } die("Unable to locate UBOX BUS NO"); } -uint32_t get_socket_ubox_busno(uint32_t socket) -{ - return get_ubox_busno(socket, UNCORE_BUS_1); -} - void bios_done_msr(void *unused) { msr_t msr = rdmsr(MSR_BIOS_DONE); diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index 956973e..b3ee02b 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -17,12 +17,15 @@ #include <soc/util.h> #include <timer.h> +/* Only call this code from socket0! */ void unlock_pam_regions(void) { uint32_t pam0123_unlock_dram = 0x33333330; uint32_t pam456_unlock_dram = 0x00333333; - uint32_t bus1 = get_socket_ubox_busno(0); + /* Get UBOX(1) for socket0 */ + uint32_t bus1 = socket0_get_ubox_busno(PCU_IIO_STACK); + /* Assume socket0 owns PCI segment 0 */ pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), -- To view, visit https://review.coreboot.org/c/coreboot/+/80102?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b18f02f62b69ec7c73cd5665102cb6bfc6e64b5 Gerrit-Change-Number: 80102 Gerrit-PatchSet: 11 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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