coreboot-gerrit March 2024

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
by Jérémy Compostella (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Subrata Banik, Tarun, Wonkyu Kim. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80275?usp=email ) Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support ...................................................................... Patch Set 17: (8 comments) Patchset: PS16: > why this CL is sitting on top of 3 other cls which seems related to FSP doing MP Init. […] I agree. I cleaned-up the relation chain which should help smoothly land this patch faster. File src/commonlib/include/commonlib/console/post_codes.h: https://review.coreboot.org/c/coreboot/+/80275/comment/afc96322_fcf1adbf : PS16, Line 337: MemoryInit > why don't we use 0xa4 for FSP_M MultiPhase entry and 0xa5 for exit? Done File src/commonlib/include/commonlib/timestamp_serialized.h: https://review.coreboot.org/c/coreboot/+/80275/comment/99337a3d_59e3c4c7 : PS16, Line 143: 972 > why not 964 and 965 ? Done File src/drivers/intel/fsp2_0/include/fsp/info_header.h: https://review.coreboot.org/c/coreboot/+/80275/comment/4da777fa_b56a3bbf : PS16, Line 41: fsp_smm_init_entry_offset > we don't need this, please mark reserved Done File src/drivers/intel/fsp2_0/include/fsp/util.h: https://review.coreboot.org/c/coreboot/+/80275/comment/6e3540cc_e116af87 : PS16, Line 83: }; : : struct fsp_multi_phase_get_number_of_phases_params { : uint32_t number_of_phases; : uint32_t phases_executed; : }; > nit: move after line #58 ? Done File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/80275/comment/d49225e2_c63535f4 : PS16, Line 278: fspm_return_value_handler > nit: why don't we create `fsp_return_value_handler` to address both FSP-M and S case now ? There are fundamental differences between memory and silicon fsp return handler like multiphase ID or dependencies on GOP/VBT... https://review.coreboot.org/c/coreboot/+/80275/comment/4fe4c0a3_c5a680e7 : PS16, Line 433: fspm_multi_phase_init(hdr); > should we avoid calling into fspm_multi_phase_init() if FSP version is not 2. […] It would require guarding the function definition with `CONFIG_PLATFORM_USES_FSP2_4` and it will lead to the same result as the current implementation as the compiler optimized out that call. File util/cbfstool/eventlog.c: https://review.coreboot.org/c/coreboot/+/80275/comment/387dab7a_53cff450 : PS16, Line 410: {POSTCODE_FSP_MULTI_PHASE_INIT_ENTRY, "FSP-M/S Multi Phase Init Enter"}, : {POSTCODE_FSP_MULTI_PHASE_INIT_EXIT, "FPS-M/S Multi Phase Init Exit"}, > as suggested, keep different post codes Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Gerrit-Change-Number: 80275 Gerrit-PatchSet: 17 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 17:49:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0/ppi: Fix FSP PPI callback calling convention
by Jérémy Compostella (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Chen, Gang C, Jincheng Li, Ronak Kanabar, Shuo Liu, Subrata Banik. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80574?usp=email ) Change subject: drivers/intel/fsp2_0/ppi: Fix FSP PPI callback calling convention ...................................................................... Patch Set 8: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80574/comment/a326beb2_d407d7d5 : PS7, Line 9: Multi Processor PEIM-to-PEIM Interface deals with pointer to function : living in FSP space > this is not correct, with a unified stack between FSP and coreboot. This code is getting executed in the context of coreboot rather than FSP. Coreboot receives a pointer to a function which is a FSP function hence living in the FSP space. I am not talking about the context of execution just where the function is coming from. In this case it lives in the FSP space and therefore obey to FSP C-calling convention rules. > i would like to understand the problem in detail about what you are running into. So far, we are using this PPI for many platforms and don't see any problem. Yeah and this is mostly out of luck because the C-calling convention between UEFI (Microsoft) and Linux (Unix like - GCC) is the same on 32 bits (`cdecl`). But technically, the C-calling convention for UEFI functions is defined by the `EFIAPI` macro. C components like coreboot when they call into such functions must ensure they follow the right calling convention. For 64-bits the calling convention is clearly different: Microsoft x64 calling convention vs System V AMD64 ABI. Currently, the coreboot code as receives a `efi_ap_procedure` function (which correctly includes `EFIAPI` in its definition) but then it discards it by casting it as `void *`. While this does not lead to any issue in 32-bits , this is 1- incorrect 2 - lead to crashes in 64-bits. Because it is just incorrect in the first place I made a dedicated patch instead of including it in the 64-bits support patch. -- To view, visit https://review.coreboot.org/c/coreboot/+/80574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec95 Gerrit-Change-Number: 80574 Gerrit-PatchSet: 8 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 17:48:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0/ppi: Fix FSP PPI callback calling convention
by Jérémy Compostella (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Chen, Gang C, Jincheng Li, Jérémy Compostella, Ronak Kanabar, Shuo Liu. Hello Andrey Petrov, Arthur Heymans, Chen, Gang C, Jincheng Li, Ronak Kanabar, Shuo Liu, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80574?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp2_0/ppi: Fix FSP PPI callback calling convention ...................................................................... drivers/intel/fsp2_0/ppi: Fix FSP PPI callback calling convention Multi Processor PEIM-to-PEIM Interface deals with pointer to FSP functions which therefore obey to the UEFI C calling convention which coreboot must complies to. By casting the callback pointer to a `void (*)(void *)' when calling `mp_run_on_all_aps' the C calling convention attribute is lost and the the code generated by the compiler does not match the FSP C calling convention. This commit adds a function indirection to ensure FSP callbacks are invoked appropriately. TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec95 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c 1 file changed, 32 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/80574/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/80574?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If0397f5cc8d0f4f1872bd37a001fe42e0c37ec95 Gerrit-Change-Number: 80574 Gerrit-PatchSet: 8 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support
by Jérémy Compostella (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Tarun, Wonkyu Kim. Hello Andrey Petrov, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Shuo Liu, Tarun, Wonkyu Kim, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/80275?usp=email to look at the new patch set (#17). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support ...................................................................... drivers/intel/fsp2_0: Add limited to 32-bits FSP 2.4 support Intel Firmware Support Package 2.4 specification (document 736809) brings some significant changes compared to version 2.3 (document 644852): 1. It supports FSP-M multi-phase init. Some fields have been added to the FSP header data structure for this purpose. 2. The `FSPM_ARCH2_UPD' and `FSPS_ARCH2_UPD' data structures must be used in place of `FSPM_ARCH_UPD' and `FSPS_ARCH_UPD' respectively. 3. It support 64-bits FSP but 64-bits support will be provided by subsequent patch. Note that similarly to what is done for silicon initialization, timestamps and post-codes are used during the memory initialization multi-phase. [736809] https://cdrdv2-public.intel.com/736809/736809_FSP_EAS_v2.4_Errata_A.pdf [644852] https://cdrdv2-public.intel.com/644852/644852_2.3_Firmware-Support-Package-… TEST=verified on Lunar Lake RVP board (lnlrvp) Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/commonlib/include/commonlib/console/post_codes.h M src/commonlib/include/commonlib/timestamp_serialized.h M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/include/fsp/info_header.h M src/drivers/intel/fsp2_0/include/fsp/util.h M src/drivers/intel/fsp2_0/memory_init.c M src/drivers/intel/fsp2_0/silicon_init.c M src/drivers/intel/fsp2_0/upd_display.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/tigerlake/fsp_params.c M util/cbfstool/eventlog.c 13 files changed, 131 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/80275/17 -- To view, visit https://review.coreboot.org/c/coreboot/+/80275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1c24d26e105c3dcbd9cca0e7197ab1362344aa97 Gerrit-Change-Number: 80275 Gerrit-PatchSet: 17 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Appukuttan V K <appukuttan.vk(a)intel.com> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: qemu-riscv: Improve Documentation
by Ayan Agrawal (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Daniel Maslowski, Daniel Maslowski, Felix Singer, Martin L Roth, ron minnich. Ayan Agrawal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77410?usp=email ) Change subject: qemu-riscv: Improve Documentation ...................................................................... Patch Set 11: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/77410/comment/cfcbdb91_33b69974 : PS9, Line 9: The documentation for loading coreboot as kernel doesn't work and is outdated. : Should use -bios to load coreboot in QEMU > Align lines to 72 characters. Add an empty line between description and Change-Id. TIL, thanks! Updated, should be okay now. -- To view, visit https://review.coreboot.org/c/coreboot/+/77410?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6dbddb6d8801c456196142c3c7d0a2cbf2ed0fb7 Gerrit-Change-Number: 77410 Gerrit-PatchSet: 11 Gerrit-Owner: Ayan Agrawal <ayanagr03(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <cyrevolt(a)googlemail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Daniel Maslowski <info(a)orangecms.org> Gerrit-Attention: Daniel Maslowski <cyrevolt(a)googlemail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 17:30:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: qemu-riscv: Improve Documentation
by Ayan Agrawal (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Daniel Maslowski, Daniel Maslowski, Martin L Roth, ron minnich. Hello Daniel Maslowski, Daniel Maslowski, Philipp Hug, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77410?usp=email to look at the new patch set (#11). Change subject: qemu-riscv: Improve Documentation ...................................................................... qemu-riscv: Improve Documentation The documentation for loading coreboot as kernel doesn't work and is outdated. Should use -bios to load coreboot in QEMU Change-Id: I6dbddb6d8801c456196142c3c7d0a2cbf2ed0fb7 Signed-off-by: Ayan Agrawal <ayanagr03(a)gmail.com> --- M Documentation/mainboard/emulation/qemu-riscv.md 1 file changed, 36 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/77410/11 -- To view, visit https://review.coreboot.org/c/coreboot/+/77410?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6dbddb6d8801c456196142c3c7d0a2cbf2ed0fb7 Gerrit-Change-Number: 77410 Gerrit-PatchSet: 11 Gerrit-Owner: Ayan Agrawal <ayanagr03(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <cyrevolt(a)googlemail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Daniel Maslowski <info(a)orangecms.org> Gerrit-Attention: Daniel Maslowski <cyrevolt(a)googlemail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: qemu-riscv: Improve Documentation
by Ayan Agrawal (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Daniel Maslowski, Daniel Maslowski, Martin L Roth, ron minnich. Hello Daniel Maslowski, Daniel Maslowski, Philipp Hug, build bot (Jenkins), ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/77410?usp=email to look at the new patch set (#10). Change subject: qemu-riscv: Improve Documentation ...................................................................... qemu-riscv: Improve Documentation The documentation for loading coreboot as kernel doesn't work and is outdated. Should use -bios to load coreboot in QEMU Change-Id: I6dbddb6d8801c456196142c3c7d0a2cbf2ed0fb7 Signed-off-by: Ayan Agrawal <ayanagr03(a)gmail.com> --- M Documentation/mainboard/emulation/qemu-riscv.md 1 file changed, 36 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/77410/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/77410?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6dbddb6d8801c456196142c3c7d0a2cbf2ed0fb7 Gerrit-Change-Number: 77410 Gerrit-PatchSet: 10 Gerrit-Owner: Ayan Agrawal <ayanagr03(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <cyrevolt(a)googlemail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Daniel Maslowski <info(a)orangecms.org> Gerrit-Attention: Daniel Maslowski <cyrevolt(a)googlemail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: qemu-riscv: Improve Documentation
by Felix Singer (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Daniel Maslowski, Daniel Maslowski, Martin L Roth, ron minnich. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77410?usp=email ) Change subject: qemu-riscv: Improve Documentation ...................................................................... Patch Set 9: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/77410/comment/ba7817e2_b5159a27 : PS9, Line 9: The documentation for loading coreboot as kernel doesn't work and is outdated. : Should use -bios to load coreboot in QEMU Align lines to 72 characters. Add an empty line between description and Change-Id. -- To view, visit https://review.coreboot.org/c/coreboot/+/77410?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6dbddb6d8801c456196142c3c7d0a2cbf2ed0fb7 Gerrit-Change-Number: 77410 Gerrit-PatchSet: 9 Gerrit-Owner: Ayan Agrawal <ayanagr03(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <cyrevolt(a)googlemail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Daniel Maslowski <info(a)orangecms.org> Gerrit-Attention: Daniel Maslowski <cyrevolt(a)googlemail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 17:23:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[S] Change in coreboot[main]: qemu-riscv: Improve Documentation
by Ayan Agrawal (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Daniel Maslowski, Daniel Maslowski, Martin L Roth, ron minnich. Ayan Agrawal has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77410?usp=email ) Change subject: qemu-riscv: Improve Documentation ...................................................................... Patch Set 9: (1 comment) File Documentation/mainboard/emulation/qemu-riscv.md: https://review.coreboot.org/c/coreboot/+/77410/comment/4342d02f_867f007b : PS7, Line 35: > This trailing space needs to be removed, then this patch can be merged. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77410?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6dbddb6d8801c456196142c3c7d0a2cbf2ed0fb7 Gerrit-Change-Number: 77410 Gerrit-PatchSet: 9 Gerrit-Owner: Ayan Agrawal <ayanagr03(a)gmail.com> Gerrit-Reviewer: Daniel Maslowski <cyrevolt(a)googlemail.com> Gerrit-Reviewer: Daniel Maslowski <info(a)orangecms.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Daniel Maslowski <info(a)orangecms.org> Gerrit-Attention: Daniel Maslowski <cyrevolt(a)googlemail.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 17:23:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports
by Martin L Roth (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Alicja Michalska, Arthur Heymans, Nick Vaccaro. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80848?usp=email ) Change subject: soc/intel/tigerlake: Add IRQ mapping for PEG PCI-E ports ...................................................................... Patch Set 1: (1 comment) Patchset: PS1: Hi, It looks like you haven't contributed to the coreboot project before. Welcome, and thank you for the patch. We hope that this is just the first of many. Please let us know if there's anything we can do to help get your first sets patches merged as you get used to the contribution process. The coreboot project has a hands-off policy regarding other people's patches so nobody here is going to update the contents without your permission. If you would you like someone to take over your patches at any point, please just post a comment to that effect on the specific patch. You might find the coding style guide and the gerrit guidelines useful to read. https://doc.coreboot.org/contributing/coding_style.html https://doc.coreboot.org/contributing/gerrit_guidelines.html If you want to talk with anyone, you can talk to developers on one of the many options we have: https://doc.coreboot.org/community/forums.html Again, please let us know if you have any questions or if there's anything we can do to help. -- To view, visit https://review.coreboot.org/c/coreboot/+/80848?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If102522efa1a67b362b14d859d9e27a37bad85a4 Gerrit-Change-Number: 80848 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 05 Mar 2024 17:13:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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