coreboot-gerrit March 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug
by Nico Huber (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Arthur Heymans, Chen, Gang C, Christian Walter, Felix Singer, Jincheng Li, Johnny Lin, Jérémy Compostella, Patrick Rudolph, Paul Menzel, Ray Ni, Ronak Kanabar, Shuo Liu, Tim Chu. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80579?usp=email ) Change subject: drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80579?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I38a4f4b7470556e528a1672044c31f8bd92887d4 Gerrit-Change-Number: 80579 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Ray Ni <ray.ni(a)intel.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Ray Ni <ray.ni(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Chen, Gang C <gang.c.chen(a)intel.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 21:25:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: lib/program.ld: Make (NOLOAD) and to_load more explicit
by Nico Huber (Code Review) 05 Mar '24

05 Mar '24

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80803?usp=email ) Change subject: lib/program.ld: Make (NOLOAD) and to_load more explicit ...................................................................... lib/program.ld: Make (NOLOAD) and to_load more explicit (NOLOAD) indicates that the section occupies no space in the file, but does take up space in memory during process execution. It's typically used for bss sections which contain uninitialized global/static variables. to_load makes sure the section is part of the program headers. This is needed for instance with relocatable stages to know how much memory the program will use. Although the BFD linker makes some good guesses making this a NOOP, other linkers like LLD need to mark these sections more explicitly. Change-Id: Ic14543ba580abe7a34c69bba714eae8cce504977 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80803 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-by: Maximilian Brune <maximilian.brune(a)9elements.com> --- M src/lib/program.ld 1 file changed, 6 insertions(+), 6 deletions(-) Approvals: Nico Huber: Looks good to me, approved build bot (Jenkins): Verified Julius Werner: Looks good to me, approved Maximilian Brune: Looks good to me, approved diff --git a/src/lib/program.ld b/src/lib/program.ld index 21f4be8..1784447 100644 --- a/src/lib/program.ld +++ b/src/lib/program.ld @@ -68,7 +68,7 @@ LONG(0); LONG(0); __CTOR_END__ = .; -} +} : to_load #endif /* Include data, bss, and heap in that order. Not defined for all stages. */ @@ -113,11 +113,11 @@ . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _edata = .; RECORD_SIZE(data) -} +} : to_load #endif #if !ENV_SEPARATE_DATA_AND_BSS -.bss . : { +.bss . (NOLOAD) : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _bss = .; *(.bss) @@ -127,18 +127,18 @@ . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _ebss = .; RECORD_SIZE(bss) -} +} : to_load #endif #if ENV_HAS_HEAP_SECTION -.heap . : { +.heap . (NOLOAD) : { . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _heap = .; . += CONFIG_HEAP_SIZE; . = ALIGN(ARCH_POINTER_ALIGN_SIZE); _eheap = .; RECORD_SIZE(heap) -} +} : to_load #endif #if ENV_RAMSTAGE && CONFIG(ASAN_IN_RAMSTAGE) -- To view, visit https://review.coreboot.org/c/coreboot/+/80803?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic14543ba580abe7a34c69bba714eae8cce504977 Gerrit-Change-Number: 80803 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[S] Change in coreboot[main]: lib/program.ld: Make (NOLOAD) and to_load more explicit
by Nico Huber (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80803?usp=email ) Change subject: lib/program.ld: Make (NOLOAD) and to_load more explicit ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/80803?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic14543ba580abe7a34c69bba714eae8cce504977 Gerrit-Change-Number: 80803 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 05 Mar 2024 21:22:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/amd/onyx_poc/devicetree: explicitly assign PCIe engine type
by Felix Held (Code Review) 05 Mar '24

05 Mar '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81095?usp=email ) Change subject: mb/amd/onyx_poc/devicetree: explicitly assign PCIe engine type ...................................................................... mb/amd/onyx_poc/devicetree: explicitly assign PCIe engine type Explicitly assign the 'PCIE' value to the 'type' field of the corresponding MPIO chips in the devicetree. Since the mpio_type enum element 'PCIE' has the value 0, this won't change the behavior, but explicitly assigning this makes this easier to understand. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I84a364cf16c99ba11f67cf033962bbf2c982f6ff --- M src/mainboard/amd/onyx_poc/devicetree.cb 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/81095/1 diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb index 39c681d..3597847 100644 --- a/src/mainboard/amd/onyx_poc/devicetree.cb +++ b/src/mainboard/amd/onyx_poc/devicetree.cb @@ -57,6 +57,7 @@ device ref rcec_0 on end device ref gpp_bridge_0_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P2 + register "type" = "PCIE" register "start_lane" = "48" register "end_lane" = "63" register "gpio_group" = "1" @@ -66,6 +67,7 @@ end device ref gpp_bridge_0_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G2 + register "type" = "PCIE" register "start_lane" = "112" register "end_lane" = "127" register "gpio_group" = "1" @@ -76,6 +78,7 @@ end device ref gpp_bridge_0_0_c on chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "PCIE" register "start_lane" = "128" register "end_lane" = "131" register "gpio_group" = "1" @@ -98,6 +101,7 @@ device ref rcec_1 on end device ref gpp_bridge_1_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P3 + register "type" = "PCIE" register "start_lane" = "16" register "end_lane" = "31" register "gpio_group" = "1" @@ -107,6 +111,7 @@ end device ref gpp_bridge_1_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G3 + register "type" = "PCIE" register "start_lane" = "80" register "end_lane" = "95" register "gpio_group" = "1" @@ -121,6 +126,7 @@ device ref rcec_2 on end device ref gpp_bridge_2_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P1 + register "type" = "PCIE" register "start_lane" = "32" register "end_lane" = "47" register "gpio_group" = "1" @@ -131,6 +137,7 @@ end device ref gpp_bridge_2_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G1 + register "type" = "PCIE" register "start_lane" = "64" register "end_lane" = "79" register "gpio_group" = "1" @@ -146,6 +153,7 @@ device ref rcec_3 on end device ref gpp_bridge_3_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P0 + register "type" = "PCIE" register "start_lane" = "0" register "end_lane" = "15" register "gpio_group" = "1" @@ -155,6 +163,7 @@ end device ref gpp_bridge_3_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G0 + register "type" = "PCIE" register "start_lane" = "96" register "end_lane" = "111" register "gpio_group" = "1" @@ -164,6 +173,7 @@ end device ref gpp_bridge_3_0_c on # WAFL chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "PCIE" register "start_lane" = "132" register "end_lane" = "133" register "gpio_group" = "1" @@ -173,6 +183,7 @@ end device ref gpp_bridge_3_1_c on # BMC chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "PCIE" register "start_lane" = "134" register "end_lane" = "134" register "gpio_group" = "1" @@ -183,6 +194,7 @@ end device ref gpp_bridge_3_2_c on # BMC chip vendorcode/amd/opensil/genoa_poc/mpio + register "type" = "PCIE" register "start_lane" = "135" register "end_lane" = "135" register "gpio_group" = "1" -- To view, visit https://review.coreboot.org/c/coreboot/+/81095?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84a364cf16c99ba11f67cf033962bbf2c982f6ff Gerrit-Change-Number: 81095 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/sifive/sifive-unmatched: add support for spi1 x4 mode
by ron minnich (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Maximilian Brune, Philipp Hug. ron minnich has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81031?usp=email ) Change subject: mb/sifive/sifive-unmatched: add support for spi1 x4 mode ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81031/comment/bdd26042_2fcc5fa0 : PS2, Line 7: SiFive Unmatched: add support for spi1 x4 mode > use mb/sifive/sifive-unmatched: prefix? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81031?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida7f195eb6e4fc85018ceb83cf317595127c4af5 Gerrit-Change-Number: 81031 Gerrit-PatchSet: 3 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 20:13:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Philipp Hug <philipp(a)hug.cx> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/sifive/sifive-unmatched: add support for spi1 x4 mode
by ron minnich (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Maximilian Brune, ron minnich. Hello Maximilian Brune, Philipp Hug, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81031?usp=email to look at the new patch set (#3). Change subject: mb/sifive/sifive-unmatched: add support for spi1 x4 mode ...................................................................... mb/sifive/sifive-unmatched: add support for spi1 x4 mode Tested on an unmatched, both SPI1 x1 and x4 work now. Change-Id: Ida7f195eb6e4fc85018ceb83cf317595127c4af5 Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> --- M src/mainboard/sifive/hifive-unmatched/cbfs_spi.c 1 file changed, 25 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/81031/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81031?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida7f195eb6e4fc85018ceb83cf317595127c4af5 Gerrit-Change-Number: 81031 Gerrit-PatchSet: 3 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: brox: ish: Add Kconfigs for ISH
by Yuval Peress (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Li1 Feng, Martin L Roth, Shelley Chen. Yuval Peress has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81050?usp=email ) Change subject: brox: ish: Add Kconfigs for ISH ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brox/Kconfig.name: https://review.coreboot.org/c/coreboot/+/81050/comment/af76a2dc_86d71f70 : PS2, Line 9: > Nit: add another space to line up with above? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/81050?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic670d550a9aaad64e52489d895b8aac2aee4b5ed Gerrit-Change-Number: 81050 Gerrit-PatchSet: 3 Gerrit-Owner: Yuval Peress <peress(a)google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-Comment-Date: Tue, 05 Mar 2024 19:39:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: brox: ish: Add Kconfigs for ISH
by Yuval Peress (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Li1 Feng, Shelley Chen, Yuval Peress. Hello Li1 Feng, Shelley Chen, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81050?usp=email to look at the new patch set (#3). Change subject: brox: ish: Add Kconfigs for ISH ...................................................................... brox: ish: Add Kconfigs for ISH Modeled after the Rex Kconfigs for ISH. Change-Id: Ic670d550a9aaad64e52489d895b8aac2aee4b5ed Signed-off-by: Yuval Peress <peress(a)google.com> --- M src/mainboard/google/brox/Kconfig M src/mainboard/google/brox/Kconfig.name 2 files changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/81050/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81050?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic670d550a9aaad64e52489d895b8aac2aee4b5ed Gerrit-Change-Number: 81050 Gerrit-PatchSet: 3 Gerrit-Owner: Yuval Peress <peress(a)google.com> Gerrit-Reviewer: Li1 Feng <li1.feng(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yuval Peress <peress(a)google.com> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Li1 Feng <li1.feng(a)intel.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/intel/common/mp_init: Fix USE_INTEL_FSP_MP_INIT use-case
by Jérémy Compostella (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Arthur Heymans, Subrata Banik. Jérémy Compostella has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80575?usp=email ) Change subject: soc/intel/common/mp_init: Fix USE_INTEL_FSP_MP_INIT use-case ...................................................................... Patch Set 6: (1 comment) Patchset: PS5: > don't you see a compilation error due to unavailability of `init_cpus()` while using USE_INTEL_FSP_ […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/80575?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb8cdfef7b4279da2c7dff344c95fe446a605934 Gerrit-Change-Number: 80575 Gerrit-PatchSet: 6 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Comment-Date: Tue, 05 Mar 2024 19:35:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: drivers/intel/fsp2_0: Add "silicon" to the multiphase callback name
by Jérémy Compostella (Code Review) 05 Mar '24

05 Mar '24

Attention is currently required from: Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik, Tarun. Hello Andrey Petrov, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Ronak Kanabar, Subrata Banik, Tarun, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/81094?usp=email to look at the new patch set (#3). Change subject: drivers/intel/fsp2_0: Add "silicon" to the multiphase callback name ...................................................................... drivers/intel/fsp2_0: Add "silicon" to the multiphase callback name The `platform_fsp_multi_phase_init_cb' callback is specific to FSP-S, let's rename it 'platform_fsp_silicon_multi_phase_init_cb' to avoid any confusion. Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/intel/fsp2_0/include/fsp/api.h M src/drivers/intel/fsp2_0/silicon_init.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/meteorlake/fsp_params.c M src/soc/intel/tigerlake/fsp_params.c 5 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/81094/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/81094?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I86b69e2069f08023e6f48464f6df4593710aa9ee Gerrit-Change-Number: 81094 Gerrit-PatchSet: 3 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit March 2024