coreboot-gerrit March 2024

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[S] Change in coreboot[main]: drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug
by Shuo Liu (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Arthur Heymans. Shuo Liu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80579?usp=email ) Change subject: drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug ...................................................................... Patch Set 7: (1 comment) File src/drivers/intel/fsp2_0/memory_init.c: https://review.coreboot.org/c/coreboot/+/80579/comment/4e4d2f3d_8ecdc9d7 : PS7, Line 174: & CONFIG(… [View More]

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[XS] Change in coreboot[main]: drivers/intel/fsp2_0: Use DECLARE_REGION for FSP_SPEC_VIOLATION_ XEON...
by Shuo Liu (Code Review) 06 Mar '24

06 Mar '24

Shuo Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81097?usp=email ) Change subject: drivers/intel/fsp2_0: Use DECLARE_REGION for FSP_SPEC_VIOLATION_ XEON_SP_HEAP_WORKAROUND ...................................................................... drivers/intel/fsp2_0: Use DECLARE_REGION for FSP_SPEC_VIOLATION_ XEON_SP_HEAP_WORKAROUND Fixes: 0201d98("drivers/intel/fsp: Work around multi-socket Xeon-SP pipe init bug") Change-Id: … [View More]

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[S] Change in coreboot[main]: mb/sifive/sifive-unmatched: add support for spi1 x4 mode
by Felix Singer (Code Review) 06 Mar '24

06 Mar '24

Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81031?usp=email ) Change subject: mb/sifive/sifive-unmatched: add support for spi1 x4 mode ...................................................................... mb/sifive/sifive-unmatched: add support for spi1 x4 mode Tested on an unmatched, both SPI1 x1 and x4 work now. Change-Id: Ida7f195eb6e4fc85018ceb83cf317595127c4af5 Signed-off-by: Ronald G Minnich <rminnich(a)gmail.com> Reviewed-on: https://… [View More]review.coreboot.org/c/coreboot/+/81031 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Philipp Hug <philipp(a)hug.cx> Reviewed-by: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> --- M src/mainboard/sifive/hifive-unmatched/cbfs_spi.c 1 file changed, 25 insertions(+), 11 deletions(-) Approvals: Felix Singer: Looks good to me, approved build bot (Jenkins): Verified Philipp Hug: Looks good to me, but someone else must approve diff --git a/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c b/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c index 787d8e7..f47da22 100644 --- a/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c +++ b/src/mainboard/sifive/hifive-unmatched/cbfs_spi.c @@ -116,15 +116,34 @@ if (spi_flash_init_done == true) return; - uint32_t m = read32((uint32_t *)FU740_MSEL); + uint32_t m = read32((uint32_t *)FU740_MSEL) & 0xf; + printk(BIOS_DEBUG, "%s MSEL %#x\n", __func__, m); + + // We have not yet found a way to reliably program the + // on-board SPI part (sifive neglected to put a diode on vcc ...) + // Once we work that out, we can test this code. + // It is left here as a hint of what needs to be done. // Pass the information of the flash read operation to the spi controller - //.pad_cnt = 6, - if (MSEL_SPI0x4(m) || MSEL_SPI1x4(m)) { + if (MSEL_SPI0x4(m)) { + die("SPI0x4 is not supported yet"); //config.ffmt_config.data_proto = FU740_SPI_PROTO_Q; //config.ffmt_config.cmd_code = 0x6B; // Quad output read //.cmd_code = 0xec, + //.pad_cnt = 6, } - if (MSEL_SPI1x1(m)) { + if (MSEL_SPI1x4(m)) { + printk(BIOS_DEBUG, "%s SPI1x4 1\n", __func__); + fu740_spi_configs[1].ffmt_config.data_proto = FU740_SPI_PROTO_Q; + fu740_spi_configs[1].ffmt_config.cmd_code = 0x6b; // quad + if (spi_flash_probe(1, 0, &spi_flash)) { + printk(BIOS_EMERG, "SPI1x4 failed to init SPI flash\n"); + return; + } + if (fu740_spi_setup(&spi_flash.spi) == -1) { + printk(BIOS_EMERG, "SPI1x4 failed to configure mmap for SPI flash\n"); + } + printk(BIOS_DEBUG, "%s SPI1x4 2\n", __func__); + } else if (MSEL_SPI1x1(m)) { printk(BIOS_DEBUG, "%s 1\n", __func__); fu740_spi_configs[1].ffmt_config.data_proto = FU740_SPI_PROTO_S; fu740_spi_configs[1].ffmt_config.cmd_code = 0x03; // Normal read @@ -133,17 +152,12 @@ printk(BIOS_EMERG, "failed to init SPI flash\n"); return; } - // initialize soc spi controller - //if (fu740_spi_setup(&spi1_flash.spi) == -1) { - // printk(BIOS_EMERG, "failed to configure mmap for SPI flash\n"); - //} - //hexdump((void*)0x10041000, 0x100); - //hexdump((void*)0x30000000, 0x100); printk(BIOS_DEBUG, "%s 2\n", __func__); } else if (MSEL_SPI2SD(m)) { spi_sdcard_init(&spi2_sdcard, 2, 0); } else { - die("Wrong configuration of MSEL\n"); + printk(BIOS_EMERG, "MSEL: %#02x: ", m); + die("unsupported configuration of MSEL\n"); } spi_flash_init_done = true; -- To view, visit https://review.coreboot.org/c/coreboot/+/81031?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida7f195eb6e4fc85018ceb83cf317595127c4af5 Gerrit-Change-Number: 81031 Gerrit-PatchSet: 4 Gerrit-Owner: ron minnich <rminnich(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged [View Less]

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[S] Change in coreboot[main]: mb/sifive/sifive-unmatched: add support for spi1 x4 mode
by Felix Singer (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Maximilian Brune, Philipp Hug, ron minnich. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81031?usp=email ) Change subject: mb/sifive/sifive-unmatched: add support for spi1 x4 mode ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/81031/comment/a922877d_b0a55afb : PS3, Line 9: Tested on an … [View More]

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[S] Change in coreboot[main]: brox: ish: Add Kconfigs for ISH
by Li1 Feng (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Martin L Roth, Shelley Chen, Yuval Peress. Li1 Feng has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81050?usp=email ) Change subject: brox: ish: Add Kconfigs for ISH ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brox/Kconfig: https://review.coreboot.org/c/coreboot/+/81050/comment/e907b99e_c253f1ed : PS3, Line 10: select DRIVERS_INTEL_ISH Line … [View More]

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[XS] Change in coreboot[main]: src/acpi: Increase ACPI revision from 6.0 to 6.4
by minyu li (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Cliff Huang, Felix Singer, Lance Zhao, Paul Menzel, Tim Wawrzynczak. minyu li has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80781?usp=email ) Change subject: src/acpi: Increase ACPI revision from 6.0 to 6.4 ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/80781/comment/034c691a_c50a9230 : PS1, Line 9: Modify ACPI … [View More]

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[XS] Change in coreboot[main]: vc/amd/opensil/genoa_poc/memmap: use get_top_of_mem_below_4gb
by Varshit Pandya (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Felix Held. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81092?usp=email ) Change subject: vc/amd/opensil/genoa_poc/memmap: use get_top_of_mem_below_4gb ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81092?usp=email To unsubscribe, or for help writing mail filters, visit https://review.… [View More]

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[XS] Change in coreboot[main]: vc/amd/opensil/genoa_poc/memmap: use GiB define
by Varshit Pandya (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Felix Held. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81093?usp=email ) Change subject: vc/amd/opensil/genoa_poc/memmap: use GiB define ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81093?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings… [View More]

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[S] Change in coreboot[main]: mb/amd/onyx_poc/devicetree: explicitly assign PCIe engine type
by Varshit Pandya (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Felix Held, Matt DeVillier. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81095?usp=email ) Change subject: mb/amd/onyx_poc/devicetree: explicitly assign PCIe engine type ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/81095?usp=email To unsubscribe, or for help writing mail filters, visit https:… [View More]

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[S] Change in coreboot[main]: mb/google/brya/var/omniknight: remove Implement touchscreen power seq...
by Jamie Chen (Code Review) 06 Mar '24

06 Mar '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Ivan Chen, Kapil Porwal, Martin L Roth, Matt DeVillier, Nick Vaccaro, Paul Menzel, Subrata Banik. Jamie Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80769?usp=email ) Change subject: mb/google/brya/var/omniknight: remove Implement touchscreen power sequencing ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: > if the issue … [View More]is the touchscreen being powered on before BL_EN, then I ask again: […] From Schematic, although BL_EN is output from the CPU, it seems that the BL_EN pin cannot be controlled from gpio.c. -- To view, visit https://review.coreboot.org/c/coreboot/+/80769?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I66f4a7915f135927fbc0a16254dece202dfc23a2 Gerrit-Change-Number: 80769 Gerrit-PatchSet: 7 Gerrit-Owner: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Reviewer: Derek Huang <derekhuang(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ivan Chen <yulunchen(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Ivan Chen <yulunchen(a)google.com> Gerrit-Comment-Date: Wed, 06 Mar 2024 01:10:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: comment [View Less]

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coreboot-gerrit March 2024